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| 101 innovation drive san jose, ca 95134 www.altera.com stratix iv device handbook volume 1 siv5v1-4.1
copyright ? 2010 altera corporation. all rights reserved. altera, the programmable solutions company, the stylized altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of their respective holders. altera products are protected under numerous u.s. and foreign patents and pending ap- plications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specification s in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibilit y or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera cu stomers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services . ? march 2010 altera corporation stratix iv device handbook volume 1 contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii additional information about this handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-xv how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-xv typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-xv section i. device core revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 chapter 1. stratix iv device family overview feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 stratix iv gx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 stratix iv e device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 stratix iv gt devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 architecture features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 high-speed transceiver features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 highest aggregate data bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 wide range of protocol support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 diagnostic features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 signal integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 fpga fabric and i/o features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 device core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 digital signal processing (dsp) blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 i/o features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 high-speed differential i/o with dpa and soft-cdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 external memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 integrated software platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 chapter 2. logic array blocks and adaptive logic modules in stratix iv devices logic array blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 lab interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 lab control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 iv contents stratix iv device handbook volume 1 ? march 2010 altera corporation adaptive logic modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 alm operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 extended lut mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 arithmetic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 shared arithmetic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 lut-register mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 register chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 alm interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 clear and preset logic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 lab power management techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 chapter 3. trimatrix embedded memory blocks in stratix iv devices overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 trimatrix memory block types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 parity bit support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 byte enable support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 packed mode support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 address clock enable support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 mixed width support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 asynchronous clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 error correction code (ecc) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 memory modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 single-port ram mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 simple dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 true dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 shift-register mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 rom mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 clocking modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 independent clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 input/output clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 read/write clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 single clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 selecting trimatrix memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 conflict resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 read-during-write behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 same-port read-during-write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 mixed-port read-during-write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 power-up conditions and memory initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 chapter 4. dsp blocks in stratix iv devices stratix iv dsp block overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 stratix iv simplified dsp operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 stratix iv operational modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 contents v ? march 2010 altera corporation stratix iv device handbook volume 1 stratix iv dsp block resource descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 input registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 multiplier and first-stage adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 pipeline register stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 second-stage adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 rounding and saturation stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 second adder and output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 stratix iv operational mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 independent multiplier modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 9-, 12-, and 18-bit multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 36-bit multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 double multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 two-multiplier adder sum mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 18 x 18 complex multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 four-multiplier adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 high-precision multiplier adder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 multiply accumulate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 shift modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 rounding and saturation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 dsp block control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 chapter 5. clock networks and p lls in stratix iv devices clock networks in stratix iv devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 global clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 regional clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 periphery clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 clock sources per quadrant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 clock regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 clock network sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 dedicated clock input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 labs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 pll clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 clock input connections to the plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 clock output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 clock control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 clock enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 clock source control for plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 cascading plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 vi contents stratix iv device handbook volume 1 ? march 2010 altera corporation plls in stratix iv devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 stratix iv pll hardware overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 pll clock i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 pll control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 pfdena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 areset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 clock feedback modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 source synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 source-synchronous mode for lvds compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 no-compensation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 zero-delay buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 external feedback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 clock multiplication and division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 post-scale counter cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 programmable duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 programmable phase shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 programmable bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 spread-spectrum tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 clock switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 automatic clock switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 manual clock switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 pll reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 pll reconfiguration hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 post-scale counters (c0 to c9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 scan chain description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 charge pump and loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48 bypassing a pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 dynamic phase-shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 pll specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 chapter revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 section ii. i/o interfaces revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii-1 chapter 6. i/o features in stratix iv devices i/o standards support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 i/o standards and voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 i/o banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 modular i/o banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 contents vii ? march 2010 altera corporation stratix iv device handbook volume 1 i/o structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 3.3-v i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 external memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 high-speed differential i/o with dpa support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 current strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 i/o delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 programmable ioe delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 programmable output buffer delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 open-drain output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 bus hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 differential output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 multivolt i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 on-chip termination support and i/o termination schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 on-chip series (r s ) termination without calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 on-chip series termination with calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 left-shift series termination control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 on-chip parallel termination with calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -27 expanded on-chip series termination with calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 dynamic on-chip termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 lvds input oct (r d ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 summary of oct assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 oct calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 oct calibration block location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 sharing an oct calibration block on multiple i/o banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 oct calibration block modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 oct calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 serial data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 example of using multiple oct calibration blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 r s calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 termination schemes for i/o standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 single-ended i/o standards termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 differential i/o standards termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 lvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 differential lvpecl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 rsds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 mini-lvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 i/o bank restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 non-voltage-referenced standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 voltage-referenced standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 mixing voltage-referenced and non-voltage-referenced standards . . . . . . . . . . . . . . . . . . . . . 6-46 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 chapter 7. external memory interfaces in stratix iv devices memory interfaces pin support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 using the r up and r dn pins in a dqs/dq group used for memory interfaces . . . . . . . . . . . . . . . 7-27 combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface . . . . . . . . . . . 7-27 rules to combine groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 viii contents stratix iv device handbook volume 1 ? march 2010 altera corporation stratix iv external memory interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 dqs phase-shift circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 dll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 phase offset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42 dqs logic block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44 dqs delay chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45 update enable circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45 dqs postamble circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 leveling circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47 dynamic on-chip termination control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49 i/o element registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49 delay chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53 i/o configuration block and dqs configuration block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-55 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-57 chapter 8. high-speed differential i/o interfaces and dpa in stratix iv devices overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 locations of the i/o banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 lvds channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 lvds serdes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 altlvds port list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 differential transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 programmable v od and programmable pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 programmable vod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 programmable pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 differential receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 differential i/o termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 receiver hardware blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 dpa block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 data realignment block (bit slip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 receiver data path modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 non-dpa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 dpa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 soft-cdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 lvds interface with the use external pll option enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8- 25 left and right plls (pll_lx and pll_rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28 stratix iv clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 source-synchronous timing budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 differential data orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 differential i/o bit position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 transmitter channel-to-channel skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 receiver skew margin for non-dpa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 contents ix ? march 2010 altera corporation stratix iv device handbook volume 1 differential pin placement guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 guidelines for dpa-enabled differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 dpa-enabled channels and single-ended i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 dpa-enabled channel driving distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 using corner and center left and right plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 -38 using both center left and right plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39 guidelines for dpa-disabled differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 dpa-disabled channels and single-ended i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 dpa-disabled channel driving distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41 using corner and center left and right plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 -41 using both center left and right plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43 chapter revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44 section iii. system integration revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii-1 chapter 9. hot socketing and power-on reset in stratix iv devices stratix iv hot-socketing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 stratix iv devices can be driven before power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 i/o pins remain tri-stated during power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 insertion or removal of a stratix iv device from a powered-up system . . . . . . . . . . . . . . . . . . . . . . 9-2 hot-socketing feature implementation in stratix iv devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 power-on reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 power-on reset specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 chapter 10. configuration, design security, and remote system upgrades in stratix iv devices overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 configuration devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 configuration schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 configuration features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 power-on reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 vccpgm pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 vccpd pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 fast passive parallel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 fpp configuration using a max ii device as an external host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 fpp configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 fpp configuration using a microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 fast active serial configuration (serial configuration devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10- 15 estimating active serial configuration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 programming serial configuration devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 guidelines for connecting serial configuration devices on an as interface . . . . . . . . . . . . . . . . . 10-24 passive serial configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 ps configuration using a max ii device as an external host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 ps configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 ps configuration using a microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 ps configuration using a download cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 jtag configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34 jam stapl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 device configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 configuration data decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47 x contents stratix iv device handbook volume 1 ? march 2010 altera corporation remote system upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-49 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-50 enabling remote update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-51 configuration image types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-52 remote system upgrade mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-53 remote update mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-53 dedicated remote system upgrade circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-55 remote system upgrade registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-56 remote system upgrade control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-57 remote system upgrade status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-58 remote system upgrade state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-59 user watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-60 quartus ii software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-60 altremote_update megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-61 design security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-61 stratix iv security protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-62 security against copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-62 security against reverse engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-62 security against tampering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-63 aes decryption block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-63 flexible security key storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-63 stratix iv design security solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-64 security modes available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65 volatile key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65 non-volatile key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65 non-volatile key with tamper protection bit set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 5 no key operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65 supported configuration schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-66 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-67 chapter 11. seu mitigation in stratix iv devices error detection fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 configuration error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 user mode error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 automated single-event upset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 error detection pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 crc_error pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 error detection block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 error detection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 error detection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 recovering from crc errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 chapter 12. jtag boundary-scan testing in stratix iv devices bst architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 bst operation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 i/o voltage support in a jtag chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 bst circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 bsdl support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 contents xi ? march 2010 altera corporation stratix iv device handbook volume 1 chapter 13. power management in stratix iv devices overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 stratix iv power technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 programmable power technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 stratix iv external power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 temperature sensing diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 external pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 xii contents stratix iv device handbook volume 1 ? march 2010 altera corporation ? march 2010 altera corporation stratix iv device handbook volume 1 chapter revision dates the chapters in this book, stratix iv device handbook volume 1 , were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1 stratix iv device family overview revised: march 2010 part number: siv51001-3.1 chapter 2 logic array blocks and adaptive logic modules in stratix iv devices revised: november 2009 part number: siv51002-3.0 chapter 3 trimatrix embedded memory blocks in stratix iv devices revised: march 2010 part number: siv51003-3.1 chapter 4 dsp blocks in stratix iv devices revised: november 2009 part number: siv51004-3.0 chapter 5 clock networks and plls in stratix iv devices revised: march 2010 part number: siv51005-3.1 chapter 6 i/o features in stratix iv devices revised: march 2010 part number: siv51006-3.1 chapter 7 external memory interfaces in stratix iv devices revised: march 2010 part number: siv51007-3.1 chapter 8 high-speed differential i/o interfaces and dpa in stratix iv devices revised: march 2010 part number: siv51008-3.1 chapter 9 hot socketing and power-on reset in stratix iv devices revised: march 2010 part number: siv51009-3.1 chapter 10 configuration, design security, and remote system upgrades in stratix iv devices revised: march 2010 part number: siv51010-3.1 chapter 11 seu mitigation in stratix iv devices revised: march 2010 part number: siv51011-3.1 xiv chapter revision dates stratix iv device handbook volume 1 ? march 2010 altera corporation chapter 12 jtag boundary-scan testing in stratix iv devices revised: march 2010 part number: siv51012-3.1 chapter 13 power management in stratix iv devices revised: march 2010 part number: siv51013-3.1 ? march 2010 altera corporation stratix iv device handbook volume 1 additional information about this handbook this handbook provides comprehensive information about the altera ? stratix ? iv family of devices. how to contact altera for the most up-to-date information about altera products, see the following table. typographic conventions the following table shows the typographic conventions that this document uses. contact (note 1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature non-technical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicates command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf . italic type with initial capital letters indicates document titles. for example, an 519: stratix iv design guidelines. italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, info?xvi additional information stratix iv device handbook volume 1 ? march 2010 altera corporation courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . active-low signals are denoted by suffix n . for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). 1., 2., 3., and a., b., c., and so on. numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. r the angled arrow instructs you to press enter . f the feet direct you to more information about a particular topic. visual cue meaning ? march 2010 altera corporation stratix iv device handbook volume 1 section i. device core this section provides a complete overview of all features relating to the stratix ? iv device family, which is the most architecturally advanced, high-performance, low-power fpga in the market place. this section includes the following chapters: revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook. i?2 section i: device core stratix iv device handbook volume 1 ? march 2010 altera corporation ? march 2010 altera corporation stratix iv device handbook volume 1 1. stratix iv device family overview altera ? stratix ? iv fpgas deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. stratix iv fpgas are based on the taiwan semiconductor manufacturing company (tsmc) 40-nm process technology and surpass all other high-end fpgas, with the highest logic density, most transceivers, and lowest power requirements. the stratix iv device family contains three optimized variants to meet different application requirements: f r fr c r vc fr rfr upcoming stratix iv device features document. f r fr c crr stratix iv device handbook , refer to the addendum to the stratix iv device handbook chapter. this chapter contains the following sections: 1?2 chapter 1: stratix iv device family overview feature summary stratix iv device handbook volume 1 ? march 2010 altera corporation feature summary the following list summarizes the stratix iv device family features: f r r fr rfr pci express compiler user guide . chapter 1: stratix iv device family overview 1?3 feature summary ? march 2010 altera corporation stratix iv device handbook volume 1 stratix iv gx devices stratix iv gx devices provide up to 48 full-duplex cdr-based transceiver channels per device: 1 c r f rcvr c r vc vr w vc c r r fr c rcvr c c vc rfr 11 111 1 r r fr rcvr rccr rfr stratix iv transceiver architecture chapter. figure 1?1 shows a high-level stratix iv gx chip view. figure 1?1. stratix iv gx chip view (note 1) note to figure 1?1 : (1) resource counts vary with device selection, package selection, or both. general purpose i/o and memory interface 600 mbps-8.5 gbps cdr-based transceiver general purpose i/o and 150 mbps-1.6 gbps lvds interface with dpa and soft-cdr transceiver block transceiver block transceiver block transceiver block pci express hard ip block pci express hard ip block pci express hard ip block pci express hard ip block general purpose i/o and memory interface pll pll pll pll pll pll general purpose i/o and memory interface general purpose i/o and memory interface pll pll fpga fabric (logic elements, dsp, embedded memory, clock networks) transceiver block general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr pll pll pll pll transceiver block transceiver block transceiver block transceiver block general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr 1?4 chapter 1: stratix iv device family overview feature summary stratix iv device handbook volume 1 ? march 2010 altera corporation stratix iv e device stratix iv e devices provide an excellent solution for applications that do not require high-speed cdr-based transceivers, but are logic, user i/o, or memory intensive. figure 1?2 shows a high-level stratix iv e chip view. figure 1?2. stratix iv e chip view (note 1) note to figure 1?2 : (1) resource counts vary with device selection, package selection, or both. general purpose i/o and memory interface general purpose i/o and 150 mbps-1.6 gbps lvds interface with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and memory interface pll pll pll pll pll pll pll pll pll pll general purpose i/o and memory interface general purpose i/o and memory interface pll pll fpga fabric (logic elements, dsp, embedded memory, clock networks) general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr chapter 1: stratix iv device family overview 1?5 feature summary ? march 2010 altera corporation stratix iv device handbook volume 1 stratix iv gt devices stratix iv gt devices provide up to 48 cdr-based transceiver channels per device: 1 c r f rcvr c r vc vr w vc c r r fr c rcvr c c vc rfr 1 11 1 r r fr r vc rcvr rccr rfr stratix iv transceiver architecture chapter. figure 1?3 shows a high-level stratix iv gt chip view. figure 1?3. stratix iv gt chip view (note 1) note to figure 1?3 : (1) resource counts vary with device selection, package selection, or both. general p u rpose i/o and memory interface 600 mbps-11.3 gbps cdr-b ased transceiv er general p u rpose i/o and up to 1.6 gbps l v ds interface w ith dpa and soft-cdr pci express hard ip block pci express hard ip block pci express hard ip block pci express hard ip block transcei v er block transcei v er block transcei v er block transcei v er block general p u rpose i/o and memory interface pll pll pll pll pll pll general p u rpose i/o and memory interface general p u rpose i/o and memory interface pll pll fpga fabric (logic elements, dsp, emb edded memory, clock netw orks) transcei v er block general p u rpose i/o and high-speed l vds i/o w ith dpa and soft cdr general p u rpose i/o and high-speed l vds i/o with dpa and soft cdr pll pll pll pll general p u rpose i/o and high-speed l vds i/o with dpa and soft cdr general p u rpose i/o and high-speed l vds i/o with dpa and soft cdr general p u rpose i/o and high-speed l vds i/o with dpa and soft cdr transcei v er block transcei v er block transcei v er block transcei v er block 1?6 chapter 1: stratix iv device family overview architecture features stratix iv device handbook volume 1 ? march 2010 altera corporation architecture features the stratix iv device family features are divided into high-speed transceiver features and fpga fabric and i/o features. 1 rcvr fr r r vc high-speed transceiver features the following sections describe high-speed transceiver features for stratix iv gx and stratix iv gt devices. highest aggregate data bandwidth up to 48 full-duplex transceiver channels supporting data rates up to 8.5 gbps in stratix iv gx devices and up to 11.3 gbps in stratix iv gt devices. wide range of protocol support physical layer support for the following serial protocols: f r r fr rfr pci express compiler user guide . chapter 1: stratix iv device family overview 1?7 architecture features ? march 2010 altera corporation stratix iv device handbook volume 1 xaui/higig support compliant to ieee802.3ae specification embedded state machine circuitry to convert xgmii idle code groups (||i||) to and from idle ordered sets (||a||, ||k||, ||r||) at the transmitter and receiver, respectively 8b/10b encoder and decoder, receiver synchronization state machine, lane deskew, and 100 ppm clock compensation circuitry gbe support compliant to ieee802.3-2005 specification automatic idle ordered set (/i1/, /i2/) generation at the transmitter, depending on the current running disparity 8b/10b encoder and decoder, receiver synchronization state machine, and 100 ppm clock compensation circuitry support for other protocol features such as msb-to-lsb transmission in sonet/sdh configuration and spread-spectrum clocking in pcie configurations diagnostic features serial loopback from the transmitter serializer to the receiver cdr for transceiver pcs and pma diagnostics reverse serial loopback pre- and post-cdr to transmitter buffer for physical link diagnostics loopback master and slave capability in pci express hard ip blocks f for more information, refer to the pci express compiler user guide . signal integrity stratix iv devices simplify the challenge of signal integrity through a number of chip, package, and board-level enhancements to enable efficient high-speed data transfer into and out of the device. these enhancements include: programmable 3-tap transmitter pre-emphasis with up to 8,192 pre-emphasis levels to compensate for pre-cursor and post-cursor inter-symbol interference (isi) up to 900% boost capa bility on the first pre-emphasis post-tap user-controlled and adaptive 4-stage receiver equalization with up to 16 db of high-frequency gain on-die power supply regulators for transmitter and receiver phase-locked loop (pll) charge pump and voltage controlled oscillator (vco) for superior noise immunity on-package and on-chip power supply decoupling to satisfy transient current requirements at higher frequencies, thereby reducing the need for on-board decoupling capacitors calibration circuitry for transmitter and receiver on-chip termination (oct) resistors 1?8 chapter 1: stratix iv device family overview architecture features stratix iv device handbook volume 1 ? march 2010 altera corporation fpga fabric and i/o features the following section describes the stratix iv fpga fabric and i/o features. device core features embedded memory digital signal processing (dsp) blocks clock networks chapter 1: stratix iv device family overview 1?9 architecture features ? march 2010 altera corporation stratix iv device handbook volume 1 plls three to 12 plls per device supporting spread-spectrum input tracking, programmable bandwidth, clock switchover, dynamic reconfiguration, and delay compensation on-chip pll power supply regulators to minimize noise coupling i/o features sixteen to 24 modular i/o banks per device with 24 to 48 i/os per bank designed and packaged for optimal simultaneous switching noise (ssn) performance and migration capability support for a wide range of industry i/o standards, including single-ended (lvttl/cmos/pci/pcix), differential (lvds/mini-lvds/rsds), voltage-referenced single-ended and differential (sstl/hstl class i/ii) i/o standards on-chip series (r s ) and on-chip parallel (r t ) termination with auto-calibration for single-ended i/os and on-chip differential (r d ) termination for differential i/os programmable output drive strength, slew rate control, bus hold, and weak pull-up capability for single-ended i/os user i/o:gnd:v cc ratio of 8:1:1 to reduce loop inductance in the package?pcb interface programmable transmitter differential output voltage (v od ) and pre-emphasis for high-speed lvds i/o high-speed differential i/o with dpa and soft-cdr dedicated circuitry on the left and right sides of the device to support differential links at data rates from 150 mbps to 1.6 gbps up to 98 differential serdes in stratix iv gx devices, up to 132 differential serdes in stratix iv e devices, and up to 47 differential serdes in stratix iv gt devices dpa circuitry at the receiver automatically compensates for channel-to-channel and channel-to-clock skew in source synchronous interfaces soft-cdr circuitry at the receiver allows implementation of asynchronous serial interfaces with embedded clocks at up to 1.6 gbps data rate (sgmii and gbe) external memory interfaces support for existing and emerging memory interface standards such as ddr sdram, ddr2 sdram, ddr3 sdram, qdrii sram, qdrii+ sram, and rldram ii ddr3 up to 1,067 mbps/533 mhz programmable dq group widths of 4 to 36 bits (includes parity bits) dynamic oct, trace mismatch compensation, read-write leveling, and half-rate register capabilities provide a robust external memory interface solution 1?10 chapter 1: stratix iv device family overview architecture features stratix iv device handbook volume 1 ? march 2010 altera corporation system integration all stratix iv devices support hot socketing four configuration modes: passive serial (ps) fast passive parallel (fpp) fast active serial (fas) jtag configuration ability to perform remote system upgrades 256-bit advanced encryption standard (aes) encryption of configuration bits protects your design against copying, reverse engineering, and tampering built-in soft error detection for configuration ram cells f for more information about how to connect the pll, external memory interfaces, i/o, high-speed differential i/o, power, and the jtag pins to pcb, refer to the stratix iv gx and stratix iv e device family pin connection guidelines and the stratix iv gt device family pin connection guidelines . chapter 1: stratix iv device family overview 1?11 architecture features ? march 2010 altera corporation stratix iv device handbook volume 1 table 1?1 lists the stratix iv gx device features. tab le 1 ?1 . stratix iv gx device features (part 1 of 2) feature ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 package option f780 f1152 f780 f1152 f780 f1152 f1517 f780 f1152 f1517 f780 f1152 f1517 f1760 f1932 f780 f1152 f1517 f1760 f1932 f1152 f1517 f1760 f1932 alms 29,040 42,240 70,300 91,200 116,480 141,440 212,480 les 72,600 105,600 175,750 228,000 291,200 353,600 531,200 0.6 gbps- 8.5 gbps transceivers (pma + pcs) (1) ?16? ?16? ?1624? ?1624? ?16242432? ?162424 32 16242432 0.6 gbps- 6.5 gbps transceivers (pma + pcs) (1) 8 ? 8 16? 8 16 ?? 8 16 ?? 16 16???? 16 16??? ? ???? pma-only cmu channels (0.6 gbps- 6.5 gbps) ?8??8??812??812??8121216??8121216 8121216 pci express hard ip blocks 12121 2 1 2 2 4 2 42 4 high-speed lvd s serdes (up to 1.6 gbps) (4) 28 56 28 28 56 28 44 88 28 44 88 ? 44 88 88 98 ? 44 88 88 98 44 88 88 98 spi-4.2 links 1 1 1 2 4 1 2 4 ? 2 4 ? 2 4 2 4 1?12 chapter 1: stratix iv device family overview architecture features stratix iv device handbook volume 1 m9k blocks (256 36 bits) 462 660 950 1,235 936 1,248 1,280 m144k blocks (2048 72 bits) 16 16 20 22 36 48 64 total memory (mlab+m9k+ m144k) kbits 7,370 9,564 13,627 17,133 17,248 22,564 27,376 embedded multipliers 18 18 (2) 384 512 920 1,288 832 1,040 1,024 1,024 plls 343436836846812124681212681212 user i/os (3) 372 488 372 372 488 372 564 564 744 372 564 564 744 289 564 564 744 880 920 289 564 564 744 880 920 564 744 880 920 speed grade (fastest to slowest) (5) ?2 , ?3, ?4 ?2, ?3, ?4 ?2 , ?3, ?4 ?2 , ?3, ?4 ?2, ?3, ?4 ?2 , ?3, ?4 ?2 , ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2 , ?3, ?4 ?2 , ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2 , ?3, ?4 ?2 , ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2 , ?3, ?4 ?2 , ?3 , ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 notes to table 1?1 : (1) the total number of transceivers is divided equally between the left and right side of each device, except for the devices i n the f780 package. these d evices have eight transceiver channels located only on the right side of the device. (2) four multiplier adder mode. (3) the user i/os count from pin-out files includes all general purpose i/o, dedicated clock pins, and dual purpose configuratio n pins. transceiver pins and dedicated configuration pins are not included in the pin count. (4) total pairs of high-speed lvds serdes take the lowest channel count of r x /t x . (5) the difference between the stratix iv gx devices in the ? 2 and ? 2 speed grades is the number of available transceiver channels. the ? 2 device allows you to use the transceiver cmu blocks as transceiver channels. the ? 2 device does not allow you to use the cmu blocks as transceiver channels. in addition to the reduction of available transceiver channels in the stratix iv gx ? 2x device, the data rates in the ? 2 device are limited to 6.5 gbps. ta ble 1? 1. stratix iv gx device features (part 2 of 2) feature ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 package option f780 f1152 f780 f1152 f780 f1152 f1517 f780 f1152 f1517 f780 f1152 f1517 f1760 f1932 f780 f1152 f1517 f1760 f1932 f1152 f1517 f1760 f1932 chapter 1: stratix iv device family overview 1?13 architecture features ? march 2010 altera corporation stratix iv device handbook volume 1 table 1?2 summarizes the stratix iv gx device package options. 1 c c rc fr r r c ccr f r crr rr r frc power delivery network design tool for stratix iv devices accounts for the on-package decoupling and reflects the reduced requirements for pcb decoupling capacitors. table 1?3 lists the stratix iv gx device on-package decoupling information. tab le 1 ?2 . stratix iv gx device package options (note 1) device f780 (29 mm 29 mm) (5) f1152 (35 mm 35 mm) (5) f1152 (35 mm 35 mm) (4) , (6) f1517 (40 mm 40 mm) (4) , (6) f1760 (42.5 mm 42.5 mm) (6) f1932 (45 mm 45 mm) (6) ep4sgx70 df29 ? ? hf35 ? ? ? ? ep4sgx110 df29 ? ff35 hf35 ? ? ? ? ep4sgx180 df29 ? ff35 ? hf35 kf40 ? ? ep4sgx230 df29 ? ff35 ? hf35 kf40 ? ? ep4sgx290 ? fh29 (2) ff35 ? hf35 kf40 kf43 nf45 ep4sgx360 ? fh29 (2) ff35 ? hf35 kf40 kf43 nf45 ep4sgx530 ? ? ? ? hh35 (3) kh40 (3) kf43 nf45 notes to ta bl e 1? 2 : (1) device packages in the same column and marked unde r the same arrow sign have vertical migration capability. (2) the 780-pin ep4sgx290 and ep4sgx360 devices are availabl e only in 33 mm 33 mm hy brid flip chip package. (3) the 1152-pin and 1517-pin ep4sgx530 devices are available only in 42.5 mm 42.5 mm hybrid flip chip packages. (4) when migrating between hybrid and flip chip packages, there is an additional keep-out area. for more information, refer to t he altera device package information data sheet . (5) devices listed in this column are available in ?2, ?3, a nd ?4 speed grades. these devices do not have on-package decoupling capacitors. (6) devices listed in this column are available in ?2, ?3, a nd ?4 speed grades. these devices have on-package decoupling capacit ors. for more information about on-package decoupling capacitor value in each device, refer to table 1?3 . tab le 1 ?3 . stratix iv gx device on-package decoupling information (note 1) (part 1 of 2) ordering information v cc v ccio v ccl_gxb v cca_l/r v cct and v ccr (shared) ep4sgx70 hf35 2 1uf + 2 470nf 10nf per bank (2) 100nf per transceiver block 100nf 1 470nf + 1 47nf per side ep4sgx110 hf35 2 1uf + 2 470nf 10nf per bank (2) 100nf per transceiver block 100nf 1 470nf + 1 47nf per side 1?14 chapter 1: stratix iv device family overview architecture features stratix iv device handbook volume 1 ep4sgx180 hf35 kf40 2 1uf + 2 470nf 10nf per bank (2) 100nf per transceiver block 100nf 1 470nf + 1 47nf per side ep4sgx230 hf35 kf40 2 1uf + 2 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 1 470 nf + 1 47 nf per side ep4sgx290 hf35 kf40 kf43 nf45 4 1uf + 4 470 nf 10 nf per bank (2) 100 nf per transceiver block 100nf 1 470 nf + 1 47 nf per side ep4sgx360 hf35 kf40 kf43 nf45 4 1uf + 4 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 1 470 nf + 1 47 nf per side ep4sgx530 hh35 kh40 kf43 nf45 4 1uf + 4 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 1 470 nf + 1 47 nf per side notes to table 1?3 : (1) table 1?3 refers to production devices on-package decoupling. for more in formation about decoupling design of engineering sample (es) de vices, contact altera technical support . (2) for i/o banks 3(*), 4(*), 7(*), and 8(*) only. there is no opd for i/o bank 1(*), 2(*), 5(*), and 6(*). ta ble 1? 3. stratix iv gx device on-package decoupling information (note 1) (part 2 of 2) ordering information v cc v ccio v ccl_gxb v cca_l/r v cct and v ccr (shared) chapter 1: stratix iv device family overview 1?15 architecture features ? march 2010 altera corporation stratix iv device handbook volume 1 table 1?4 lists the stratix iv e device features. tab le 1 ?4 . stratix iv e device features feature ep4se230 ep4se360 ep4se530 ep4se820 package pin count 780 780 1152 1152 1517 1760 1152 1517 1760 alms 91,200 141,440 212,480 325,220 les 228,000 353,600 531,200 813,050 high-speed lvds serdes (up to 1.6 gbps) (1) 56 56 88 88 112 112 88 112 132 spi-4.2 links 3 3 4 4 6 4 6 6 m9k blocks (256 36 bits) 1,235 1,248 1,280 1610 m144k blocks (2048 72 bits) 22 48 64 60 total memory (mlab+m9k+ m144k) kbits 17,133 22,564 27,376 33,294 embedded multipliers (18 18) (2) 1,288 1,040 1,024 960 plls 4 4 8 8 12 12 8 12 12 user i/os (3) 488 488 744 744 976 976 744 (4) 976 (4) 1120 (4) speed grade (fastest to slowest) ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?3, ?4 ?3, ?4 ?3, ?4 notes to ta bl e 1? 4 : (1) the user i/o count from the pin-out files include all general purpose i/os, dedicated clock pins, and dual purpose configuration pins. transceiver pins and dedicated configuration pins are not included in the pin count. (2) four multiplier adder mode. (3) total pairs of high-speed lvds serdes take the lowest channel count of r x /t x . (4) this data is preliminary. 1?16 chapter 1: stratix iv device family overview architecture features stratix iv device handbook volume 1 ? march 2010 altera corporation table 1?5 summarizes the stratix iv e device package options. table 1?6 lists the stratix iv e on-package decoupling information. table 1?7 lists the stratix iv gt device features. tab le 1 ?5 . stratix iv e device package options (note 1) device f780 (29 mm 29 mm) (4) , (5) f1152 (35 mm 35 mm) (4) , (6) f1517 (40 mm 40 mm) (6) f1760 (42.5 mm 42.5 mm) (6) ep4se230 f29 ? ? ? ep4se360 h29 (2) f35 ? ? ep4se530 ? h35 (3) h40 (3) f43 ep4se820 ? h35 (3) h40 (3) f43 notes to ta bl e 1? 5 : (1) device packages in the same column and marked under the same arrow sign have vertical migration capability. (2) the 780-pin ep4se360 device is available only in the 33 mm 33 mm hybrid flip chip package. (3) the 1152-pin and 1517-pin for ep4se530 and ep4se820 devices are availa ble only in the 42.5 mm 42.5 mm hybrid flip chip package . (4) when migrating between hybrid and flip chip packages, there is an additional keep-out area. for more information, refer to t he altera device package information data sheet . (5) devices listed in this column do not have on-package decoupling capacitors. (6) devices listed in this column have on- package decoupling capacitors. for more in formation about on-package decoupling capaci tor value for each device, refer to table 1?6 . tab le 1 ?6 . stratix iv e device on-package decoupling information (note 1) ordering information v cc v ccio ep4se360 f35 4 1uf + 4 470 nf 10 nf per bank ep4se530 h35 h40 f43 4 1uf + 4 470 nf 10 nf per bank ep4se820 h35 h40 f43 4 1uf + 4 470 nf 10 nf per bank note to tab l e 1 ?6 : (1) table 1?6 refers to production devices on-package dec oupling. for more information about decoupling design of engineering sample (es) devices, contact altera technical support . tab le 1 ?7 . stratix iv gt device features (part 1 of 2) feature ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g3 ep4s100g4 ep4s100g5 package pin count 1517 1517 1517 1932 1932 1517 1932 alms 91,200 212,480 91,200 116,480 141,440 212,480 les 228,000 531,200 228,000 291,200 353,600 531,200 total transceiver channels 36 36 36 48 48 36 48 10g transceiver channels (600 mbps - 11.3 gbps with pma + pcs) 12 12 24 24 24 24 32 chapter 1: stratix iv device family overview 1?17 architecture features ? march 2010 altera corporation stratix iv device handbook volume 1 8g transceiver channels (600 mbps - 8.5 gbps with pms + pcs) (1) 12 12 0 8 8 0 0 pma-only cmu channels (600 mbps- 6.5 gbps) 12 12 12 16 16 12 16 pci express hard ip blocks 2224424 high-speed lvds serdes (up to 1.6 gbps) (2) 46 46 46 47 47 46 47 sp1-4.2 links 2 2 2 2 2 2 2 m9k blocks (256 72 bits) 1,235 1,280 1,235 936 1,248 1,280 m144k blocks (2048 72 bits) 22 64 22 36 48 64 total memory (mlab + m9k + m144k) kbits 17,133 27,376 17,133 17,248 22,564 27,376 embedded multipliers 18 18 (3) 1,288 1,024 1,288 832 1,024 1,024 plls 8 8 8 12 12 8 12 user i/os (4) , (5) 654 654 654 781 781 654 781 speed grade (fastest to slowest) ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 notes to ta bl e 1? 7 : (1) you can configure all 10g transceiver channels as 8g transceiver channels. for example, the ep4s40g2f40 device has twenty-fo ur 8g transceiver channels and the ep4s100g5f45 device has thirty-two 8g transceiver channels. (2) total pairs of high-speed lvds serdes take the lowest channel count of r x /t x . (3) four multiplier adder mode. (4) the user i/o count from the pin-out files include all general purpose i/os, dedicated clock pins, and dual purpose configura tion pins. transceiver pins and dedicated configuration pins are not included in the pin count. (5) this data is preliminary. tab le 1 ?7 . stratix iv gt device features (part 2 of 2) feature ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g3 ep4s100g4 ep4s100g5 1?18 chapter 1: stratix iv device family overview integrated software platform stratix iv device handbook volume 1 ? march 2010 altera corporation table 1?8 summarizes the resource counts for the stratix iv gt devices. table 1?9 lists the stratix iv gt on-package decoupling information. integrated software platform the quartus ii software provides an integrated environment for hdl and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, signaltap ii logic analyzer, and device configuration of stratix iv designs. the quartus ii software provides the megawizard ? , , , , tab le 1 ?8 . stratix iv gt device package options (note 1) device 1517 pin (40 mm 40 mm) (2) 1932 pin (45 mm 45 mm) stratix iv gt 40 g devices ep4s40g2 f40 ? ep4s40g5 h40 (3) ? stratix iv gt 100 g devices ep4s100g2 f40 ? ep4s100g3 ? f45 ep4s100g4 ? f45 ep4s100g5 h40 (3) f45 notes to ta bl e 1? 8 : (1) devices under the same arrow sign have vertical migration capability. (2) when migrating between hybrid and flip chip packages, ther e is an additional keep-out area. for more information, refer to the altera device package information data sheet . (3) ep4s40g5 and ep4s100g5 devices with 1517 pin-count are only available in 42.5-mm 42.5-mm hybrid flip chip packages. tab le 1 ?9 . stratix iv gt device on-package decoupling information (note 1) ordering information v cc v ccio v ccl_gxb v cca_l/r v cct_l/r v cc r_l /r ep4s40g2f40 ep4s100g2f40 2 1uf + 2 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 100 nf 100 nf ep4s100g3f45 4 1uf + 4 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 100 nf 100 nf ep4s100g4f45 ep4s40g5h40 ep4s100g5h40 ep4s100g5f45 notes to ta bl e 1? 9 : (1) table 1?9 refers to production devices on-package dec oupling. for more information about decoupling design of engineering sample (es) devices, contact altera technical support . (2) for i/o banks 3(*), 4(*), 7(*), and 8(*) only. there is no opd for i/o bank 1(*), 2(*), 5(*), and 6(*). chapter 1: stratix iv device family overview 1?19 ordering information ? march 2010 altera corporation stratix iv device handbook volume 1 the stratix iv gx and gt transceivers allow you to implement low-power and reliable high-speed serial interface applications with its fully reconfigurable hardware, optimal signal integrity, and integrated quartus ii software platform. f r r fr r fwr fr rfr quartus ii handbook . ordering information this section describes the stratix iv e, gt, and gx devices ordering information. figure 1?4 shows the ordering codes for stratix iv gx and e devices. figure 1?4. stratix iv gx and e device packaging ordering information device density transceiver count package type 2, 2x, 3, or 4, with 2 b eing the fastest corresponds to pin count 29 = 780 pins 35 = 1152 pins 40 = 1517 pins 43 = 1760 pins 45 = 1932 pins f: fineline bga (fbga) h: hy b rid fineline bga ep4sgx: stratix i v transceiv er d: 8 f: 16 h: 24 k: 36 n: 4 8 ep4se: stratix i v logic/memory 70 110 180 230 290 360 530 820 c: commercial temperature (t j =0 cto85 c) indust rial t emperat ure (t j =-40 cto100 c) optional suffix fam i l y s i g n a t u r e operating temperature sp e e d gr ad e ball array dimension 2 ep4sgx 230 c 40 fk es indicates specific device options n: lead-free devices i: es: engineering sample 1?20 chapter 1: stratix iv device family overview document revision history stratix iv device handbook volume 1 ? march 2010 altera corporation figure 1?5 shows the ordering codes for stratix iv gt devices. document revision history table 1?10 lists the revision history for this chapter. figure 1?5. stratix iv gt device packaging ordering information device density package type 1, 2, 3 with 1 b eing the fastest corresponds to pin cou nt 40 = 1517 pins 45 = 1932 pins f: fineline bga (fbga) h: hy b rid fineline bga 2 = 230k les 3 = 290k les 4 = 360k les 5 = 530k les c: commercial temperature (t j =0 cto85 c) indust rial t emperat ure (t j = 0c to 100c) optional suffix fam i l y s i g n a t u r e operating temperature sp eed gr ade ball array dimension 2 ep4s 230 c 40 f es indicat es specific device opt ions n: lead-free devices i: es: engineering sample aggregate bandwidth ep4s 240g 40g 100g table 1?10. document revision history (part 1 of 2) date and document version changes made summary of changes march 2010 v3.1 updated table 1?1 , table 1?2 , and tab le 1 ?7 . updated figure 1?3 . updated the ?stratix iv gt devices? section. added two new references to the introduction section. minor text edits. ? november 2009 v3.0 updated the ?stratix iv device family overview?, ?feature summary?, ?stratix iv gt devices?, ?high-speed transceiver features?, ?fpga fabric and i/o features?, ?highest aggregate data bandwidth?, ?system integration?, and ?integrated software platform? sections. added table 1?3, table 1?6, and table 1?9. updated table 1?1, table 1?2, table 1?4, table 1?5, table 1?7, and ta ble 1? 8. updated figure 1?3, figure 1?4, and figure 1?5. minor text edits. ? june 2009 v2.4 updated table 1?1. minor text edits. ? chapter 1: stratix iv device family overview 1?21 document revision history ? march 2010 altera corporation stratix iv device handbook volume 1 april 2009 v2.3 added table 1?5, table 1?6, and figure 1?3. updated figure 1?5. updated table 1?1, table 1?2, table 1?3, and table 1?4. updated ?introduction?, ?feature summary?, ?stratix iv gx devices?, ?stratix iv gt devices?, ?architecture features?, and ?fpga fabric and i/o features? ? march 2009 v2.2 updated ?feature summary?, ?stratix iv gx devices?, ?stratix iv e device?, ?stratix iv gt devices?, ?signal integrity? removed tables 1-5 and 1-6 updated figure 1?4 ? march 2009 v2.1 updated ?introduction?, ?feature summary?, ?stratix iv device diagnostic features?, ?signal integrity?, ?clock networks?,?high-speed differential i/o with dpa and soft-cdr?, ?system integration?, and ?ordering information? sections. added ?stratix iv gt 100g devices? and ?stratix iv gt 100g transceiver bandwidth? sections. updated table 1?1, table 1?2, table 1?3, and table 1?4. added table 1?5 and table 1?6. updated figure 1?3 and figure 1?4. added figure 1?5. removed ?referenced documents? section. ? november 2008 v2.0 updated ?feature summary? on page 1?1. updated ?stratix iv device diagnostic features? on page 1?7. updated ?fpga fabric and i/o features? on page 1?8. updated table 1?1. updated table 1?2. updated ?table 1?5 shows the total number of transceivers available in the stratix iv gt device.? on page 1?15. ? july 2008 v1.1 revised ?introduction?. ? may 2008 v1.0 initial release. ? table 1?10. document revision history (part 2 of 2) date and document version changes made summary of changes 1?22 chapter 1: stratix iv device family overview document revision history stratix iv device handbook volume 1 ? march 2010 altera corporation ? november 2009 altera corporation stratix iv device handbook volume 1 2. logic array blocks and adaptive logic modules in stratix iv devices this chapter describes the features of the labs in the stratix iv core fabric. labs are made up of alms you can configure to implement logic functions, arithmetic functions, and register functions. logic array blocks (labs) and adaptive logic modules (alms) are the basic building blocks of the stratix ? iv device. you can use these to configure logic functions, arithmetic functions, and register functions. the alm provides advanced features with efficient logic utilization and is completely backward-compatible. this chapter contains the following sections: logic array blocks each lab consists of ten alms, various carry chains, shared arithmetic chains, lab control signals, local interconnect, and register chain connection lines. the local interconnect transfers signals between alms in the same lab. the direct link interconnect allows the lab to drive into the local interconnect of its left and right neighbors. register chain connections transfer the output of the alm register to the adjacent alm register in the lab. the quartus ? ii compiler places associated logic in the lab or adjacent labs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. figure 2?1 shows the stratix iv lab structure and the lab interconnects. siv51002-3.0 2?2 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices logic array blocks stratix iv device handbook volume 1 ? november 2009 altera corporation the lab of the stratix iv device has a derivative called memory lab (mlab), which adds look-up table (lut)-based sram capability to the lab, as shown in figure 2?2 . the mlab supports a maximum of 640 bits of simple dual-port static random access memory (sram). you can configure each alm in an mlab as either a 64 1 or a 32 2 block, resulting in a configuration of either a 64 10 or a 32 20 simple dual-port sram block. mlab and lab blocks always coexist as pairs in all stratix iv families. mlab is a superset of the lab and includes all lab features. f cr trimatrix embedded memory blocks in stratix iv devices chapter. figure 2?1. stratix iv lab structure direct link interconnect from adjacent block direct link interconnect to adjacent block row interconnects of variable speed & length column interconnects of variable speed & length local interconnect is driven from either side by columns & labs, & from above by rows local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block alms mlab c4 c12 r20 r4 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?3 logic array blocks ? november 2009 altera corporation stratix iv device handbook volume 1 lab interconnects the lab local interconnect can drive alms in the same lab. it is driven by column and row interconnects and alm outputs in the same lab. neighboring labs/mlabs, m9k ram blocks, m144k blocks, or dsp blocks from the left or right can also drive the lab?s local interconnect through the direct link connection. the direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. each lab can drive 30 alms through fast-local and direct-link interconnects. figure 2?2. stratix iv lab and mlab structure note to figure 2?2 : (1) you can use the mlab alm as a regular lab alm or configure it as a dual-port sram, as shown. mlab lab lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram lut-based-64 x 1 simple dual-port sram (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) alm alm alm alm alm alm alm alm alm alm lab control block lab control block 2?4 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices logic array blocks stratix iv device handbook volume 1 ? november 2009 altera corporation figure 2?3 shows the direct-link connection. lab control signals each lab contains dedicated logic for driving control signals to its alms. control signals include three clocks, three clock enables, two asynchronous clears, a synchronous clear, and synchronous load control signals. this gives a maximum of 10 control signals at a time. although you generally use synchronous-load and clear signals when implementing counters, you can also use them with other functions. each lab has two unique clock sources and three clock enable signals, as shown in figure 2?4 . the lab control block can generate up to three clocks using two clock sources and three clock enable signals. each lab?s clock and clock enable signals are linked. for example, any alm in a particular lab using the labclk1 signal also uses the labclkena1 signal. if the lab uses both the rising and falling edges of a clock, it also uses two lab-wide clock signals. de-asserting the clock enable signal turns off the corresponding lab-wide clock. the lab row clocks [5..0] and lab local interconnects generate the lab-wide control signals. the multitrack interconnect?s inherent low skew allows clock and control signal distribution in addition to data. figure 2?3. direct-link connection alms direct-link interconnect to right direct-link interconnect from the right lab, trimatrix memory b lock, dsp b lock, or ioe o utput direct-link interconnect from the left lab, trimatrix memory b lock, dsp b lock, or ioe o utput local inter connect lab alms direct-link interconnect to left mlab chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?5 adaptive logic modules ? november 2009 altera corporation stratix iv device handbook volume 1 adaptive logic modules the alm is the basic building block of logic in the stratix iv architecture. it provides advanced features with efficient logic utilization. each alm contains a variety of lut-based resources that can be divided between two combinational adaptive luts (aluts) and two registers. with up to eight inputs for the two combinational aluts, one alm can implement various combinations of two functions. this adaptability allows an alm to be completely backward-compatible with four-input lut architectures. one alm can also implement any function with up to six inputs and certain seven-input functions. in addition to the adaptive lut-based resources, each alm contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain. through these dedicated resources, an alm can efficiently implement various arithmetic functions and shift registers. each alm drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link. figure 2?5 shows a high-level block diagram of the stratix iv alm. figure 2?4. lab-wide control signals dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclk2 syncload labclkena0 or asyncload or labpreset labclk0 labclk1 labclr1 labclkena1 labclkena2 labclr0 synclr 6 6 6 there are two unique clock signals per lab. 2?6 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook volume 1 ? november 2009 altera corporation figure 2?5. high-level block diagram of the stratix iv alm dq to general or local routing reg0 to general or local routing datae0 dataf0 reg_chain_in reg_chain_out adder0 dataa datab datac datad datae1 dataf1 dq to general or local routing reg1 to general or local routing adder1 carry_in carry_o ut combinational/memory alut0 6-input lut 6-input lut shared_arith_out shared_arith_in combinational/memory alut1 labclk chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?7 adaptive logic modules ? november 2009 altera corporation stratix iv device handbook volume 1 figure 2?6 shows a detailed view of all the connections in an alm. one alm contains two programmable registers. each register has data, clock, clock enable, synchronous and asynchronous clear, and synchronous load and clear inputs. global signals, general-purpose i/o pins, or any internal logic can drive the register?s clock and clear-control signals. either general-purpose i/o pins or internal logic can drive the clock enable. for combinational functions, the register is bypassed and the output of the lut drives directly to the outputs of an alm. each alm has two sets of outputs that drive the local, row, and column routing resources. the lut, adder, or register outputs can drive these output drivers (refer to figure 2?6 ). for each set of output drivers, two alm outputs can drive column, row, or direct-link routing connections. one of these alm outputs can also drive local interconnect resources. this allows the lut or adder to drive one output while the register drives another output. figure 2?6. stratix iv alm connection details d q + reg_chain_in aclr[1:0] sclr syncload clk[2:0] carry_in dataf0 datae0 dataa datab datac1 datae1 dataf1 shared_arith_out carry_out reg_chain_out clr d q clr shared_arith_in local interconnect row, column direct link routing row, column direct link routing local interconnect 4-input lut 4-input lut 3-input lut 3-input lut 3-input lut 3-input lut + datac0 v cc gnd row, column direct link routing row, column direct link routing 2?8 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook volume 1 ? november 2009 altera corporation this feature, called register packing, improves device utilization because the device can use the register and the combinational logic for unrelated functions. another special packing mode allows the register output to feed back into the lut of the same alm so that the register is packed with its own fan-out lut. this provides another mechanism for improved fitting. the alm can also drive out registered and unregistered versions of the lut or adder output. alm operating modes the stratix iv alm operates in one of the following modes: normal mode normal mode is suitable for general logic applications and combinational functions. in this mode, up to eight data inputs from the lab local interconnect are inputs to the combinational logic. normal mode allows two functions to be implemented in one stratix iv alm, or a single function of up to six inputs. the alm can support certain combinations of completely independent functions and various combinations of functions that have common inputs. chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?9 adaptive logic modules ? november 2009 altera corporation stratix iv device handbook volume 1 figure 2?7 shows the supported lut combinations in normal mode. normal mode provides complete backward-compatibility with four-input lut architectures. for the packing of 2 five-input functions into one alm, the functions must have at least two common inputs. the common inputs are dataa and datab . the combination of a four-input function with a five-input function requires one common input (either dataa or datab). figure 2?7. alm in normal mode (note 1) note to figure 2?7 : (1) combinations of functions with fewer inputs than those show n are also supported. for example, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, and 5 and 2. 6-input lut dataf0 datae0 dataf0 datae0 dataa datab dataa datab datab datac datac dataf0 datae0 dataa datac 6-input lut datad datad datae1 combout0 combout1 combout0 combout1 combout0 combout1 dataf1 datae1 dataf1 datad datae1 dataf1 4-input lut 4-input lut 4-input lut 6-input lut dataf0 datae0 dataa datab datac datad combout0 5-input lut 5-input lut dataf0 datae0 dataa datab datac datad combout0 combout1 datae1 dataf1 5-input lut dataf0 datae0 dataa datab datac datad combout0 combout1 datae1 dataf1 5-input lut 3-input lut 2?10 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook volume 1 ? november 2009 altera corporation in the case of implementing 2 six-input functions in one alm, four inputs must be shared and the combinational function must be the same. in a sparsely used device, functions that could be placed in one alm may be implemented in separate alms by the quartus ii software to achieve the best possible performance. as a device begins to fill up, the quartus ii software automatically utilizes the full potential of the stratix iv alm. the quartus ii compiler automatically searches for functions using common inputs or completely independent functions to be placed in one alm to make efficient use of device resources. in addition, you can manually control resource usage by setting location assignments. any six-input function can be implemented using inputs dataa, datab, datac, datad , and either datae0 and dataf0 or datae1 and dataf1 . if datae0 and dataf0 are utilized, the output is driven to register0 , and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (refer to figure 2?8 ). if datae1 and dataf1 are used, the output either drives to register1 or bypasses register1 and drives to the interconnect using the bottom set of output drivers. the quartus ii compiler automatically selects the inputs to the lut. alms in normal mode support register packing. extended lut mode use extended lut mode to implement a specific set of seven-input functions. the set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four inputs. figure 2?9 shows the template of supported seven-input functions using extended lut mode. in this mode, if the seven-input function is unregistered, the unused eighth input is available for register packing. functions that fit into the template shown in figure 2?9 occur naturally in designs. these functions often appear in designs as ?if-else? statements in verilog hdl or vhdl code. figure 2?8. input function in normal mode (note 1) notes to figure 2?8 : (1) if datae1 and dataf1 are used as inputs to a six-input function, datae0 and dataf0 are available for register packing. (2) the dataf1 input is available for register packing only if the six-input function is unregistered. 6-input lut dataf0 datae0 dataa datab datac datad datae1 dataf1 dq dq to general or local routing to general or local routing to general or local routing reg0 reg1 these inputs are available for register packing. (2) labclk chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?11 adaptive logic modules ? november 2009 altera corporation stratix iv device handbook volume 1 arithmetic mode arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. the alm in arithmetic mode uses two sets of 2 four-input luts along with two dedicated full adders. the dedicated adders allow the luts to be available to perform pre-adder logic; therefore, each adder can add the output of 2 four-input functions. the four luts share dataa and datab inputs. as shown in figure 2?10 , the carry-in signal feeds to adder0 and the carry-out from adder0 feeds to the carry-in of adder1 . the carry-out from adder1 drives to adder0 of the next alm in the lab. alms in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs. figure 2?9. template for supported seven-input functions in extended lut mode note to figure 2?9 : (1) if the seven-input function is unregistered, the unused eighth input is available for register packing. the second register, reg1 , is not available. datae0 combout0 5-input lut 5-input lut datac dataa datab datad dataf0 datae1 dataf1 dq to general or local routing to general or local routing reg0 this input is available for register packing. (1) figure 2?10. alm in arithmetic mode datae0 carry_in carry_o ut dataa datab datac datad datae1 dq dq to general or local routing to general or local routing reg0 reg1 to general or local routing to general or local routing 4-input lut 4-input lut 4-input lut 4-input lut adder1 adder0 dataf0 dataf1 2?12 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook volume 1 ? november 2009 altera corporation while operating in arithmetic mode, the alm can support simultaneous use of the adder?s carry output along with combinational logic outputs. in this operation, adder output is ignored. using the adder with combinational logic output provides resource savings of up to 50% for functions that can use this ability. arithmetic mode also offers clock enable, counter enable, synchronous up/down control, add/subtract control, synchronous clear, and synchronous load. the lab local interconnect data inputs generate the clock enable, counter enable, synchronous up/down, and add/subtract control signals. these control signals are good candidates for the inputs that are shared between the four luts in the alm. the synchronous clear and synchronous load options are lab-wide signals that affect all registers in the lab. these signals can also be individually disabled or enabled per register. the quartus ii software automatically places any registers that are not used by the counter into other labs. carry chain the carry chain provides a fast carry function between the dedicated adders in arithmetic or shared-arithmetic mode. the two-bit carry select feature in stratix iv devices halves the propagation delay of carry chains within the alm. carry chains can begin in either the first alm or the fifth alm in the lab. the final carry-out signal is routed to the alm, where it is fed to local, row, or column interconnects. the quartus ii compiler automatically creates carry-chain logic during design processing, or you can create it manually during design entry. parameterized functions such as lpm functions automatically take advantage of carry chains for the appropriate functions. the quartus ii compiler creates carry chains longer than 20 (10 alms in arithmetic or shared arithmetic mode) by linking labs together automatically. for enhanced fitting, a long carry chain runs vertically, allowing fast horizontal connections to trimatrix memory and dsp blocks. a carry chain can continue as far as a full column. to avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the lab can support carry chains that only utilize either the top half or bottom half of the lab before connecting to the next lab. this leaves the other half of the alms in the lab available for implementing narrower fan-in functions in normal mode. carry chains that use the top five alms in the first lab carry into the top half of the alms in the next lab within the column. carry chains that use the bottom five alms in the first lab carry into the bottom half of the alms in the next lab within the column. in every alternate lab column, the top half can be bypassed; in the other mlab columns, the bottom half can be bypassed. for more information about carry-chain interconnects, refer to ?alm interconnects? on page 2?17 . chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?13 adaptive logic modules ? november 2009 altera corporation stratix iv device handbook volume 1 shared arithmetic mode in shared arithmetic mode, the alm can implement a three-input add within the alm. in this mode, the alm is configured with 4 four-input luts. each lut either computes the sum of three inputs or the carry of three inputs. the output of the carry computation is fed to the next adder (either to adder1 in the same alm or to adder0 of the next alm in the lab) using a dedicated connection called the shared arithmetic chain. this shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree. figure 2?11 shows the alm using this feature. you can find adder trees in many different applications. for example, the summation of the partial products in a logic-based multiplier can be implemented in a tree structure. another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or de-spread data that was transmitted utilizing spread-spectrum technology. shared arithmetic chain the shared arithmetic chain available in enhanced arithmetic mode allows the alm to implement a three-input add. this significantly reduces the resources necessary to implement large adder trees or correlator functions. the shared arithmetic chains can begin in either the first or sixth alm in the lab. the quartus ii compiler creates shared arithmetic chains longer than 20 (10 alms in arithmetic or shared arithmetic mode) by linking labs together automatically. for enhanced fitting, a long shared arithmetic chain runs vertically, allowing fast horizontal connections to the trimatrix memory and dsp blocks. a shared arithmetic chain can continue as far as a full column. figure 2?11. alm in shared arithmetic mode datae0 carry_in shared_arith_in shared_arith_o ut carry_o ut dataa datab datac datad datae1 dq dq to general or local routing to general or local routing reg0 reg1 to general or local routing to general or local routing 4-input lut 4-input lut 4-input lut 4-input lut labclk 2?14 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook volume 1 ? november 2009 altera corporation similar to the carry chains, the top and bottom halves of shared arithmetic chains in alternate lab columns can be bypassed. this capability allows the shared arithmetic chain to cascade through half of the alms in an lab while leaving the other half available for narrower fan-in functionality. every other lab column is top-half by-passable, while the other lab columns are bottom-half by-passable. for more information on shared arithmetic chain interconnect, refer to ?alm interconnects? on page 2?17 . lut-register mode lut-register mode allows third-register capability within an alm. two internal feedback loops allow combinational alut1 to implement the master latch and combinational alut0 to implement the slave latch needed for the third register. the lut register shares its clock, clock enable, and asynchronous clear sources with the top dedicated register. figure 2?12 shows the register constructed using two combinational blocks within the alm. figure 2?12. lut register from two combinational blocks 4-input lut 5-input lut clk aclr datain(datac) sclr sumout combout lut regout sumout combout chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?15 adaptive logic modules ? november 2009 altera corporation stratix iv device handbook volume 1 figure 2?13 shows the alm in lut-register mode. register chain in addition to general routing outputs, alms in the lab have register-chain outputs. register-chain routing allows registers in the same lab to be cascaded together. the register-chain interconnect allows the lab to use luts for a single combinational function and the registers to be used for an unrelated shift-register implementation. these resources speed up connections between alms while saving local interconnect resources (refer to figure 2?14 ). the quartus ii compiler automatically takes advantage of these resources to improve utilization and performance. figure 2?13. alm in lut-register mode with three-register capability datain aclr sclr regout latchout datain sdata regout aclr datain sdata regout aclr dc1 e0 f1 e1 f0 clk [2:0] aclr [1:0] reg_chain_in lelocal 0 leout 0 a leout 0 b reg_chain_out lelocal 1 leout 1 a leout 1 b 2?16 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices adaptive logic modules stratix iv device handbook volume 1 ? november 2009 altera corporation for more information about register chain interconnect, refer to ?alm interconnects? on page 2?17 . figure 2?14. register chain within the lab (note 1) note to figure 2?14 : (1) you can use the combinational or adder logic to implement an unrelated, un-registered function. dq to general or local routing reg0 to general or local routing reg_chain_in adder0 dq to general or local routing reg1 to general or local routing adder1 dq to general or local routing reg0 to general or local routing reg_chain_out adder0 dq to general or local routing reg1 to general or local routing adder1 from previous alm within the lab to next alm within the lab combinational logic combinational logic labclk chapter 2: logic array blocks and adaptive logic modules in stratix iv devices 2?17 adaptive logic modules ? november 2009 altera corporation stratix iv device handbook volume 1 alm interconnects there are three dedicated paths between alms: register cascade, carry chain, and shared arithmetic chain. stratix iv devices include an enhanced interconnect structure in labs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. the register chain connection allows the register output of one alm to connect directly to the register input of the next alm in the lab for fast shift registers. these alm-to-alm connections bypass the local interconnect. the quartus ii compiler automatically takes advantage of these resources to improve utilization and performance. figure 2?15 shows the shared arithmetic chain, carry chain, and register chain interconnects. clear and preset logic control lab-wide signals control the logic for the register ?s clear signal. the alm directly supports an asynchronous clear function. you can achieve the register preset through the quartus ii software?s not-gate push-back logic option. each lab supports up to two clears. stratix iv devices provide a device-wide reset pin ( dev_clrn ) that resets all the registers in the device. an option set before compilation in the quartus ii software controls this pin. this device-wide reset overrides all other control signals. figure 2?15. shared arithmetic chain, carry chain, and register chain interconnects alm 1 alm 2 alm 3 alm 4 alm 5 alm 6 carry chain & shared arithmetic chain routing to adjacent alm local interconnect register chain routing to adjacent alm's register inpu t local interconnect routing among alms in the lab alm 7 alm 8 alm 9 alm 10 2?18 chapter 2: logic array blocks and adaptive logic modules in stratix iv devices document revision history stratix iv device handbook volume 1 ? november 2009 altera corporation lab power management techniques the following techniques are used to manage static and dynamic power consumption within the lab: labclk1 signal also uses the labclkena1 signal. to disable an lab-wide clock power consumption without disabling the entire clock tree, use the lab-wide clock enable to gate the lab-wide clock. the quartus ii software automatically promotes register-level clock enable signals to the lab-level. all registers within the lab that share a common clock and clock enable are controlled by a shared, gated clock. to take advantage of these clock enables, use a clock-enable construct in your hdl code for the registered logic. f r r fr c c wr c w rfr wr cr v f r document revision history table 2?1 shows the revision history for this chapter. . tab le 2 ?1 . document revision history date and document version changes made summary of changes november 2009 v3.0 updated graphics. minor text edits. ? june 2009 v2.2 removed the conclusion section. added introductory sentences to improve search ability. minor text edits. ? march 2009 v2.1 removed ?referenced documents? section. ? november 2008 v2.0 updated figure 2?6. made minor editorial changes. ? may 2008 v1.0 initial release. ? ? march 2010 altera corporation stratix iv device handbook volume 1 3. trimatrix embedded memory blocks in stratix iv devices this chapter describes the trimatrix embedded memory blocks in stratix ? iv devices. trimatrix embedded memory blocks provide three different sizes of embedded sram to efficiently address the needs of stratix iv fpga designs. trimatrix memory includes 640-bit memory logic array blocks (mlabs), 9-kbit m9k blocks, and 144-kbit m144k blocks. mlabs have been optimized to implement filter delay lines, small fifo buffers, and shift registers. you can use the m9k blocks for general purpose memory applications and the m144k blocks for processor code storage, packet buffering, and video frame buffering. you can independently configure each embedded memory block to be a single- or dual-port ram, fifo buffer, rom, or shift register using the quartus ? ii megawizard tm plug-in manager. you can stitch together multiple blocks of the same type to produce larger memories with minimal timing penalty. trimatrix memory provides up to 31,491 kbits of embedded sram at up to 600 mhz operation. this chapter contains the following sections: overview table 3?1 lists the features supported by the three sizes of trimatrix memory. tab le 3 ?1 . summary of trimatrix memory features (part 1 of 2) feature mlabs m9k blocks m144k blocks maximum performance 600 mhz 600 mhz 540 mhz total ram bits (including parity bits) 640 9216 147,456 configurations (depth width) 64 8 64 9 6410 3216 3218 3220 8k 1 4k 2 2k 4 1k 8 1k 9 512 16 512 18 256 32 256 36 16k 8 16k 9 8k 16 8k 18 4k 32 4k 36 2k 64 2k 72 parity bits vv v byte enable vv v packed mode ? vv siv51003-3.1 3?2 chapter 3: trimatrix embedded memory blocks in stratix iv devices overview stratix iv device handbook volume 1 ? march 2010 altera corporation table 3?2 lists the capacity and distribution of the trimatrix memory blocks in each stratix iv family member. address clock enable vv v single-port memory vv v simple dual-port memory vv v true dual-port memory ? vv embedded shift register vv v rom vv v fifo buffer vv v simple dual-port mixed width support ? vv true dual-port mixed width support ? vv memory initialization file ( .mif ) vv v mixed-clock mode vv v power-up condition outputs cleared if registered, otherwise reads memory contents outputs cleared outputs cleared register clears output registers output registers output registers write/read operation triggering write: falling clock edges read: rising clock edges write and read: rising clock edges write and read: rising clock edges same-port read-during-write outputs set to ?don?t care? outputs set to ?old data? or ?new data? outputs set to ?old data? or ?new data? mixed-port read-during-write outputs set to ?old data? or ?don?t care? outputs set to ?old data? or ?don?t care? outputs set to ?old data? or ?don?t care? ecc support soft ip support using the quartus ii software soft ip support using the quartus ii software built-in support in 64-wide sdp mode or soft ip support using the quartus ii software tab le 3 ?1 . summary of trimatrix memory features (part 2 of 2) feature mlabs m9k blocks m144k blocks tab le 3 ?2 . trimatrix memory capacity and distribution in stratix iv devices (part 1 of 2) device mlabs m9k blocks m144k blocks total dedicated ram bits (dedicated memory blocks only) (kb) total ram bits (including mlabs) (kb) ep4se230 4560 1235 22 14,283 17,133 ep4se360 7072 1248 48 18,144 22,564 ep4se530 10,624 1280 64 20,736 27,376 ep4se820 16,261 1610 60 23,130 33,294 ep4sgx70 1452 462 16 6462 7370 ep4sgx110 2112 660 16 8244 9564 ep4sgx180 3515 950 20 11,430 13,627 ep4sgx230 4560 1235 22 14,283 17,133 chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?3 overview ? march 2010 altera corporation stratix iv device handbook volume 1 trimatrix memory block types while the m9k and m144k memory blocks are dedicated resources, the mlabs are dual-purpose blocks. they can be configured as regular logic array blocks (labs) or as mlabs. ten adaptive logic modules (alms) make up one mlab. each alm in an mlab can be configured as either a 64 1 or a 32 2 block, resulting in a 64 10 or 32 20 simple dual-port sram block in a single mlab. parity bit support all trimatrix memory blocks have built-in parity-bit support. the ninth bit associated with each byte can store a parity bit or serve as an additional data bit. no parity function is actually performed on the ninth bit. byte enable support all trimatrix memory blocks support byte enables that mask the input data so that only specific bytes of data are written. the unwritten bytes retain the previously written values. the write enable ( wren ) signals, along with the byte enable ( byteena ) signals, control the ram blocks? write operations. the default value for the byte enable signals is high (enabled), in which case writing is controlled only by the write enable signals. the byte enable registers have no clear port. when using parity bits on the m9k and m144k blocks, the byte enable controls all nine bits (eight bits of data plus one parity bit). when using parity bits on the mlab, the byte-enable controls all 10 bits in the widest mode. byte enables operate in a one-hot fashion, with the lsb of the byteena signal corresponding to the lsb of the data bus. for example, if you use a ram block in 18 mode, with byteena = 01 , data[8..0] is enabled, and data[17..9] is disabled. similarly, if byteena = 11 , both data[8..0] and data[17..9] are enabled. byte enables are active high. 1 c fr w rrr crrc c fr 1 c ep4sgx290 5824 936 36 13,608 17,248 ep4sgx360 7072 1248 48 18,144 22,564 ep4sgx530 10,624 1280 64 20,736 27,376 ep4s40g2 4560 1235 22 14,283 17,133 ep4s40g5 10,624 1280 64 20,736 27,376 ep4s100g2 4560 1235 22 14,283 17,133 ep4s100g3 5824 936 36 13,608 17,248 ep4s100g4 7072 1248 48 18,144 22,564 ep4s100g5 10624 1280 64 20,736 27,376 tab le 3 ?2 . trimatrix memory capacity and distribution in stratix iv devices (part 2 of 2) device mlabs m9k blocks m144k blocks total dedicated ram bits (dedicated memory blocks only) (kb) total ram bits (including mlabs) (kb) 3?4 chapter 3: trimatrix embedded memory blocks in stratix iv devices overview stratix iv device handbook volume 1 ? march 2010 altera corporation figure 3?1 shows how the write enable ( wren ) and byte enable ( byteena ) signals control the operations of the ram blocks. when a byte-enable bit is de-asserted during a write cycle, the corresponding data byte output can appear as either a ?don?t care? value or the current data at that location. the output value for the masked byte is controllable using the quartus ii software. when a byte-enable bit is asserted during a write cycle, the corresponding data byte output also depends on the setting chosen in the quartus ii software. figure 3?1. byte enable functional waveform inclock wren address data don't care: q (asynch) byteena xxxx abcd xxxx xx 10 01 11 xx an a0 a1 a2 a0 a1 a2 abcd ffff ffff abff ffff ffcd contents at a0 contents at a1 contents at a2 doutn abxx xxcd abcd abff ffcd abcd doutn abff ffcd abcd abff ffcd abcd current data: q (asynch) chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?5 overview ? march 2010 altera corporation stratix iv device handbook volume 1 packed mode support stratix iv m9k and m144k blocks support packed mode. the packed mode feature packs two independent single-port rams into one memory block. the quartus ii software automatically implements packed mode where appropriate by placing the physical ram block into true dual-port mode and using the msb of the address to distinguish between the two logical rams. the size of each independent single-port ram must not exceed half of the target block size. address clock enable support all stratix iv memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled ( addressstall = 1 ). when the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. the default value for the address clock enable signals is low (disabled). figure 3?2 shows an address clock enable block diagram. the address clock enable is referred to by the port name addressstall. figure 3?3 shows the address clock enable waveform during the read cycle. figure 3?2. address clock enable figure 3?3. address clock enable during read cycle waveform address[0] address[n] addressstall clock 1 0 address[0] register address[n] register address[n] address[0] 1 0 inclock rden rdaddress q (synch) a0 a1 a2 a3 a4 a5 a6 q (asynch) an a0 a4 a5 latched address (inside memory) dout0 dout1 dout4 dout4 dout5 addressstall a1 doutn-1 doutn doutn dout0 dout1 3?6 chapter 3: trimatrix embedded memory blocks in stratix iv devices overview stratix iv device handbook volume 1 ? march 2010 altera corporation figure 3?4 shows the address clock enable waveform during the write cycle. mixed width support m9k and m144k memory blocks support mixed data widths inherently. mlabs can support mixed data widths through emulation using the quartus ii software. when using simple dual-port, true dual-port, or fifo modes, mixed width support allows you to read and write different data widths to a memory block. for more information about the different widths supported per memory mode, refer to ?memory modes? on page 3?8 . 1 r w asynchronous clear stratix iv trimatrix memory blocks support asynchronous clears on output latches and output registers. therefore, if your ram is not using output registers, you can still clear the ram outputs using the output latch asynchronous clear. figure 3?5 shows a waveform of the output latch asynchronous clear function. figure 3?4. address clock enable during the write cycle waveform inclock wren wraddress a0 a1 a2 a3 a4 a5 a6 an a0 a4 a5 latched address (inside memory) addressstall a1 data 00 01 02 03 04 05 06 contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 xx 04 xx 00 03 01 xx 02 xx xx xx 05 figure 3?5. output latch asynchronous clear waveform aclr aclr at latch q outclk chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?7 overview ? march 2010 altera corporation stratix iv device handbook volume 1 you can selectively enable asynchronous clears per logical memory using the quartus ii ram megawizard plug-in manager. f r r fr rfr internal memory (ram and rom) user guide . error correction code (ecc) support stratix iv m144k blocks have built-in support for error correction code (ecc) when in 64-wide simple dual-port mode. ecc allows you to detect and correct data errors in the memory array. the m144k blocks have a single-error-correction double-error-detection (secded) implementation. secded can detect and fix a single bit error in a 64-bit word, or detect two bit errors in a 64-bit word. it cannot detect three or more errors. the m144k ecc status is communicated using a three-bit status flag eccstatus[2..0] . the status flag can be either registered or unregistered. when registered, it uses the same clock and asynchronous clear signals as the output registers. when unregistered, it cannot be asynchronously cleared. table 3?3 lists the truth table for the ecc status flags. 1 c fr w 1 rwr r w tab le 3 ?3 . truth table for ecc status flags status eccstatus[2] eccstatus[1] eccstatus[0] n o e r r o r 000 single error and fixed 0 1 1 double error and no fix 1 0 1 illegal 0 0 1 illegal 0 1 0 illegal 1 0 0 illegal 1 1 x 3?8 chapter 3: trimatrix embedded memory blocks in stratix iv devices memory modes stratix iv device handbook volume 1 ? march 2010 altera corporation figure 3?6 shows a diagram of the ecc block of the m144k block. memory modes stratix iv trimatrix memory blocks allow you to implement fully synchronous sram memory in multiple modes of operation. m9k and m144k blocks do not support asynchronous memory (unregistered inputs). mlabs support asynchronous (flow-through) read operations. depending on which trimatrix memory block you target, you can use the following: 1 r c r r r r r c crr r c f v r f r c rr r wr r figure 3?6. ecc block diagram of the m144k block data input 64 64 64 872 secded encoder ram array 72 64 64 8 8 8 8 64 64 3 status flags data output secded encoder comparator error correction block error locator flag generator chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?9 memory modes ? march 2010 altera corporation stratix iv device handbook volume 1 single-port ram mode all trimatrix memory blocks support single-port mode. single-port mode allows you to do either one-read or one-write operation at a time. simultaneous reads and writes are not supported in single-port mode. figure 3?7 shows the single-port ram configuration. during a write operation, ram output behavior is configurable. if you use the read-enable signal and perform a write operation with read enable de-activated, the ram outputs retain the values they held during the most recent active read enable. if you activate read enable during a write operation, or if you are not using the read-enable signal at all, the ram outputs either show the ?new data? being written, the ?old data? at that address, or a ?don?t care? value. to choose the desired behavior, set the read-during-write behavior to either new data , old data , or don?t care in the ram megawizard plug-in manager in the quartus ii software. for more information, refer to ?read-during-write behavior? on page 3?18 . table 3?4 lists the possible port width configurations for trimatrix memory blocks in single-port mode. figure 3?7. single-port ram (note 1) note to figure 3?7 : (1) you can implement two single-port memory blocks in a single m9k or m144k block. for more information, refer to ?packed mode s upport? on page 3?5 . tab le 3 ?4 . port width configurations for mlabs, m9k, and m144k blocks (single-port mode) mlabs m9k blocks m144k blocks port width configurations 64 8 64 9 6410 3216 3218 3220 8k 1 4k 2 2k 4 1k 8 1k 9 512 16 512 18 256 32 256 36 16k 8 16k 9 8k 16 8k 18 4k 32 4k 36 2k 64 2k 72 data[ ] address[ ] wren b yteena[] addressstall inclock clockena rden aclr ou tclock q[] 3?10 chapter 3: trimatrix embedded memory blocks in stratix iv devices memory modes stratix iv device handbook volume 1 ? march 2010 altera corporation figure 3?8 shows timing waveforms for read and write operations in single-port mode with unregistered outputs. registering the ram?s outputs simply delays the q output by one clock cycle. simple dual-port mode all trimatrix memory blocks support simple dual-port mode. simple dual-port mode allows you to perform one read and one write operation to different locations at the same time. write operation happens on port a; read operation happens on port b. figure 3?9 shows a simple dual-port configuration. simple dual-port mode supports different read and write data widths (mixed-width support). table 3?5 lists the mixed width configurations for m9k blocks in simple dual-port mode. mlabs do not have native support for mixed-width operation. the quartus ii software implements mixed-width memories in mlabs by using more than one mlab. figure 3?8. timing waveform for read-write operations (single-port mode) clk_a wrena rdena address a0 a1 bytenna 01 10 00 11 data_a a123 b456 c789 dddd eeee ffff q_a (asyn) a0 (old data) a1 (old data) dddd eeee b423 d old d old 23 figure 3?9. stratix iv simple dual-port memory (note 1) note to figure 3?9 : (1) simple dual-port ram supports input/output clock mode in addition to read/write clock mode. data[ ] w raddress[ ] wren b yteena[] wr_addressstall w rclock w rclocken aclr rdaddress[ ] rden q[ ] rd_addressstall rdclock rdclocken ecc_status tab le 3 ?5 . m9k block mixed-width configurations (simple dual-port mode) (part 1 of 2) read port write port 8k1 4k2 2k4 1k8 51216 25632 1k9 51218 25636 8k 1 vvvv v v ?? ? 4k 2 vvvv v v ?? ? 2k 4 vvvv v v ?? ? chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?11 memory modes ? march 2010 altera corporation stratix iv device handbook volume 1 table 3?6 lists the mixed-width configurations for m144k blocks in simple dual-port mode. in simple dual-port mode, m9k and m144k blocks support separate write-enable and read-enable signals. you can save power by keeping the read-enable signal low (inactive) when not reading. read-during-write operations to the same address can either output a ?don?t care? value or ?old data? value. to choose the desired behavior, set the read-during-write behavior to either don?t care or old data in the ram megawizard plug-in manager in the quartus ii software. for more information, refer to ?read-during-write behavior? on page 3?18 . mlabs only support a write-enable signal. for mlabs, you can set the same-port read-during-write behavior to don?t care and the mixed-port read-during-write behavior to either don?t care or old data . the available choices depend on the configuration of the mlab. there is no ?new data? option for mlabs. 1k 8 vvvv v v ?? ? 51216 vvvv v v ?? ? 25632 vvvv v v ?? ? 1k9 ???? ? ? vv v 51218 ? ? ? ? ? ? vv v 25636 ? ? ? ? ? ? vv v tab le 3 ?5 . m9k block mixed-width configurations (simple dual-port mode) (part 2 of 2) read port write port 8k1 4k2 2k4 1k8 51216 25632 1k9 51218 25636 tab le 3 ?6 . m144k block mixed-width configurations (simple dual-port mode) read port write port 16k 8 8k 16 4k 32 2k 64 16k 9 8k 18 4k 36 2k 72 16k 8 vvvv ???? 8k 16 vvvv ???? 4k 32 vvvv ???? 2k 64 vvvv ???? 16k9 ???? vvvv 8k18 ???? vvvv 4k36 ???? vvvv 2k72 ???? vvvv 3?12 chapter 3: trimatrix embedded memory blocks in stratix iv devices memory modes stratix iv device handbook volume 1 ? march 2010 altera corporation figure 3?10 shows timing waveforms for read and write operations in simple dual-port mode with unregistered outputs. registering the ram outputs simply delays the q output by one clock cycle. figure 3?11 shows timing waveforms for read and write operations in mixed-port mode with unregistered outputs. true dual-port mode stratix iv m9k and m144k blocks support true dual-port mode. sometimes called bi-directional dual-port, this mode allows you to perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies. figure 3?10. simple dual-port timing waveforms wrclock wren wraddress rdclock an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) rden rdaddress bn b0 b1 b2 b3 doutn-1 doutn dout0 din-1 din din4 din5 din6 data figure 3?11. mixed-port read-during-write timing waveforms wrclock wren wraddress rdclock an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) rden rdaddress bn b0 b1 b2 b3 doutn-1 doutn dout0 din-1 din din4 din5 din6 data chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?13 memory modes ? march 2010 altera corporation stratix iv device handbook volume 1 figure 3?12 shows the true dual-port ram configuration. the widest bit configuration of the m9k and m144k blocks in true dual-port mode is as follows: figure 3?12. stratix iv true dual-port memory (note 1) note to figure 3?12 : (1) true dual-port memory supports input/output clock mode in addition to independent clock mode. tab le 3 ?7 . m9k block mixed-width configuration (true dual-port mode) read port write port 8k1 4k2 2k4 1k8 51216 1k9 51218 8k 1 vvvvv ?? 4k 2 vvvvv ?? 2k 4 vvvvv ?? 1k 8 vvvvv ?? 51216 vvvvv ?? 1k9 ????? vv 51218 ? ? ? ? ? vv tab le 3 ?8 . m144k block mixed-width configurations (true dual-port mode) (part 1 of 2) read port write port 16k 8 8k 16 4k 32 16k 9 8k 18 4k 36 16k 8 vvv ??? 8k 16 vvv ??? 4k 32 vvv ??? data_a[ ] address_a[ ] wren_a b yteena_a[] addressstall_a clock_a rden_a aclr_a q_a[] data_b[ ] address_b[] wren_b b yteena_b[] addressstall_b clock_ b rden_b aclr_b q_b[] 3?14 chapter 3: trimatrix embedded memory blocks in stratix iv devices memory modes stratix iv device handbook volume 1 ? march 2010 altera corporation in true dual-port mode, m9k and m144k blocks support separate write-enable and read-enable signals. you can save power by keeping the read-enable signal low (inactive) when not reading. read-during-write operations to the same address can either output ?new data? at that location or ?old data?. to choose the desired behavior, set the read-during-write behavior to either new data or old data in the ram megawizard plug-in manager in the quartus ii software. for more information, refer to ?read-during-write behavior? on page 3?18 . in true dual-port mode, you can access any memory location at any time from either port. when accessing the same memory location from both ports, you must avoid possible write conflicts. a write conflict happens when you attempt to write to the same address location from both ports at the same time. this results in unknown data being stored to that address location. no conflict resolution circuitry is built into the stratix iv trimatrix memory blocks. you must handle address conflicts external to the ram block. figure 3?13 shows true dual-port timing waveforms for the write operation at port a and the read operation at port b, with the read-during-write behavior set to new data . registering the ram?s outputs simply delays the q outputs by one clock cycle. 16k 9 ? ? ? vvv 8k 18 ? ? ? vvv 4k 36 ? ? ? vvv tab le 3 ?8 . m144k block mixed-width configurations (true dual-port mode) (part 2 of 2) read port write port 16k 8 8k 16 4k 32 16k 9 8k 18 4k 36 figure 3?13. true dual-port timing waveform clk_a wren_a address_a clk_b an-1 an a0 a1 a2 a3 a4 a5 a6 q_b (asynch) wren_b address_b bn b0 b1 b2 b3 doutn-1 doutn dout0 q_a (asynch) din-1 din din4 din5 din6 data_a din-1 din dou t0 dou t1 dout2 dout3 din4 din5 dout2 dout1 chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?15 memory modes ? march 2010 altera corporation stratix iv device handbook volume 1 shift-register mode all stratix iv memory blocks support shift register mode. embedded memory block configurations can implement shift registers for digital signal processing (dsp) applications, such as finite impulse response (fir) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross-correlation functions. these and other dsp applications require local data storage, traditionally implemented with standard flipflops that quickly exhaust many logic cells for large shift registers. a more efficient alternative is to use embedded memory as a shift-register block, which saves logic cell and routing resources. the size of a shift register ( w m n ) is determined by the input data width ( w ), the length of the taps ( m ), and the number of taps ( n ). you can cascade memory blocks to implement larger shift registers. figure 3?14 shows the trimatrix memory block in shift-register mode. figure 3?14. shift-register memory configuration w w x m x n shift register m-bit shift register m-bit shift register m-bit shift register m-bit shift register w w w w w w w n number of tap s 3?16 chapter 3: trimatrix embedded memory blocks in stratix iv devices clocking modes stratix iv device handbook volume 1 ? march 2010 altera corporation rom mode all stratix iv trimatrix memory blocks support rom mode. a .mif file initializes the rom contents of these blocks. the address lines of the rom are registered on m9k and m144k blocks, but can be unregistered on mlabs. the outputs can be registered or unregistered. output registers can be asynchronously cleared. the rom read operation is identical to the read operation in the single-port ram configuration. fifo mode all trimatrix memory blocks support fifo mode. mlabs are ideal for designs with many small, shallow fifo buffers. to implement fifo buffers in your design, use the quartus ii software fifo megawizard plug-in manager. both single- and dual-clock (asynchronous) fifo buffers are supported. f r r fr ffr rfr scfifo and dcfifo megafunctions user guide . 1 r w clocking modes stratix iv trimatrix memory blocks support the following clocking modes: ?independent clock mode? on page 3?16 ?input/output clock mode? on page 3?17 ?read/write clock mode? on page 3?17 ?single clock mode? on page 3?17 1 r r c r rr c crr r c r wr r wc cc r c r r independent clock mode stratix iv trimatrix memory blocks can implement independent clock mode for true dual-port memories. in this mode, a separate clock is available for each port (clock a and clock b). clock a controls all registers on the port a side; clock b controls all registers on the port b side. each port also supports independent clock enables for both port a and port b registers, respectively. asynchronous clears are supported only for output latches and output registers on both ports. tab le 3 ?9 . trimatrix memory clock modes clocking mode tr ue dual-port mode simple dual-port mode single-port mode rom mode fifo mode independent v ?? v ? input/output vvvv ? read/write ? v ?? v single clock vvvvv chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?17 design considerations ? march 2010 altera corporation stratix iv device handbook volume 1 input/output clock mode stratix iv trimatrix memory blocks can implement input/output clock mode for true dual-port and simple dual-port memories. in this mode, an input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables. an output clock controls the data output registers. asynchronous clears are available on output latches and output registers only. read/write clock mode stratix iv trimatrix memory blocks can implement read/write clock mode for simple dual-port memories. in this mode, a write clock controls the data-input, write-address, and write-enable registers. similarly, a read clock controls the data-output, read-address, and read-enable registers. the memory blocks support independent clock enables for both the read and write clocks. asynchronous clears are available on data output latches and registers only. when using read/write clock mode, if you perform a simultaneous read/write to the same address location, the output read data is unknown. if you require the output data to be a known value, use either single-clock mode or input/output clock mode and choose the appropriate read-during-write behavior in the megawizard plug-in manager. single clock mode stratix iv trimatrix memory blocks can implement single-clock mode for true dual-port, simple dual-port, and single-port memories. in this mode, a single clock, together with a clock enable, is used to control all registers of the memory block. asynchronous clears are available on output latches and output registers only. design considerations this section describes guidelines for designing with trimatrix memory blocks. selecting trimatrix memory blocks the quartus ii software automatically partitions user-defined memory into embedded memory blocks by taking into account both speed and size constraints placed on your design. for example, the quartus ii software may spread memory out across multiple memory blocks when resources are available to increase the performance of the design. you can manually assign memory to a specific block size using the ram megawizard plug-in manager. mlabs can implement single-port sram through emulation using the quartus ii software. emulation results in minimal additional logic resources being used. because of the dual-purpose architecture of the mlab, it only has data input registers and output registers in the block. mlabs gain input address registers and additional data output registers from alms. f r r fr rr c rfr logic array blocks and adaptive logic modules in stratix iv devices chapter. 3?18 chapter 3: trimatrix embedded memory blocks in stratix iv devices design considerations stratix iv device handbook volume 1 ? march 2010 altera corporation conflict resolution when using memory blocks in true dual-port mode, it is possible to attempt two write operations to the same memory location (address). because no conflict resolution circuitry is built into the memory blocks, this results in unknown data being written to that location. therefore, you must implement conflict resolution logic external to the memory block to avoid address conflicts. read-during-write behavior you can customize the read-during-write behavior of the stratix iv trimatrix memory blocks to suit your design needs. two types of read-during-write operations are available: same port and mixed port. figure 3?15 shows the difference between the two types. same-port read-during-write mode this mode applies to either a single-port ram or the same port of a true dual-port ram. for mlabs, the output of the mlabs can only be set to don?t care in same-port read-during-write mode. in this mode, the output of the mlabs is unknown during a write cycle. there is a window near the falling edge of the clock during which the output is unknown. prior to that window, ?old data? is read out; after that window, ?new data? is seen at the output. figure 3?15. stratix iv read-during-write data flow port a data in port b data in port a data out port b data out mixed-port data flow same-port data flow chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?19 design considerations ? march 2010 altera corporation stratix iv device handbook volume 1 figure 3?16 shows sample functional waveforms of same-port read-during-write behavior in don?t care mode for mlabs. for m9k and m144k memory blocks, three output choices are available in same-port read-during-write mode: ?new data? (or flow-through) or ?old data?. in new data mode, the ?new data? is available on the rising edge of the same clock cycle on which it was written. in old data mode, the ram outputs reflect the ?old data? at that address before the write operation proceeds. in don?t care mode, the ram outputs ?unknown values? for a read-during-write operation. figure 3?17 shows sample functional waveforms of same-port read-during-write behavior in new data mode for m9k and m144k blocks. figure 3?16. mlabs same-port read-during write: don?t care mode figure 3?17. m9k and m144k blocks same-port read-during-write: new data mode clk_a wrena data_in address a1 q(unregistered) a0(old data) a2 ffff aaaa xxxx xx ffff aaaa a1(old data) a2(old data) q(registered) ffff aaaa a0 xx xx xx clk_a wrena rdena address 0a 0b bytenna 01 10 00 11 data_a a123 b456 c789 dddd eeee ffff q_a (asyn) xx23 b423 b423 dddd eeee ffff 3?20 chapter 3: trimatrix embedded memory blocks in stratix iv devices design considerations stratix iv device handbook volume 1 ? march 2010 altera corporation figure 3?18 shows sample functional waveforms of same-port read-during-write behavior in old data mode for m9k and m144k blocks. mixed-port read-during-write mode this mode applies to a ram in simple or true dual-port mode that has one port reading from and the other port writing to the same address location with the same clock. in this mode, you also have two output choices: ?old data? or ?don?t care?. in old data mode, a read-during-write operation to different ports causes the ram outputs to reflect the ?old data? at that address location. in don?t care mode, the same operation results in a ?don?t care? or ?unknown? value on the ram outputs. f rwr vr cr w r r r r fr rfr internal memory (ram and rom) user guide . figure 3?19 shows a sample functional waveform of mixed-port read-during-write behavior for old data mode in mlabs. figure 3?18. m9k and m144k blocks same-port read-during-write: old data mode clk_a wrena rdena address a0 a1 bytenna 01 10 00 11 data_a a123 b456 c789 dddd eeee ffff q_a (asyn) a0 (old data) a1 (old data) dddd eeee b423 d old d old 23 figure 3?19. mlabs mixed-port read-during-write: old data mode clk_a wrena data_in wraddress a1 byteena_a q_b(registered) a0 rdaddress a1 a0 aaaa bbbb cccc dddd eeee ffff a0 (old data) a1 (old data) dddd aabb aaaa 11 01 10 11 01 10 ddee chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?21 design considerations ? march 2010 altera corporation stratix iv device handbook volume 1 figure 3?20 shows a sample functional waveform of mixed-port read-during-write behavior for don?t care mode in mlabs. figure 3?21 shows a sample functional waveform of mixed-port read-during-write behavior for old data mode in m9k and m144k blocks. figure 3?20. mlabs mixed-port read-during-write: don?t care mode figure 3?21. m9k and m144k blocks mixed-port read-during write: old data mode clk_a wrena data_in wraddress a1 byteena_a q_b(registered) a0 rdaddress a1 a0 aaaa bbbb cccc dddd eeee ffff aaaa dddd ddee ccbb aabb 11 01 10 11 01 10 ffee clk_a&b wrena address_a bytenna 11 01 11 data_a q_b_(asyn) a0 (old data) a1 (old data) dddd eeee aabb aaaa a1 a0 aaaa bbbb cccc dddd eeee ffff a1 a0 address_b 10 rdenb 3?22 chapter 3: trimatrix embedded memory blocks in stratix iv devices design considerations stratix iv device handbook volume 1 ? march 2010 altera corporation figure 3?22 shows a sample functional waveform of mixed-port read-during-write behavior for don?t care mode in m9k and m144k blocks. mixed-port read-during-write is not supported when two different clocks are used in a dual-port ram. the output value is unknown during a dual-clock mixed-port read-during-write operation. power-up conditions and memory initialization m9k and m144k memory block outputs power up to zero (cleared), regardless of whether the output registers are used or bypassed. mlabs power up to zero if output registers are used and power up reading the memory contents if output registers are not used. you must take this into consideration when designing logic that might evaluate the initial power-up values of the mlab memory block. for stratix iv devices, the quartus ii software initializes the ram cells to zero unless there is a .mif file specified. all memory blocks support initialization using a .mif file. you can create .mif files in the quartus ii software and specify their use with the ram megawizard plug-in manager when instantiating a memory in your design. even if a memory is pre-initialized (for example, using a .mif file), it still powers up with its outputs cleared. f r r fr .mif files, refer to the internal memory (ram and rom) user guide and the quartus ii handbook . power management stratix iv memory block clock-enables allow you to control clocking of each memory block to reduce ac power consumption. use the read-enable signal to ensure that read operations only occur when you need them to. if your design does not need read-during-write, you can reduce your power consumption by de-asserting the read-enable signal during write operations, or any period when no memory operations occur. the quartus ii software automatically places any unused memory blocks in low-power mode to reduce static power. figure 3?22. m9k and m144k blocks mixed-port read-during write: don?t care mode clk_a&b wrena rdenb address_a a0 a1 bytenna 11 01 10 11 data_a aaaa bbbb cccc dddd eeee ffff q_b_(asyn) xxxx (unknown data) address_b a0 a1 chapter 3: trimatrix embedded memory blocks in stratix iv devices 3?23 document revision history ? march 2010 altera corporation stratix iv device handbook volume 1 document revision history table 3?10 lists the revision history for this chapter. table 3?10. document revision history date and document version changes made summary of changes march 2010 v3.1 updated the ?simple dual-port mode? , ?same-port read-during- write mode? , and ?mixed-port read-during-write mode? sections. updated figure 3?14 . minor text edits. ? november 2009 v3.0 updated table 3?2. updated the ?simple dual-port mode? section. minor text edits. updated graphics. ? june 2009 v2.3 updated table 3?1 and figure 3?2. updated the ?introduction?, ?byte enable support?, ?mixed width support?, ?asynchronous clear?, ?single-port ram?, ?simple dual- port mode?, ?true dual-port mode?, ?fifo mode?, and ?read/write clock mode? sections. added introductory sentences to improve search ability. removed the conclusion section. minor text edits. ? april 2009 v2.2 updated table 3?2. ? march 2009 v2.1 updated table 3?2. removed ?referenced documents? section. ? november 2008 v2.0 updated ?power-up conditions and memory initialization? on page 3?20 ? may 2008 v1.0 initial release. ? 3?24 chapter 3: trimatrix embedded memory blocks in stratix iv devices document revision history stratix iv device handbook volume 1 ? march 2010 altera corporation ? november 2009 altera corporation stratix iv device handbook volume 1 4. dsp blocks in stratix iv devices this chapter describes how the stratix ? iv device digital signal processing (dsp) blocks are optimized to support dsp applications requiring high data throughput, such as finite impulse response (fir) filters, infinite impulse response (iir) filters, fast fourier transform (fft) functions, and encoders. you can configure the dsp blocks to implement one of several operational modes to suit your application. the built-in shift register chain, multipliers, and adders/subtractors minimize the amount of external logic to implement these functions, resulting in efficient resource utilization and improved performance and data throughput for dsp applications. many complex systems, such as wimax, 3gpp wcdma, high-performance computing (hpc), voice over internet protocol (voip), h.264 video compression, medical imaging, and hdtv use sophisticated digital signal processing techniques, which typically require a large number of mathematical computations. stratix iv devices are ideally suited for these tasks because the dsp blocks consist of a combination of dedicated elements that perform multiplication, addition, subtraction, accumulation, summation, and dynamic shift operations. along with the high-performance stratix iv soft logic fabric and trimatrix memory structures, you can configure dsp blocks to build sophisticated fixed-point and floating-point arithmetic functions. these can be manipulated easily to implement common, larger computationally intensive subsystems such as fir filters, complex fir filters, iir filters, fft functions, and discrete cosine transform (dct) functions. this chapter contains the following sections: siv51004-3.0 4?2 chapter 4: dsp blocks in stratix iv devices stratix iv dsp block overview stratix iv device handbook volume 1 ? november 2009 altera corporation stratix iv dsp block overview each stratix iv device has two to seven columns of dsp blocks that implement multiplication, multiply-add, multiply-accumulate (mac), and dynamic shift functions efficiently. architectural highlights of the stratix iv dsp block include: tab le 4 ?1 . number of dsp blocks in stratix iv devices (part 1 of 2) family device dsp blocks independent input and output multiplication operators high-precision multiplier adder mode four multiplier adder mode 99 multipliers 1212 multipliers 1818 multipliers 18 18 complex 36 36 multipliers 18 36 multipliers 18 18 multipliers stratix iv e ep4se230 161 1288 966 644 322 322 644 1288 ep4se360 130 1040 780 520 260 260 520 1040 ep4se530 128 1024 768 512 256 256 512 1024 ep4se820 120 960 720 480 240 240 480 960 stratix iv gx ep4sgx70 48 384 288 192 96 96 192 384 ep4sgx110 64 512 384 256 128 128 256 512 ep4sgx180 115 920 690 460 230 230 460 920 ep4sgx230 161 1288 966 644 322 322 644 1288 ep4sgx290 104 832 624 416 208 208 416 832 ep4sgx360 (1) 130 1040 780 520 260 260 520 1040 ep4sgx360 (2) 128 1024 768 512 256 256 512 1024 ep4sgx530 128 1024 768 512 256 256 512 1024 chapter 4: dsp blocks in stratix iv devices 4?3 stratix iv simplified dsp operation ? november 2009 altera corporation stratix iv device handbook volume 1 table 4?1 shows that the largest stratix iv dsp-centric device provides up to 1288 18 18 multiplier functionality in the 36 36, complex 18 18, and summation modes. each dsp block occupies four labs in height and can be divided further into two half blocks that share some common clock signals, but are for all common purposes identical in functionality. figure 4?1 shows the layout of each dsp block. stratix iv simplified dsp operation in stratix iv devices, the fundamental building block is a pair of 18 18-bit multipliers followed by a first-stage 37-bit addition/subtraction unit, as shown in equation 4?1 and figure 4?2 . 1 r r rr c fr stratix iv gt ep4s40g2 161 1288 966 644 322 322 644 1288 ep4s40g5 128 1024 768 512 256 256 512 1024 ep4s100g2 161 1288 966 644 322 322 644 1288 ep4s100g3 104 832 624 416 208 208 416 832 ep4s100g4 128 1024 768 512 256 256 512 1024 ep4s100g5 128 1024 768 512 256 256 512 1024 notes to ta bl e 4? 1 : (1) this is applicable for al l packages in ep 4sgx360 excep t f1932. (2) this is applicable for ep4sgx360f1932 only. tab le 4 ?1 . number of dsp blocks in stratix iv devices (part 2 of 2) family device dsp blocks independent input and output multiplication operators high-precision multiplier adder mode four multiplier adder mode 99 multipliers 1212 multipliers 1818 multipliers 18 18 complex 36 36 multipliers 18 36 multipliers 18 18 multipliers figure 4?1. overview of dsp block signals 34 144 144 288 72 72 half-dsp block half-dsp block output data output data fu ll dsp block control input data 4?4 chapter 4: dsp blocks in stratix iv devices stratix iv simplified dsp operation stratix iv device handbook volume 1 ? november 2009 altera corporation the structure shown in figure 4?2 is useful for building more complex structures, such as complex multipliers and 36 36 multipliers, as described in later sections. each stratix iv dsp block contains four two-multiplier adder units (2 two-multiplier adder units per half block). therefore, there are eight 18 18 multiplier functionalities per dsp block. following the two-multiplier adder units are the pipeline registers, the second-stage adders, and an output register stage. you can configure the second-stage adders to provide the alternative functions per half block, as shown in equation 4?2 and equation 4?3 . in these equations, n denotes sample time and p[36..0] denotes the result from the two-multiplier adder units. equation 4?1. multiplier equation p[36..0] = a 0 [17..0] b 0 [17..0] a 1 [17..0] b 1 [17..0] figure 4?2. basic two-multiplier adder building block equation 4?2. four-multiplier adder equation z[37..0] = p 0 [36..0] + p 1 [36..0] equation 4?3. four-multiplier adder equation (44-bit accumulation) w n [43..0] = w n-1 [43..0] z n [37..0] dq dq a0[17..0] a1[17..0] b1[17..0] b0[17..0] p[36..0] +/- chapter 4: dsp blocks in stratix iv devices 4?5 stratix iv simplified dsp operation ? november 2009 altera corporation stratix iv device handbook volume 1 equation 4?2 provides a sum of four 18 18-bit multiplication operations (four-multiplier adder). equation 4?3 provides a four 18 18-bit multiplication operation but with a maximum 44-bit accumulation capability by feeding the output of the unit back to itself, as shown in figure 4?3 . depending on the mode you select, you can bypass all register stages except accumulation and loopback mode. in these two modes, one set of register must be enabled. if the register is not enabled, an infinite loop occurs. to support commonly found fir-like structures efficiently, a major addition to the dsp block in stratix iv devices is the ability to propagate the result of one half block to the next half block completely within the dsp block without additional soft logic overhead. this is achieved by the inclusion of a dedicated addition unit and routing that adds the 44-bit result of a previous half block with the 44-bit result of the current block. the 44-bit result is either fed to the next half block or out of the dsp block using the output register stage, as shown in figure 4?4 . detailed examples are described in later sections. figure 4?3. four-multiplier adder and accumulation capability + + 144 44 input data input register bank adder/ accum ulator output register bank half-dsp block result[] pipeline register bank 4?6 chapter 4: dsp blocks in stratix iv devices stratix iv simplified dsp operation stratix iv device handbook volume 1 ? november 2009 altera corporation the combination of a fast, low-latency four-multiplier adder unit and the ?chained cascade? capability of the output chaining adder provides the optimal fir and vector multiplication capability. to support single-channel type fir filters efficiently, you can configure one of the multiplier input?s registers to form a tap delay line input, saving resources and providing higher system performance. also shown in figure 4?4 is the optional rounding and saturation unit (rsu). this unit provides a rich set of commonly found arithmetic rounding and saturation functions used in signal processing. in addition to the independent multipliers and sum modes, you can use dsp blocks to perform shift operations. dsp blocks can dynamically switch between logical shift left/right, arithmetic shift left/right, and rotation operation in one clock cycle. figure 4?4. output cascading feature for fir structures 144 44 44 from pre viou s half dsp block to n ext half dsp block input data input register bank adder/ accum ulator round/satu rate output register bank 44 half dsp block result[] pipeline register bank chapter 4: dsp blocks in stratix iv devices 4?7 stratix iv simplified dsp operation ? november 2009 altera corporation stratix iv device handbook volume 1 figure 4?5 shows a top-level view of the stratix iv dsp block. figure 4?6 on page 4?9 shows a more detailed top-level view of the dsp block. figure 4?5. stratix iv full dsp block input register bank pipeline register bank adder/accum ulator output mu ltiplexer round/satu rate output register bank from pre vious half dsp block to n ext half dsp block 44 44 input data 144 input register bank pipeline register bank adder/accum ulator output mu ltiplexter round/satu rate output register bank input data 144 top half dsp block bottom half dsp block result[] result[] 4?8 chapter 4: dsp blocks in stratix iv devices stratix iv operational modes overview stratix iv device handbook volume 1 ? november 2009 altera corporation stratix iv operational modes overview you can use each stratix iv dsp block in one of five basic operational modes. table 4?2 shows the five basic operational modes and the number of multipliers that you can implement within a single dsp block, depending on the mode. the dsp block consists of two identical halves (the top half and bottom half). each half has four 18 18 multipliers. the quartus ? ii software includes megafunctions used to control the mode of operation of the multipliers. after making the appropriate parameter settings using the megafunction?s megawizard ? , clock, ena , and aclr signals. for example, you can break down a single dsp block to operate a 9 9 multiplier in one half block and an 18 18 two-multiplier adder in the other half block. this increases dsp block resource efficiency and allows you to implement more multipliers within a stratix iv device. the quartus ii software automatically places multipliers that can share the same dsp block resources within the same block. tab le 4 ?2 . stratix iv dsp block operation modes mode multiplier in width # of mults # per block signed or unsigned rnd, sat in shift register chainout adder 1st stage add/sub 2nd stage add/acc independent multiplier 9 bits 1 8 both no no no ? ? 12 bits 1 6 both no no no ? ? 18 bits 1 4 both yes yes no ? ? 36 bits 1 2 both no no no ? ? double 1 2 both no no no ? ? two-multiplier adder (1) 18 bits 2 4 signed (4) yes no no both ? four-multiplier adder 18 bits 4 2 both yes yes yes both add only multiply accumulate 18 bits 4 2 both yes yes yes both both shift (2) 36 bits (3) 1 2 both no no ? ? ? high precision multiplier adder 18 36 2 2 both no no no ? add only notes to ta bl e 4? 2 : (1) this mode also supports loopback mode. in loopback mode, the number of loopback multipliers per dsp block is two. you can us e the remaining multipliers in regular two-multiplier adder mode. (2) dynamic shift mode supports arithmetic shift left, arithmetic shift right, logical shift left, logical shift right, and rotation operation. (3) dynamic shift mode operates on a 32-bit input vector but the multiplier width is configured as 36 bits. (4) unsigned value is also supported but you must ensure that the result can be contained within 36 bits. chapter 4: dsp blocks in stratix iv devices 4?9 stratix iv dsp block resource descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 stratix iv dsp block resource descriptions the dsp block consists of the following elements: figure 4?6. half dsp block architecture notes to figure 4?6 : (1) block output for accumulator overflow and saturate overflow. (2) block output for saturation overflow of chainout. (3) the chainin port must only be connected to chainout of the previous dsp blocks and must not be connected to general routings. chainin[ ] (3) scanina[ ] dataa_0[ ] datab_0[ ] dataa_1[ ] datab_1[ ] dataa_2[ ] datab_2[ ] dataa_3[ ] scanouta chainout datab_3[ ] input register bank first stage adder first stage adder pipeline register bank second stage adder/accum ulator first round/satu rate second adder register bank chainout adder second round/satu rate output register bank shift/rotate result[ ] clock[3..0] ena[3..0] alcr[3..0] zero_loop b ack accum_sload zero_chaino ut chainout_round chainout_satu rate signa signb output_round output_satu rate rotate shift_right o v erflo w (1) chainout_sat_o v erflo w (2 ) half-dsp block loopb ack mu ltiplexer 4?10 chapter 4: dsp blocks in stratix iv devices stratix iv dsp block resource descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation input registers all of the dsp block registers are triggered by the positive edge of the clock signal and are cleared upon power up. each multiplier operand can feed an input register or go directly to the multiplier, bypassing the input registers. the following dsp block signals control the input registers within the dsp block: clock[3..0] ena[3..0] aclr[3..0] every dsp block has nine 18-bit data input register banks per half dsp block. every half dsp block has the option to use the eight data register banks as inputs to the four multipliers. the special ninth register bank is a delay register required by modes that use both the cascade and chainout features of the dsp block. use the ninth register bank to balance the latency requirements when using the chained cascade feature. a feature of the input register bank is to support a tap delay line. therefore, the top leg of the multiplier input (a) can be driven from general routing or from the cascade chain, as shown in figure 4?7 . table 4?9 on page 4?33 lists the dsp block dynamic signals. chapter 4: dsp blocks in stratix iv devices 4?11 stratix iv dsp block resource descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 at compile time, you must select whether the a-input comes from general routing or from the cascade chain. in cascade mode, the dedicated shift outputs from one multiplier block and directly feeds the input registers of the adjacent multiplier below it (within the same half dsp block) or the first multiplier in the next half dsp block, to form an 8-tap shift register chain per dsp block. the dsp block can increase the length of the shift register chain by cascading to the lower dsp blocks. the dedicated shift register chain spans a single column, but you can implement longer shift register chains requiring multiple columns using the regular fpga routing resources. figure 4?7. input register of a half dsp block +/- +/- signa signb clock[3..0] ena[3..0] aclr[3..0] scanina[17..0] dataa_0[17..0] loopb ack datab_0[17..0] dataa_1[17..0] datab_1[17..0] dataa_2[17..0] datab_2[17..0] dataa_3[17..0] datab_3[17..0] scanouta delay register 4?12 chapter 4: dsp blocks in stratix iv devices stratix iv dsp block resource descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation shift registers are useful in dsp functions such as fir filters. when implementing 18 18 or smaller width multipliers, you do not need external logic to create the shift register chain because the input shift registers are internal to the dsp block. this implementation significantly reduces the logical element (le) resources required, avoids routing congestion, and results in predictable timing. the first multiplier in every half dsp block (top- and bottom-half) in stratix iv devices has a multiplexer for the first multiplier b-input (lower-leg input) register to select between general routing and loopback, as shown in figure 4?6 on page 4?9 . in loopback mode, the most significant 18-bit registered outputs are connected as feedback to the multiplier input of the first top multiplier in each half dsp block. loopback modes are used by recursive filters where the previous output is needed to compute the current output. loopback mode is described in ?two-multiplier adder sum mode? on page 4?22 . table 4?3 lists input register modes for the dsp block. multiplier and first-stage adder the multiplier stage natively supports 9 9, 12 12, 18 18, or 36 36 multipliers. other wordlengths are padded up to the nearest appropriate native wordlength; for example, 16 16 would be padded up to use 18 18. for more information, refer to ?independent multiplier modes? on page 4?15 . depending on the data width of the multiplier, a single dsp block can perform many multiplications in parallel. each multiplier operand can be a unique signed or unsigned number. two dynamic signals, signa and signb , control the representation of each operand, respectively. a logic 1 value on the signa/signb signal indicates that data a/data b is a signed number; a logic 0 value indicates an unsigned number. ta b l e 4 ?4 shows the sign of the multiplication result for the various operand sign representations. the result of the multiplication is signed if any one of the operands is a signed value. tab le 4 ?3 . input register modes register input mode (1) 99 1212 1818 3636 double parallel input vvvvv shift register input (2) ?? v ?? loopback input (3) ?? v ?? notes to ta bl e 4? 3 : (1) multiplier operand input wordlengths are statically configured at compile time. (2) available only on the a-operand. (3) only one loopback input is allowed per half block. for more information, refer to figure 4?15 on page 4?23 . chapter 4: dsp blocks in stratix iv devices 4?13 stratix iv dsp block resource descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 each half block has its own signa and signb signal. therefore, all of the data a inputs feeding the same half dsp block must have the same sign representation. similarly, all of the data b inputs feeding the same half dsp block must have the same sign representation. the multiplier offers full precision regardless of the sign representation in all operational modes except for full precision 18 18 loopback and two-multiplier adder modes. for more information, refer to ?two-multiplier adder sum mode? on page 4?22 . 1 f w signa and signb signals are unused, the quartus ii software sets the multiplier to perform unsigned multiplication. figure 4?6 on page 4?9 shows that the outputs of the multipliers are the only outputs that can feed into the first-stage adder. there are four first-stage adders in a dsp block (two adders per half dsp block). the first-stage adder block has the ability to perform addition and subtraction. the control signal for addition or subtraction is static and has to be configured upon compile time. the first-stage adders are used by the sum modes to compute the sum of two multipliers, 18 18-complex multipliers, and to perform the first stage of a 36 36 multiply and shift operations. depending on your specifications, the output of the first-stage adder has the option to feed into the pipeline registers, second-stage adder, rounding and saturation unit, or output registers. pipeline register stage figure 4?6 on page 4?9 shows that the output from the first-stage adder can either feed or bypass the pipeline registers. pipeline registers increase the dsp block?s maximum performance (at the expense of extra cycles of latency), especially when using the subsequent dsp block stages. pipeline registers split up the long signal path between the input registers/multiplier/first-stage adder and the second-stage adder/ round-and-saturation/output registers, creating two shorter paths. second-stage adder there are four individual 44-bit second-stage adders per dsp block (two adders per half dsp block). you can configure the second-stage adders as follows: tab le 4 ?4 . multiplier sign representation data a (signa value) data b (signb value) result unsigned (logic 0) unsigned (logic 0) unsigned unsigned (logic 0) signed (logic 1) signed signed (logic 1) unsigned (logic 0) signed signed (logic 1) signed (logic 1) signed 4?14 chapter 4: dsp blocks in stratix iv devices stratix iv dsp block resource descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation 1 you can use the chained-output adder at the same time as a second-level adder in chained output summation mode. the output of the second-stage adder has the option to go into the rounding and saturation logic unit or the output register. 1 you cannot use the second-stage adder independently from the multiplier and first-stage adder. rounding and saturation stage the rounding and saturation logic units are located at the output of the 44-bit second-stage adder (the rounding logic unit followed by the saturation logic unit). there are two rounding and saturation logic units per half dsp block. the input to the rounding and saturation logic unit can come from one of the following stages: output of the multiplier (independent multiply mode in 18 18) output of the first-stage adder (two-multiplier adder) output of the pipeline registers output of the second-stage adder (four-multiplier adder and multiply-accumulate mode in 18 18) these stages are described in ?stratix iv operational mode descriptions? on page 4?15 . the rounding and saturation logic unit is controlled by the dynamic rounding and saturate signals, respectively. a logic 1 value on the rounding and/or saturate signals enables the rounding and/or saturate logic unit, respectively. 1 you can use the rounding and saturation logic units together or independently. second adder and output registers the second adder register and output register banks are two banks of 44-bit registers that you can combine to form larger 72-bit banks to support 36 36 output results. the outputs of the different stages in the stratix iv devices are routed to the output registers through an output selection unit. depending on the operational mode of the dsp block, the output selection unit selects whether the outputs of the dsp blocks comes from the outputs of the multiplier block, first-stage adder, pipeline registers, second-stage adder, or the rounding and saturation logic unit. the output selection unit is set automatically by the software, based on the dsp block operational mode you specified, and has the option to either drive or bypass the output registers. the exception is when you use the block in shift mode, in which case you dynamically control the output-select multiplexer directly. when the dsp block is configured in chained cascaded output mode, both of the second-stage adders are used. use the first one for performing a four-multiplier adder; use the second for the chainout adder. chapter 4: dsp blocks in stratix iv devices 4?15 stratix iv operational mode descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 the outputs of the four-multiplier adder are routed to the second-stage adder registers before they enter the chainout adder. the output of the chainout adder goes to the regular output register bank. depending on the configuration, you can route the chainout results to the input of the next half block?s chainout adder input or to the general fabric (functioning as regular output registers). for more information, refer to ?stratix iv operational mode descriptions? on page 4?15 . the second-stage and output registers are triggered by the positive edge of the clock signal and are cleared on power up. the following dsp block signals control the output registers within the dsp block: clock[3..0] ena[3..0] aclr[3..0] stratix iv operational mode descriptions this section contains an explanation of different operational modes in stratix iv devices. independent multiplier modes in independent input and output multiplier mode, the dsp block performs individual multiplication operations for general-purpose multipliers. 9-, 12-, and 18-bit multiplier you can configure each dsp block multiplier for 9-, 12-, or 18-bit multiplication. a single dsp block can support up to eight individual 9 9 multipliers, six individual 12 12 multipliers, or four individual 18 18 multipliers. for operand widths up to 9 bits, a 9 9 multiplier is implemented. for operand widths from 10 to 12 bits, a 12 12 multiplier is implemented, and for operand widths from 13 to 18 bits, an 18 18 multiplier is implemented. this is done by the quartus ii software by zero-padding the lsbs. figure 4?8 , figure 4?9 , and figure 4?10 show the dsp block in the independent multiplier operation. table 4?9 on page 4?33 lists the dynamic signals for the dsp block. 4?16 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation figure 4?8. 18-bit independent multiplier mode shown for a half dsp block note to figure 4?8 : (1) block output for accumulator overflow and saturate overflow. clock[3..0] ena[3..0] aclr[3..0] signa signb output_round output_satu rate o v erflo w (1) 36 36 dataa_0[17..0] datab_0[17..0] dataa_1[17..0] datab_1[17..0] half-dsp block input register bank pipeline register bank round/satu rate round/satu rate output register bank 18 18 18 18 result_0[ ] result_1[ ] chapter 4: dsp blocks in stratix iv devices 4?17 stratix iv operational mode descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 figure 4?9. 12-bit independent multiplier mode shown for a half dsp block 24 12 12 12 12 12 12 24 24 input register bank pipeline register bank output register bank clock[3..0] ena[3..0] aclr[3..0] signa signb half-dsp block dataa_0[11..0] datab_0[11..0] dataa_1[11..0] datab_1[11..0] dataa_2[11..0] datab_2[11..0] result_0[ ] result_1[ ] result_2[ ] 4?18 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation the multiplier operands can accept signed integers, unsigned integers, or a combination of both. you can change the signa and signb signals dynamically and can register the signals in the dsp block. additionally, the multiplier inputs and results can be registered independently. you can use the pipeline registers within the dsp block to pipeline the multiplier result, increasing the performance of the dsp block. 1 r r c r fr 1 r figure 4?10. 9-bit independent multiplier mode shown for a half block 18 9 9 9 9 18 9 9 18 9 9 18 input register bank pipeline register bank output register bank dataa_0[8..0] datab_0[8..0] dataa_1[8..0] datab_1[8..0] dataa_2[8..0] datab_2[8..0] dataa_3[8..0] datab_3[8..0] half-dsp block clock[3..0] ena[3..0] aclr[3..0] signa signb result_0[ ] result_1[ ] result_2[ ] result_3[ ] chapter 4: dsp blocks in stratix iv devices 4?19 stratix iv operational mode descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 36-bit multiplier you can efficiently construct a 36 36 multiplier using four 18 18 multipliers. this simplification fits conveniently into one half dsp block and is implemented in the dsp block automatically by selecting 36 36 mode. stratix iv devices can have up to two 36-bit multipliers per dsp block (one 36-bit multiplier per half dsp block). the 36-bit multiplier is also under the independent multiplier mode but uses the entire half dsp block, including the dedicated hardware logic after the pipeline registers to implement the 36 36 bit multiplication operation, as shown in figure 4?11 . the 36-bit multiplier is useful for applications requiring more than 18-bit precision; for example, for the mantissa multiplication portion of single precision and extended single precision floating-point arithmetic applications. figure 4?11. 36-bit independent multiplier mode shown for a half dsp block pipeline register bank input register bank output register bank half-dsp block dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] 72 clock[3..0] ena[3..0] aclr[3..0] signa signb + + + result[ ] 4?20 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation double multiplier you can configure the stratix iv dsp block to efficiently support a signed or unsigned 54 54-bit multiplier that is required to compute the mantissa portion of an ieee double-precision floating point multiplication. you can build a 54 54-bit multiplier using basic 18 18 multipliers, shifters, and adders. in order to efficiently utilize the stratix iv dsp block?s built-in shifters and adders, a special double mode (partial 54 54 multiplier) is available that is a slight modification to the basic 36 36 multiplier mode, as shown in figure 4?12 and figure 4?13 . figure 4?12. double mode shown for a half dsp block pipeline register bank input register bank output register bank half-dsp block dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] 72 clock[3..0] ena[3..0] aclr[3..0] signa signb + + + result[ ] chapter 4: dsp blocks in stratix iv devices 4?21 stratix iv operational mode descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 figure 4?13. unsigned 54 54 multiplier for a half-dsp block shifters and adders double mode shifters and adders 36 x 36 mode + two multiplier adder mode final adder (implemented with alut logic) 36 55 72 108 result[ ] unsigned 54 x 54 multiplier "0" "0" dataa[53..36] dataa[53..36] dataa[53..36] datab[53..36] dataa[35..18] datab[53..36] dataa[17..0] datab[53..36] datab[35..18] datab[17..0] clock[3..0] ena[3..0] aclr[3..0] signa signb dataa[35..18] dataa[35..18] datab[35..18] datab[17..0] datab[17..0] dataa[17..0] datab[35..18] dataa[17..0] 4?22 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation two-multiplier adder sum mode in the two-multiplier adder configuration, the dsp block can implement four 18-bit two-multiplier adders (2 two-multiplier adders per half dsp block). you can configure the adders to take the sum or difference of two multiplier outputs. you must select summation or subtraction at compile time. the two-multiplier adder function is useful for applications such as ffts, complex fir, and iir filters. figure 4?14 shows the dsp block configured in two-multiplier adder mode. loopback mode is the other sub-feature of the two-multiplier adder mode. figure 4?15 shows the dsp block configured in the loopback mode. this mode takes the 36-bit summation result of the two multipliers and feeds back the most significant 18-bits to the input. the lower 18-bits are discarded. you have the option to disable or zero-out the loopback data by using the dynamic zero_loopback signal. a logic 1 value on the zero_loopback signal selects the zeroed data or disables the looped back data, while a logic 0 selects the looped back data. 1 c c r r wr r c r wr r f r f 1 r rr w wr r rr w r c v r r fr w 1 1 wr r v wr r r r r c c rr rr w c rr r cr rfrc f c figure 4?14. two-multiplier adder mode shown for a half dsp block note to figure 4?14 : (1) block output for accumulator overflow and saturate overflow. input register bank pipeline register bank round/satu rate output register bank clock[3..0] ena[3..0] aclr[3..0] signa signb output_round output_satu rate o v erflo w (1) result[ ] + dataa_0[17..0] datab_0[17..0] dataa_1[17..0] datab_1[17..0] half-dsp block chapter 4: dsp blocks in stratix iv devices 4?23 stratix iv operational mode descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 18 x 18 complex multiply you can configure the dsp block to implement complex multipliers using two-multiplier adder mode. a single half dsp block can implement one 18-bit complex multiplier. equation 4?4 shows a complex multiplication. to implement this complex multiplication within the dsp block, the real part ((a c) ? (b d)) is implemented using two multipliers feeding one subtractor block while the imaginary part ((a d) + (b c)) is implemented using another two multipliers feeding an adder block. figure 4?16 shows an 18-bit complex multiplication. this mode automatically assumes all inputs are using signed numbers. figure 4?15. loopback mode for a half dsp block note to figure 4?15 : (1) block output for accumulator overflow and saturate overflow. input register bank pipeline register bank round/satu rate output register bank dataa_0[17..0] datab_0[17..0] dataa_1[17..0] datab_1[17..0] zero_loop b ack clock[3..0] ena[3..0] aclr[3..0] signa signb output_round output_satu rate o v erflo w (1) result[ ] + loopb ack half-dsp block equation 4?4. complex multiplication equation (a + jb) (c + jd) = ((a c) ? (b d)) + j((a d) + (b c)) 4?24 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation four-multiplier adder in the four-multiplier adder configuration shown in figure 4?17 , the dsp block can implement two four-multiplier adders (one four-multiplier adder per half dsp block). these modes are useful for implementing one-dimensional and two-dimensional filtering applications. the four-multiplier adder is performed in two addition stages. the outputs of two of the four multipliers are initially summed in the two first-stage adder blocks. the results of these two adder blocks are then summed in the second-stage adder block to produce the final four-multiplier adder result, as shown by equation 4?2 on page 4?4 and equation 4?3 on page 4?4 . figure 4?16. complex multiplier using two-multiplier adder mode input register bank pipeline register bank output register bank a x cb x d real part a x db x c imaginary part clock[3..0] ena[3..0] aclr[3..0] signa signb a c b d half-dsp block 36 36 chapter 4: dsp blocks in stratix iv devices 4?25 stratix iv operational mode descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 four-multiplier adder mode supports the rounding and saturation logic unit. you can use the pipeline registers and output registers within the dsp block to pipeline the multiplier-adder result, increasing the performance of the dsp block. figure 4?17. four-multiplier adder mode shown for a half dsp block note to figure 4?17 : (1) block output for accumulator overflow and saturate overflow. clock[3..0] ena[3..0] aclr[3..0] signa signb output_round output_satu rate o v erflo w (1) input register bank pipeline register bank round/satu rate output register bank dataa_0[ ] datab_0[ ] dataa_1[ ] datab_1[ ] dataa_2[ ] datab_2[ ] dataa_3[ ] datab_3[ ] half-dsp block + + + result[ ] 4?26 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation high-precision multiplier adder mode in the high-precision multiplier adder configuration, shown in figure 4?18 , the dsp block can implement 2 two-multiplier adders, with multiplier precision of 18 x 36 (one two-multiplier adder per half dsp block). this mode is useful in filtering or fft applications where a data path greater than 18 bits is required, yet 18 bits is sufficient for the coefficient precision. this can occur where the data has a high dynamic range. if the coefficients are fixed, as in fft and most filter applications, the precision of 18 bits provide a dynamic range over 100 db, if the largest coefficient is normalized to the maximum 18-bit representation. in these situations, the data path can be up to 36 bits, allowing sufficient capacity for bit growth or gain changes in the signal source without loss of precision. this mode is also extremely useful in single precision block floating point applications. the high-precision multiplier adder is performed in two stages. the 18 36 multiply is divided into two 18 18 multipliers. the multiplier with the lsb of the data source is performed unsigned, while the multiplier with the msb of the data source can be signed or unsigned. the latter multiplier has its result left shifted by 18 bits prior to the first adder stage, creating an effective 18 x 36 multiplier. the results of these two adder blocks are then summed in the second stage adder block to produce the final result: z[54..0] = p 0 [53..0] + p 1 [53..0] where: p 0 = a[17..0] b[35..0] p 1 = c[17..0] d[35..0] chapter 4: dsp blocks in stratix iv devices 4?27 stratix iv operational mode descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 multiply accumulate mode in multiply accumulate mode, the second-stage adder is configured as a 44-bit accumulator or subtractor. the output of the dsp block is looped back to the second-stage adder and added or subtracted with the two outputs of the first-stage adder block according to equation 4?3 on page 4?4 . figure 4?19 shows the dsp block configured to operate in multiply accumulate mode. figure 4?18. high-precision multiplier adder configuration note to figure 4?18 : (1) block output for accumulator overflow and saturate overflow. clock[3..0] ena[3..0] aclr[3..0] signa signb o v erflo w (1) input register bank pipeline register bank output register bank dataa[0:17] p 0 p 1 dataa[0:17] datac[0:17] datac[0:17] datad[0:17] datad[18:35] datab[0:17] <<18 <<18 datab[18:35] half-dsp block + + + result[ ] 4?28 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation a single dsp block can implement up to two independent 44-bit accumulators. use the dynamic accum_sload control signal to clear the accumulation. a logic 1 value on the accum_sload signal synchronously loads the accumulator with the multiplier result only, while a logic 0 enables accumulation by adding or subtracting the output of the dsp block (accumulator feedback) to the output of the multiplier and first-stage adder. 1 cfr cr fr ccr rcr c c figure 4?19. multiply accumulate mode shown for a half dsp block note to figure 4?19 : (1) block output for saturation overflow of chainout. clock[3..0] ena[3..0] aclr[3..0] signa signb output_round output_satu rate chainout_sat_o v erflo w (1) input register bank pipeline register bank round/satu rate output register bank dataa_0[ ] datab_0[ ] dataa_1[ ] datab_1[ ] dataa_2[ ] datab_2[ ] dataa_3[ ] datab_3[ ] half-dsp block + + + result[ ] accum_sload 44 second register bank chapter 4: dsp blocks in stratix iv devices 4?29 stratix iv operational mode descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 this mode supports the rounding and saturation logic unit because it is configured as an 18-bit multiplier accumulator. you can use the pipeline registers and output registers within the dsp block to increase the performance of the dsp block. shift modes stratix iv devices support the following shift modes for 32-bit input only: asl[n] asr[32-n] lsl[n] lsr[32-n] rot[n] 1 c wc f w c r f cr c f r vc f rcr c rfr c f r r r w f cfr f f v r c r rc f f r r r r c cfr c r r rfr f r rc f r rr vcr r rc f r f f vcr c f r vcr r c f r r r f vcr r rr fr vcr r fc wr w cr rotate and shift_right , together with the signa and signb signals, determine the shifting operation. table 4?5 shows examples of shift operations. 4?30 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation figure 4?20. shift operation mode shown for a half dsp block clock[3..0] ena[3..0] aclr[3..0] signa signb rotate shift_right input register bank pipeline register bank output register bank dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] half-dsp block + + + result[ ] 32 shift/rotate tab le 4 ?5 . examples of shift operations example signa signb shift rotate a-input b-input result logical shift left lsl[n] unsigned unsigned 0 0 0xaabbccdd 0x0000100 0xbbccdd00 logical shift right lsr[32-n] unsigned unsigned 1 0 0xaabbccdd 0x0000100 0x000000aa arithmetic shift left asl[n] signed unsigned 0 0 0xaabbccdd 0x0000100 0xbbccdd00 arithmetic shift right asr[32-n] signed unsigned 1 0 0xaabbccdd 0x0000100 0xffffffaa rotation rot[n] unsigned unsigned 0 1 0xaabbccdd 0x0000100 0xbbccddaa chapter 4: dsp blocks in stratix iv devices 4?31 stratix iv operational mode descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 rounding and saturation mode rounding and saturation functions are often required in dsp arithmetic. use rounding to limit bit growth and its side effects; use saturation to reduce overflow and underflow side effects. two rounding modes are supported in stratix iv devices: 1 c f w c rr rv r r fr f r c rc rrv rv r r wr ff r ccr w w rrv wr w f ffrc w w r w ffrc w w r w r r c fw w r w r r v tab le 4 ?6 . example of round-to-nearest-even mode 6- to 4-bits rounding odd/even (integer) fractional add to integer result 010111 x > 0.5 (11) 1 0110 001101 x < 0.5 (01) 0 0011 001010 even (0010) = 0.5 (10) 0 0010 001110 odd (0011) = 0.5 (10) 1 0100 110111 x > 0.5 (11) 1 1110 101101 x < 0.5 (01) 0 1011 110110 odd (1101) = 0.5 (10) 1 1110 110010 even (1100) = 0.5 (10) 0 1100 tab le 4 ?7 . comparison of round-to-nearest-integer and round-to-nearest-even round-to-nearest-integer round-to-nearest-even 010111 ? 0110 010111 ? 0110 001101 ? 0011 001101 ? 0011 001010 ? 0011 001010 ? 0010 001110 ? 0100 001110 ? 0100 110111 ? 1110 110111 ? 1110 101101 ? 1011 101101 ? 1011 110110 ? 1110 110110 ? 1110 110010 ? 1101 110010 ? 1100 4?32 chapter 4: dsp blocks in stratix iv devices stratix iv operational mode descriptions stratix iv device handbook volume 1 ? november 2009 altera corporation two saturation modes are supported in stratix iv: 1 c f w c c fr v r c rr 1 w v r 1 1 rc r v r 1 1 r fr [43:0] ) for the rounding and saturate logic unit providing higher flexibility. these 16-bit positions are located at bits [21:6] for rounding and [43:28] for saturation, as shown in figure 4?21 . 1 c 1 cfr c 1 r rc r r wr fr r c tab le 4 ?8 . examples of saturation 44- to 36-bits saturation symmetric sat result asymmetric sat result 5926ac01342h 7ffffffffh 7ffffffffh ada38d2210h 800000001h 800000000h figure 4?21. rounding and saturation locations 43 42 29 28 1 0 43 42 21 20 7 6 0 16 user defined sat positions (bit 43-28) 16 user defined rnd positions (bit 21-6) chapter 4: dsp blocks in stratix iv devices 4?33 stratix iv operational mode descriptions ? november 2009 altera corporation stratix iv device handbook volume 1 you can use the rounding and saturation function described above in regular supported multiplication operations, as specified in table 4?2 on page 4?8 . however, for accumulation type operations, use the following convention: the functionality of the round logic unit is in the format of: result = rnd[ s (a b)], when used for an accumulation type of operation. likewise, the functionality of the saturation logic unit is in the format of: result = sat[ s (a b)], when used for an accumulation type of operation. if both the rounding and saturation logic units are used for an accumulation type of operation, the format is: result = sat[rnd[ s (a b)]] dsp block control signals the stratix iv dsp block is configured using a set of static and dynamic signals. you can configure the dsp block dynamic signals and can be set to toggle or not at run time. table 4?9 lists the dynamic signals for the dsp block. tab le 4 ?9 . dsp block dynamic signals (part 1 of 2) signal name function count signa signb signed/unsigned control for all multipliers and adders. signa for ?multiplicand? input bus to dataa[17:0] each multiplier. signb for ?multiplier? input bus datab[17:0] to each multiplier. signa = 1, signb = 1 for signed-signed multiplication signa = 1, signb = 0 for signed-unsigned multiplication signa = 0, signb = 1 for unsigned-signed multiplication signa = 0, signb = 0 for unsigned-unsigned multiplication 2 output_round round control for first stage round and saturation block. output_round = 1 for rounding on multiply output output_round = 0 for normal multiply output 1 chainout_round round control for second stage round and saturation block. chainout_round = 1 for rounding multiply output chainout_round = 0 for normal multiply output 1 output_saturate saturation control for first stage round and saturation block for q-format multiply. if both rounding and saturation is enabled, saturation is done on the rounded result. output_saturate = 1 for saturation support output_saturate = 0 for no saturation support 1 chainout_saturate saturation control for second stage round and saturation block for q-format multiply. if both rounding and saturation is enabled, saturation is done on the rounded result. chainout_saturate = 1 for saturation support chainout_saturate = 0 for no saturation support 1 4?34 chapter 4: dsp blocks in stratix iv devices software support stratix iv device handbook volume 1 ? november 2009 altera corporation software support altera provides two distinct methods for implementing various modes of the dsp block in a design: instantiation and inference. both methods use the following quartus ii megafunctions: lpm_mult altmult_add altmult_accum altfp_mult to use the dsp block, instantiate the megafunctions in the quartus ii software. alternatively, with inference, you can create an hdl design and synthesize it using a third-party synthesis tool (such as leonardospectrum ? , , , , , , f r rc fc r r rfr r fwr accum_sload dynamically specifies whether the accumulator value is zero. accum_sload = 0, accumulation input is from the output registers accum_sload = 1, accumulation input is set to zero 1 zero_chainout dynamically specifies whether the chainout value is zero. 1 zero_loopback dynamically specifies whether the loopback value is zero. 1 rotate rotate = 1, rotation feature is enabled 1 shift_right shift_right = 1, shift right feature is enabled 1 total signals per half block 11 clock0 clock1 clock2 clock3 dsp-block-wide clock signals. 4 ena0 ena1 ena2 ena3 input and pipeline register enable signals. 4 aclr0 aclr1 aclr2 aclr3 dsp block-wide asynchronous clear signals (active low). 4 total count per full block 34 tab le 4 ?9 . dsp block dynamic signals (part 2 of 2) signal name function count chapter 4: dsp blocks in stratix iv devices 4?35 document revision history ? november 2009 altera corporation stratix iv device handbook volume 1 f for more information, refer to the ?synthesis? section in volume 1 of the quartus ii development software handbook . document revision history table 4?10 shows the revision history for this chapter. table 4?10. document revision history date and document version changes made summary of changes november 2009 v3.0 updated tab le 4 ?1 . updated ?stratix iv simplified dsp operation? section. updated graphics. minor text edits. ? june 2009 v2.3 added an introductory paragraph to increase search ability. removed the conclusion section. ? april 2009 v2.2 updated table 4?1. ? march 2009 v2.1 updated table 4?1. removed ?referenced documents? section. ? november 2008 v2.0 updated table 4?2. updated figure 4?16. updated figure 4?18. ? may 2008 v1.0 initial release. ? 4?36 chapter 4: dsp blocks in stratix iv devices document revision history stratix iv device handbook volume 1 ? november 2009 altera corporation ? march 2010 altera corporation stratix iv device handbook volume 1 5. clock networks and plls in stratix iv devices this chapter describes the hierarchical clock networks and phase-locked loops (plls) which have advanced features in stratix ? iv devices. it includes details about the ability to reconfigure the pll counter clock frequency and phase shift in real time, allowing you to sweep pll output frequencies and dynamically adjust the output clock phase shift. the quartus ? ii software enables the plls and their features without external devices. the following sections describe the stratix iv clock networks and plls in detail: clock networks in stratix iv devices the global clock networks (gclks), regional clock networks (rclks), and periphery clock networks (pclks) available in stratix iv devices are organized into hierarchical clock structures that provide up to 236 unique clock domains (16 gclks + 88 rclks + 132 pclks) within the stratix iv device and allow up to 71 unique gclk, rclk, and pclk clock sources (16 gclks + 22 rclks + 33 pclks) per device quadrant. table 5?1 lists the clock resources available in stratix iv devices. tab le 5 ?1 . clock resources in stratix iv devices clock resource number of resources available source of clock resource clock input pins 32 single-ended (16 differential) clk[0..15]p and clk[0..15]n pins gclk networks 16 clk[0..15]p and clk[0..15]n pins, pll clock outputs, and logic array rclk networks 64/88 (1) clk[0..15]p and clk[0..15]n pins, pll clock outputs, and logic array pclk networks 56/88/112/132 (33 per device quadrant) (2) dpa clock outputs, pld-transceiver interface clocks, horizontal i/o pins, and logic array gclks/rclks per quadrant 32/38 (3) 16 gclks + 16 rclks 16 gclks + 22 rclks gclks/rclks per device 80/104 (4) 16 gclks + 64 rclks 16 gclks + 88 rclks notes to ta bl e 5? 1 : (1) there are 64 rclks in the ep4s40g2, ep4s100g2, ep4se230, ep 4sgx70, ep4sgx110, ep4sgx180, and ep 4sgx230 devices. there are 88 rclks in the ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se360, ep4se530, ep4se820, ep4sgx290, ep4sgx360, and ep4sgx530 devices. (2) there are 56 pclks in the ep4sgx70, and ep4sgx110 devices. there are 88 pclks in the ep4s40g2, ep4s100g2, ep4se230, ep4se360, ep4sgx180, ep4sgx230, ep4sgx290, and ep4sgx360 devices. there are 112 pclks in the ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se530 and ep4sgx530 devices. there are 132 pclks in the ep4se820 device. (3) there are 32 gclks/rclks per quadrant in the ep4s40g2, ep4s100g2, ep4se230, ep4sgx70, ep4sgx110, ep4sgx180, and ep4sgx230 de vices. there are 38 gclks/rclks per quadrant in the ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se360, ep4se530, ep4se820, ep4sgx290, ep4sgx360, and ep4sgx530 devices. (4) there are 80 gclks/rclks per entire device in the ep4s40g2, ep4s100g2, ep4se230, ep4sgx70, ep4sgx110, ep4sgx180, and ep4sgx230 devices. there are 104 gclks/rclks per entire device in the ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se360, ep4se530, ep4s e820, ep4sgx290, ep4sgx360, a nd ep4sgx530 devices. siv51005-3.1 5?2 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation stratix iv devices have up to 32 dedicated single-ended clock pins or 16 dedicated differential clock pins ( clk[0..15]p and clk[0..15]n ) that can drive either the gclk or rclk networks. these clock pins are arranged on the four sides of the stratix iv device, as shown in figure 5?1 through figure 5?4 on page 5?4 . f r r fr w cc cc rfr stratix iv device family pin connection guidelines . global clock networks stratix iv devices provide up to 16 gclks that can drive throughout the device, serving as low-skew clock sources for functional blocks such as adaptive logic modules (alms), digital signal processing (dsp) blocks, trimatrix memory blocks, and plls. stratix iv device i/o elements (ioes) and internal logic can also drive gclks to create internally generated global clocks and other high fan-out control signals; for example, synchronous or asynchronous clears and clock enables. figure 5?1 shows the clk pins and plls that can drive the gclk networks in stratix iv devices. figure 5?1. gclk networks t1 t2 l1 l2 l3 l4 b1 b2 r1 r2 r3 r4 gclk[0..3] gclk[4..7] gclk[8..11] gclk[12..15] clk[12..15] clk[4..7] clk[0..3] clk[8..11] chapter 5: clock networks and plls in stratix iv devices 5?3 clock networks in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 regional clock networks rclk networks only pertain to the quadrant they drive into. rclk networks provide the lowest clock delay and skew for logic contained within a single device quadrant. the stratix iv device ioes and internal logic within a given quadrant can also drive rclks to create internally generated regional clocks and other high fan-out control signals; for example, synchronous or asynchronous clears and clock enables. figure 5?2 through figure 5?4 on page 5?4 show the clk pins and plls that can drive the rclk networks in stratix iv devices. figure 5?2. rclk networks (ep4se230, ep4sgx70, and ep4sgx110 devices) (note 1) note to figure 5?2 : (1) a maximum of four signals from the core can drive into each group of rclks. for example, only four core signals can drive in to rclk[0..5] and another four core signals can drive into rclk[54..63] at any one time. t1 b1 rclk[0..5] rclk[38..43] rclk[6..11] rclk[32..37] rclk[54..63] rclk[44..53] rclk[12..21] rclk[22..31] clk[12..15] clk[4..7] clk[0..3] clk[8..11] q1 q2 q4 q3 l2 r2 5?4 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation figure 5?3. rclk networks (ep4s40g2, ep4s100g2, ep4sgx180, and ep4sgx230 devices) (note 1) note to figure 5?3 : (1) a maximum of four signals from the core can drive into each group of rclks. for example, only four core signals can drive in to rclk[0..5] and another four core signals can drive into rclk[54..63] at any one time. figure 5?4. rclk networks (ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se360, ep4se530, ep4se820, ep4sgx290, ep4sgx360, and ep4sgx530 devices) (note 1) , (2) , (3) notes to figure 5?4 : (1) the corner rclk[64..87] can only be fed by their respective corner pll outputs. for more details about connectivity, refer to table 5?6 on page 5?13 . (2) ep4s40g5 and ep4se360 devices have up to 8 plls. for more details about pll availability, refer to table 5?7 on page 5?19 . (3) a maximum of four signals from the core can drive into each group of rclks. for example, only four core signals can drive in to rclk[0..5] and another four core signals can drive into rclk[54..63] at any one time. rclk[0..5] rclk[38..43] rclk[6..11] rclk[32..37] rclk[54..63] rclk[44..53] rclk[12..21] rclk[22..31] clk[12..15] clk[4..7] clk[0..3] clk[8..11] q1 q2 q4 q3 r3 r2 t2 t1 b2b1 l3 l2 rclk[0..5] rclk[38..43] rclk[6..11] rclk[32..37] rclk[64..69] rclk[70..75] rclk[82..87] rclk[76..81] rclk[54..63] rclk[44..53] rclk[12..21] rclk[22..31] clk[12..15] clk[4..7] clk[0..3] clk[8..11] q1 q2 q4 q3 l3 r3 l2 r2 l4 r4 l1 r1 t2t1 b2b1 chapter 5: clock networks and plls in stratix iv devices 5?5 clock networks in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 periphery clock networks pclk networks shown in figure 5?5 to figure 5?8 on page 5?7 are collections of individual clock networks driven from the periphery of the stratix iv device. clock outputs from the dynamic phase aligner (dpa) block, programmable logic device (pld)-transceiver interface clocks, horizontal i/o pins, and internal logic can drive the pclk networks. pclks have higher skew when compared with gclk and rclk networks. you can use pclks for general purpose routing to drive signals into and out of the stratix iv device. legal clock sources for pclk networks are clock outputs from the dpa block, pld-transceiver interface clocks, horizontal i/o pins, and internal logic. figure 5?5. pclk networks (ep4sgx70 and ep4sgx110 devices) t1 b1 clk[12..15] clk[4..7] clk[0..3] clk[8..11] q1 q2 q4 q3 l2 r2 pclk[0..13] pclk[42..56] pclk[14..27] pclk[28..41] 5?6 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation figure 5?6. pclk networks (ep4s40g2, ep4s100g2, ep4se230, ep4se360, ep4sgx180, ep4sgx230, ep4sgx290, and ep4sgx360 devices) (note 1) note to figure 5?6 : (1) ep4se230 device has 4 plls. ep4sgx290 and ep4sgx360 devices have up to 12 plls. for more details about pll availability, ref er to table 5?7 on page 5?19 . figure 5?7. pclk networks (ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, ep4se530, and ep4sgx530 devices) (note 1) note to figure 5?7 : (1) ep4s40g5 device has 8 plls. for more details about pll availability, refer to table 5?7 on page 5?19 . t2 b2 t1 b1 pclk[77..87] clk[12..15] clk[4..7] clk[0..3] clk[8..11] q1 q2 q4 q3 l3 r3 l2 r2 pclk[0..10] pclk[11..21] pclk[66..76] pclk[22..32] pclk[55..65] pclk[33..43] pclk[44..54] q1 q2 q4 q3 pclk[0..13] pclk[98..111] pclk[84..97] pclk[14..27] pclk[28..41] pclk[42..55] pclk[70..83] pclk[56..69] t2 b2 t1 b1 clk[12..15] clk[4..7] clk[0..3] clk[8..11] l3 r3 l2 r2 l4 r4 l1 r1 chapter 5: clock networks and plls in stratix iv devices 5?7 clock networks in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 figure 5?8. pclk networks (ep4se820 device) q1 q2 q4 q3 pclk[0..15] pclk[16..32] pclk[116..131] pclk[99..115] pclk[82..98] pclk[33..49] pclk[50..65] pclk[66..81] t2 b2 t1 b1 clk[12..15] clk[4..7] clk[0..3] clk[8..11] l3 r3 l2 r2 l4 r4 l1 r1 5?8 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation clock sources per quadrant there are 26 section clock (sclk) networks available in each spine clock that can drive 6 row clocks in each logic array block (lab) row, 9 column i/o clocks, and 3 core reference clocks. the sclks are the clock resources to the core functional blocks, plls, and i/o interfaces of the device. figure 5?9 shows that the sclks can be driven by the gclk, rclk, pclk, or the pll feedback clock networks in each spine clock. 1 cc r r f r w fr c cc cc cc r fr c rw fr cc r rr r r fwr c r cc figure 5?9. hierarchical clock networks per spine clock (note 1) notes to figure 5?9 : (1) the gclk, rclk, pclk, and pll feedback clocks share the same routing to the sclks. the total number of clock resources must not exceed the sclk limits in each region to ensure successful design fitting in the quartus ii software. (2) there are up to 16 pclks that can drive the sclks in each spine clock in the largest device. (3) there are up to 22 rclks that can drive the sclks in each spine clock in the largest device. (4) the pll feedback clock is the clock from the pll that drives into the sclks. (5) the column i/o clock is the clock that drives the column i/o core registers and i/o interfaces. (6) the core reference clock is the clock that feeds into the pll as the pll reference clock. (7) the row clock is the clock source to the lab, memory blocks, and row i/o interfaces in the core row. sclk column i/o clock (5) core reference clock (6 ) row clock (7) gclk rclk pll feedback clock (4) pclk 9 3 26 16 3 16 (2) 22 (3) 6 chapter 5: clock networks and plls in stratix iv devices 5?9 clock networks in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 clock regions stratix iv devices provide up to 104 distinct clock domains (16 gclks + 88 rclks) in the entire device. you can use these clock resources to form the following types of clock regions: figure 5?10. stratix iv dual-regional clock region clock pins or pll outputs can drive half of the device to create side-wide clocking regions for improved interface timing. 5?10 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation clock network sources in stratix iv devices, clock input pins, pll outputs, and internal logic can drive the gclk and rclk networks. for the connectivity between dedicated pins clk[0..15] and the gclk and rclk networks, refer to table 5?2 and table 5?3 on page 5?11 . dedicated clock input pins clk pins can be either differential clocks or single-ended clocks. stratix iv devices support 16 differential clock inputs or 32 single-ended clock inputs. you can also use dedicated clock input pins clk[15..0] for high fan-out control signals such as asynchronous clears, presets, and clock enables for protocol signals such as trdy and irdy for pci through gclk or rclk networks. labs you can drive each gclk and rclk network using lab-routing to enable internal logic to drive a high fan-out, low-skew signal. 1 r c rv r r r cc c fr c cc r f r pll clock outputs stratix iv plls can drive both gclk and rclk networks, as described in table 5?5 on page 5?12 and table 5?6 on page 5?13 . table 5?2 lists the connection between the dedicated clock input pins and gclks. tab le 5 ?2 . clock input pin connectivity to the gclk networks (part 1 of 2) clock resources clk (p/n pins) 0123456789101112131415 gclk0 v v v v ???????????? gclk1 v v v v ???????????? gclk2 v v v v ???????????? gclk3 v v v v ???????????? gclk4 ???? v v v v ???????? gclk5 ???? v v v v ???????? gclk6 ???? v v v v ???????? gclk7 ???? v v v v ???????? gclk8 ???????? v v v v ???? gclk9 ???????? v v v v ???? gclk10 ???????? v v v v ???? gclk11 ???????? v v v v ???? gclk12 ???????????? v v v v gclk13 ???????????? v v v v chapter 5: clock networks and plls in stratix iv devices 5?11 clock networks in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 table 5?3 lists the connectivity between the dedicated clock input pins and rclks in stratix iv devices. a given clock input pin can drive two adjacent rclk networks to create a dual-regional clock network. gclk14 ???????????? v v v v gclk15 ???????????? v v v v tab le 5 ?2 . clock input pin connectivity to the gclk networks (part 2 of 2) clock resources clk (p/n pins) 0123456789101112131415 tab le 5 ?3 . clock input pin connectivity to the rclk networks clock resource clk (p/n pins) 0123456789101112131415 rclk [0, 4, 6, 10] v ??????????????? rclk [1, 5, 7, 11] ? v ?????????????? rclk [2, 8] ?? v ????????????? rclk [3, 9] ??? v ???????????? rclk [13, 17, 21, 23, 27, 31] ? ?? ? v ??????????? rclk [12, 16, 20, 22, 26, 30] ????? v ?????????? rclk [15, 19, 25, 29] ? ????? v ????????? rclk [14, 18, 24, 28] ? ?????? v ???????? rclk [35, 41] ? ??????? v ??????? rclk [34, 40] ? ???????? v ?????? rclk [33, 37, 39, 43] ? ????????? v ????? rclk [32, 36, 38, 42] ? ?????????? v ???? rclk [47, 51, 57, 61] ? ??????????? v ??? rclk [46, 50, 56, 60] ? ???????????? v ? ? rclk [45, 49, 53, 55, 59, 63] ? ????????????? v ? rclk [44, 48, 52, 54, 58, 62] ? ?????????????? v 5?12 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation clock input connections to the plls table 5?4 lists the dedicated clock input pin connectivity to stratix iv plls. clock output connections plls in stratix iv devices can drive up to 20 rclk networks and four gclk networks. for stratix iv pll connectivity to gclk networks, refer to table 5?5 . the quartus ii software automatically assigns pll clock outputs to rclk and gclk networks. table 5?5 lists how the pll clock outputs connect to the gclk networks. tab le 5 ?4 . stratix iv device plls and pll clock pin drivers (note 1) , (2) dedicated clock input pin clk (p/n pins) pll number l1 l2 l3 l4 b1 b2 r1 r2 r3 r4 t1 t2 clk0 v v v v ????? ??? clk1 v v v v ????? ??? clk2 v v v v ????? ??? clk3 v v v v ????? ??? clk4 ???? v v ??? ??? clk5 ???? v v ??? ??? clk6 ???? vv ??? ??? clk7 ???? vv ??? ??? clk8 ?????? v v v v ?? clk9 ?????? v v v v ?? clk10 ?????? v v v v ?? clk11 ?????? v v v v ?? clk12 ????????? ? vv clk13 ????????? ? vv clk14 ????????? ? vv clk15 ????????? ? vv note to tab l e 5 ?4 : (1) for single-ended clock inputs, only the clk<#>p pin has a dedicated connection to the pll. if you use the clk<#>n pin, a global clock is used. (2) for the availability of the clock input pins in each device density, refer to the ?stratix iv device pin-out files? section of the pin-out files for altera devices site. tab le 5 ?5 . stratix iv pll connectivity to the gclk networks (note 1) (part 1 of 2) clock network pll number l1 l2 l3 l4 b1 b2 r1 r2 r3 r4 t1 t2 gclk0 vv v v ???????? gclk1 v v v v ???????? gclk2 v v v v ???????? gclk3 v v v v ???????? chapter 5: clock networks and plls in stratix iv devices 5?13 clock networks in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 table 5?6 lists how the pll clock outputs connect to the rclk networks. clock control block every gclk and rclk network has its own clock control block. the control block provides the following features: gclk4 ???? vv ?????? gclk5 ???? vv ?????? gclk6 ???? vv ?????? gclk7 ???? vv ?????? gclk8 ?????? vvvv ?? gclk9 ?????? vvvv ?? gclk10 ?????? vvvv ?? gclk11 ?????? vvvv ?? gclk12 ?????????? vv gclk13 ?????????? v v gclk14 ?????????? v v gclk15 ?????????? v v note to tab l e 5 ?5 : (1) only pll counter outputs c0 - c3 can drive the gclk networks. tab le 5 ?6 . stratix iv rclk outputs from the pll clock outputs (note 1) clock resource pll number l1 l2 l3 l4 b1 b2 r1 r2 r3 r4 t1 t2 rclk[0..11] ? vv ????????? rclk[12..31] ???? vv ? ? ??? ? rclk[32..43] ??????? vv ?? ? rclk[44..63] ?????????? vv rclk[64..69] ??? v ???????? rclk[70..75] ????????? v ?? rclk[76..81] ?????? v ? ??? ? rclk[82..87] v ??????????? note to tab l e 5 ?6 : (1) all pll counter outputs can drive the rclk networks. tab le 5 ?5 . stratix iv pll connectivity to the gclk networks (note 1) (part 2 of 2) clock network pll number l1 l2 l3 l4 b1 b2 r1 r2 r3 r4 t1 t2 5?14 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation figure 5?11 and figure 5?12 show the gclk and rclk select blocks, respectively. you can select the clock source for the gclk select block either statically or dynamically. you can statically select the clock source using a setting in the quartus ii software or you can dynamically select the clock source using internal logic to drive the multiplexer-select inputs. when selecting the clock source dynamically, you can select either pll outputs (such as c0 or c1 ) or a combination of clock pins or pll outputs. the mapping between the input clock pins, pll counter outputs, and clock control block inputs is as follows: inclk[0] and inclk[1] ?can be fed by any of the four dedicated clock pins on the same side of the stratix iv device inclk[2] ?can be fed by pll counters c0 and c2 from the two center plls on the same side of the stratix iv device inclk[3] ?can be fed by pll counters c1 and c3 from the two center plls on the same side of the stratix iv device the corner plls (l1, l4, r1, and r4) and the corresponding clock input pins ( pll_l1_clk and so forth) do not support dynamic selection for the gclk network. the clock source selection for the gclk and rclk networks from the corner plls (l1, l4, r1, and r4) and the corresponding clock input pins ( pll_l1_clk and so forth) is controlled statically using configuration bit settings in the configuration file ( .sof or .pof ) generated by the quartus ii software. figure 5?11. stratix iv gclk control block notes to figure 5?11 : (1) when the device is operating in user mode, you can dynamically control the clock select signals through internal logic. (2) when the device is operation in user mode, you can only set the clock select signals through a configuration file (sram object file [ .sof] or programmer object file [ .pof] ) and cannot be dynamically controlled. clkp pins pll counter outputs internal logic static cloc k select (2) clkselect[1..0] this multiplexer supports user -controllable dynamic switching (1) 2 2 2 clkn pin enab le/ disab le gclk internal logic chapter 5: clock networks and plls in stratix iv devices 5?15 clock networks in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 you can only control the clock source selection for the rclk select block statically using configuration bit settings in the configuration file ( .sof or .pof ) generated by the quartus ii software. you can power down the stratix iv clock networks using both static and dynamic approaches. when a clock network is powered down, all the logic fed by the clock network is in off-state, thereby reducing the overall power consumption of the device. the unused gclk and rclk networks are automatically powered down through configuration bit settings in the configuration file ( .sof or .pof ) generated by the quartus ii software. the dynamic clock enable or disable feature allows the internal logic to control power-up or power-down synchronously on the gclk and rclk networks, including dual-regional clock regions. this function is independent of the pll and is applied directly on the clock network, as shown in figure 5?11 and figure 5?12 . you can set the input clock sources and the clkena signals for the gclk and rclk network multiplexers through the quartus ii software using the altclkctrl megafunction. you can also enable or disable the dedicated external clock output pins using the altclkctrl megafunction. figure 5?13 shows the external pll output clock control block. 1 fc c cc rc c fr cc f inclk[0..1] ports of the multiplexer, while the pll outputs feed the inclk[2..3] ports. you can choose from among these inputs using the clkselect[1..0] signal. f r r fr rfr clock control block (altclkctrl) megafunction user guide . figure 5?12. rclk control block notes to figure 5?12 : (1) when the device is operation in user mode, you can only set the clock select signals through a configuration file ( .sof or .pof ) and cannot be dynamically controlled. (2) the clkn pin is not a dedicated clock input when used as a single-ended pll clock input. clkp pin pll counter outputs internal logic clkn pin enab le/ disab le rclk internal logic static clock select (1 ) 2 (2) 5?16 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation clock enable signals figure 5?14 shows how the clock enable and disable circuit of the clock control block is implemented in stratix iv devices. figure 5?13. stratix iv external pll output clock control block notes to figure 5?13 : (1) when the device is operation in user mode, you can only set the clock select signals through a configuration file ( .sof or .pof ) and cannot be dynamically controlled. (2) the clock control block feeds to a multiplexer within the pll_<#>_clkout pin?s ioe. the pll_ <#> _clkout pin is a dual-purpose pin. therefore, this multiplexer selects either an internal signal or the output of the clock control block. pll counter outputs enab le/ disab le pll_<#>_clkout pin internal logic static clock select ioe (1) static clock select (1) internal logic (2) 7 or 10 figure 5?14. clkena implementation notes to figure 5?14 : (1) the r1 and r2 bypass paths are not available for the pll external clock outputs. (2) the select line is statically controlled by a bit setting in the configuration file ( .sof or .pof ). clkena gclk/ rclk/ pll_<#>_clkout (1) outpu t of clock select m ux (2) r1 r2 (1) (1) d q d q chapter 5: clock networks and plls in stratix iv devices 5?17 clock networks in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 in stratix iv devices, the clkena signals are supported at the clock network level instead of at the pll output counter level. this allows you to gate off the clock even when you are not using a pll. you can also use the clkena signals to control the dedicated external clocks from the plls. figure 5?15 shows a waveform example for a clock output enable. clkena is synchronous to the falling edge of the clock output. stratix iv devices also have an additional metastability register that aids in asynchronous enable and disable of the gclk and rclk networks. you can optionally bypass this register in the quartus ii software. the pll can remain locked independent of the clkena signals because the loop-related counters are not affected. this feature is useful for applications that require a low-power or sleep mode. the clkena signal can also disable clock outputs if the system is not tolerant of frequency over-shoot during resynchronization. clock source control for plls the clock input to stratix iv plls comes from clock input multiplexers. the clock multiplexer inputs come from dedicated clock input pins, plls through the gclk and rclk networks, or from dedicated connections between adjacent top/bottom and left/right plls. the clock input sources to top/bottom and left/right plls (l2, l3, t1, t2, b1, b2, r2, and r3) are shown in figure 5?16 ; the corresponding clock input sources to left and right plls (l1, l4, r1, and r4) are shown in figure 5?17 . the multiplexer select lines are only set in the configuration file ( .sof or .pof ). after programmed, this block cannot be changed without loading a new configuration file ( .sof or .pof ). the quartus ii software automatically sets the multiplexer select signals depending on the clock sources selected in the design. figure 5?15. clkena signals (note 1) note to figure 5?15 : (1) you can use the clkena signals to enable or disable the gclk and rclk networks or the pll_ <#> _clkout pins. clkena output of and gate with r2 bypassed output of clock select mux output of and gate with r2 not bypassed 5?18 chapter 5: clock networks and plls in stratix iv devices clock networks in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation cascading plls you can cascade the left/right and top/bottom plls through the gclk and rclk networks. in addition, where two left/right or top/bottom plls exist next to each other, there is a direct connection between them that does not require the gclk or rclk network. using this path reduces clock jitter when cascading plls. 1 r vc w cc f r rcvr rcvr f r r fr rfr rc rcvr c c stratix iv transceiver clocking chapter. when cascading plls in stratix iv devices, the source (upstream) pll must have a low-bandwidth setting while the destination (downstream) pll must have a high-bandwidth setting. ensure that there is no overlap of the bandwidth ranges of the two plls. figure 5?16. clock input multiplexer logic for l2, l3, t1, t2, b1, b2, r2, and r3 plls notes to figure 5?16 : (1) when the device is operating in user mode, input clock multiplexing is controlled through a configuration file ( .sof or .pof ) only and cannot be dynamically controlled. (2) n=0 for l2 and l3 plls; n=4 for b1 and b2 plls; n=8 for r2 and r3 plls, and n=12 for t1 and t2 plls. (3) you can drive the gclk or rclk input using an output from another pll, a pin-driven gclk or rclk, or through a clock control block provided the clock control block is fed by an output from another pll or a pin-driven dedicated gclk or rclk. an internally generated global signal or general purpose i/o pin cannot drive the pll. figure 5?17. clock input multiplexer logic for l1, l4, r1, and r4 plls notes to figure 5?17 : (1) dedicated clock input pins to the plls are l1, l4, r1, and r4, respectively. for example, pll_l1_clk is the dedicated clock input for pll_l1. (2) you can drive the gclk or rclk input using an output from another pll, a pin-driven gclk or rclk, or through a clock control block provided the clock control block is fed by an output from another pll or a pin-driven dedicated gclk or rclk. an internally generated global signal or general purpose i/o pin cannot drive the pll. (3) the center clock pins can feed the corner plls on the same side directly through a dedicated path. however, these paths may not be fully compensated. 4 4 (1) (1) inclk0 inclk1 to the clock switchover bloc k clk[n+3..n] (2) gclk / rclk input (3) adjacent pll output inclk0 inclk1 clk[0..3] or clk[8..11] (3) gclk/rclk (2) pll_ chapter 5: clock networks and plls in stratix iv devices 5?19 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 1 for more information about pll cascading in external memory interfaces designs, refer to the external memory phy interface (altmemphy) (nonafi) megafunction user guide . plls in stratix iv devices stratix iv devices offer up to 12 plls that provide robust clock management and synthesis for device clock management, external system clock management, and high-speed i/o interfaces. the nomenclature for the plls follows their geographical location in the device floor plan. the plls that reside on the top and bottom sides of the device are named pll_t1, pll_t2, pll_b1 and pll_b2; the plls that reside on the left and right sides of the device are named pll_l1, pll_l2, pll_l3, pll_l4, pll_r1, pll_r2, pll_r3 , and pll_r4. table 5?7 lists the number of plls available in the stratix iv device family. tab le 5 ?7 . stratix iv device pll availability (part 1 of 2) device package l1 l2 l3 l4 t1 t2 b1 b2 r1 r2 r3 r4 ep4s40g2 f1517 ? vv? vvvv ? vv ? ep4s40g5 h1517 ? vv? vvvv ? vv ? ep4s100g2 f1517 ? vv? vvvv ? vv ? ep4s100g3 f1932 vvvvvvvvvvvv ep4s100g4 f1932 vvvvvvvvvvvv ep4s100g5 h1517 ? vv? vvvv ? vv ? f1932 vvvvvvvvvvvv ep4se230 f780 ? v ?? v ? v ??v ?? ep4se360 h780 ? v ?? v ? v ??v ?? f1152 ? vv? vvvv ? vv ? ep4se530 h1152 ? vv? vvvv ? vv ? h1517 vvvvvvvvvvvv f1760 vvvvvvvvvvvv ep4se820 h1152 ? vv? vvvv ? vv ? h1517 vvvvvvvvvvvv f1760 vvvvvvvvvvvv ep4sgx70 f780 ? v ?? v ? v ????? f1152 ? v ?? v ? v ?? v ?? ep 4s gx110 f780 ? v ?? v ? v ????? f1152 ? v ?? v ? v ??v ?? ep4sgx180 f780 ? v ?? v ? v ????? f1152 ? v ?? vvvv ? v ?? f1517 ? vv? vvvv ? vv ? ep4sgx230 f780 ? v ?? v ? v ????? f1152 ? v ?? vvvv ? v ?? f1517 ? vv? vvvv ? vv ? 5?20 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation all stratix iv plls have the same core analog structure with only minor differences in the features that are supported. table 5?8 lists the features of top/bottom and left/right plls in stratix iv devices. ep4sgx290 h780 ? ? ? ? vvvv ???? f1152 ? v ?? vvvv ? v ?? f1517 ? vv? vvvv ? vv ? f1760 vvvvvvvvvvvv f1932 vvvvvvvvvvvv ep4sgx360 h780 ? ? ? ? vvvv ???? f1152 ? v ?? vvvv ? v ?? f1517 ? vv? vvvv ? vv ? f1760 vvvvvvvvvvvv f1932 vvvvvvvvvvvv ep4sgx530 h1152 ? v ?? vvvv ? v ?? h1517 ? vv? vvvv ? vv ? f1760 vvvvvvvvvvvv f1932 vvvvvvvvvvvv tab le 5 ?7 . stratix iv device pll availability (part 2 of 2) device package l1 l2 l3 l4 t1 t2 b1 b2 r1 r2 r3 r4 tab le 5 ?8 . stratix iv pll features (part 1 of 2) feature stratix iv top/bottom plls stratix iv left/right plls c (output) counters 10 7 m , n , c counter sizes 1 to 512 1 to 512 dedicated clock outputs 6 single-ended or 4 single-ended and 1 differential pair 2 single-ended or 1 differential pair clock input pins 4 single-ended or 2 differential pin pairs 4 single-ended or 2 differential pin pairs external feedback input pin single-ended or differential single-ended only spread-spectrum input clock tracking yes (1) yes (1) pll cascading through gclk and rclk and a dedicated path between adjacent plls through gclk and rclk and dedicated path between adjacent plls (2) compensation modes all except lvds clock network compensation all except external feedback mode when using differential i/os pll drives lvdsclk and loaden no yes vco output drives the dpa clock no yes phase shift resolution down to 96.125 ps (3) down to 96.125 ps (3) programmable duty cycle yes yes output counter cascading yes yes chapter 5: clock networks and plls in stratix iv devices 5?21 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 figure 5?18 shows the location of plls in stratix iv devices. stratix iv pll hardware overview stratix iv devices contain up to 12 plls with advanced clock management features. the goal of a pll is to synchronize the phase and frequency of an internal or external clock to an input reference clock. there are a number of components that comprise a pll to achieve this phase alignment. stratix iv plls align the rising edge of the input reference clock to a feedback clock using the phase-frequency detector (pfd). the falling edges are determined by the duty-cycle specifications. the pfd produces an up or down signal that determines whether the vco must operate at a higher or lower frequency. the output of the pfd feeds the charge pump and loop filter, which produces a control voltage for setting the input clock switchover yes yes notes to ta bl e 5? 8 : (1) provided input clock jitter is within input jitter tolerance specifications. (2) the dedicated path between adjacent plls is not available on l1, l4, r1, and r4 plls. (3) the smallest phase shift is determined by the voltage-controlled oscillator (vco) period divided by eight. for degree increm ents, the stratix iv device can shift all output frequencies in increments of at least 45 . smaller degree increments are possible depending on the frequency and divide parameters. tab le 5 ?8 . stratix iv pll features (part 2 of 2) feature stratix iv top/bottom plls stratix iv left/right plls figure 5?18. stratix iv pll locations pll_r1_clk pll-r4_clk clk[8..11] pll_l4_clk clk[0..3] l1 l2 l3 l4 r1 r2 r3 r4 t2 b1 b2 clk[4..7] clk[12..15] t1 q1 q4 q2 q3 left/right plls left/right plls left/right plls left/right plls top/bottom plls pll_l1_clk top/bottom plls top/bottom plls top/bottom plls 5?22 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation vco frequency. if the pfd produces an up signal, the vco frequency increases. a down signal decreases the vco frequency. the pfd outputs these up and down signals to a charge pump. if the charge pump receives an up signal, current is driven into the loop filter. conversely, if the charge pump receives a down signal, current is drawn from the loop filter. the loop filter converts these up and down signals to a voltage that is used to bias the vco. the loop filter also removes glitches from the charge pump and prevents voltage over-shoot, which filters the jitter on the vco. the voltage from the loop filter determines how fast the vco operates. a divide counter ( m ) is inserted in the feedback loop to increase the vco frequency above the input reference frequency. vco frequency (f vco ) is equal to ( m ) times the input reference clock (f ref ). the input reference clock (f ref ) to the pfd is equal to the input clock (f in ) divided by the pre-scale counter ( n ). therefore, the feedback clock (f fb ) applied to one input of the pfd is locked to the f ref that is applied to the other input of the pfd. the vco output from the left and right plls can feed seven post-scale counters ( c[0..6] ), while the corresponding vco output from the top and bottom plls can feed ten post-scale counters ( c[0..9] ). these post-scale counters allow a number of harmonically related frequencies to be produced by the pll. figure 5?19 shows a simplified block diagram of the major components of the stratix iv pll. 1 c rv r fr r rv r r r cc cr c rv cc cr c f fr r r rv c r r r r r r c rv figure 5?19. stratix iv pll block diagram notes to figure 5?19 : (1) the number of post-scale counters is seven for left and right plls and ten for top and bottom plls. (2) this is the vco post-scale counter k . (3) the fbout port is fed by the m counter in stratix iv plls. clock switchover block inclk0 inclk1 dedicated clock inputs cascade input from adjacent pll pfdena clkswitch clkbad0 clkbad1 activeclock pfd lock circuit locked n cp lf vco 2 (2) gclk/rclk 8 4 fbin diffioclk network gclk/rclk network no compensation mode zdb, external feedback modes lvds compensation mode source synchronous, normal modes c0 c1 c2 c3 cn m (1) pll output mux casade output to adjacent pll gclks rclks external clock outputs diffioclk from left/right plls load_en from left/right plls fbout (3) external memory interface dll 8 8 to dpa block on left/right plls /2, /4 chapter 5: clock networks and plls in stratix iv devices 5?23 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 pll clock i/o pins each top and bottom pll supports six clock i/o pins, organized as three pairs of pins: c[9..0] on the top and bottom plls and c[6..0] on the left and right plls) or the m counter can feed the dedicated external clock outputs, as shown in figure 5?20 and figure 5?21 . therefore, one counter or frequency can drive all output pins available from a given pll. each left and right pll supports two clock i/o pins, configured as either two single-ended i/os or one differential i/o pair. when using both pins as single-ended i/os, one of them can be the clock output while the other pin is the external feedback input (fb) pin. therefore, for single-ended i/o standards, the left and right plls only support external feedback mode. figure 5?20. external clock outputs for top and bottom plls notes to figure 5?20 : (1) you can feed these clock output pins using any one of the c[9..0] , m counters . (2) the clkout0p and clkout0n pins can be either single-ended or differential clock outputs. the clkout1 and clkout2 pins are dual-purpose i/o pins that you can use as two single-ended out puts or one differential external feedback input pin. the clkout3 and clkout4 pins are two single-ended output pins. (3) these external clock enable signals are available only when using the altclkctrl megafunction. top/bottom plls c2 c3 c4 c6 c7 c5 pll_<#>_clkout3 (1), (2) c8 c0 c1 c9 internal logic pll_<#>_clkout4 (1), (2) pll_<#>_fbn/clkout2 (1), (2) pll_<#>_fbp/clkout1 (1), (2) pll_<#>_clkout0n (1), (2) pll_<#>_clkout0p (1), (2) clkena0 (3) clkena1 (3) clkena3 (3) clkena2 (3) clkena4 (3) clkena5 (3) m(fbout) 5?24 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation each pin of a single-ended output pair can either be in-phase or 180 out-of-phase. the quartus ii software places the not gate in the design into the ioe to implement the 180 phase with respect to the other pin in the pair. the clock output pin pairs support the same i/o standards as standard output pins (in the top and bottom banks) as well as lvds, lvpecl, differential high-speed transceiver logic (hstl), and differential sstl. f r wc r r r cc rfr i/o features in stratix iv devices chapter. stratix iv plls can also drive out to any regular i/o pin through the gclk or rclk network. you can also use the external clock output pins as user i/o pins if you do not need external pll clocking. figure 5?21. external clock outputs for left and right plls notes to figure 5?21 : (1) you can feed these clock output pins using any one of the c[6..0], m counters. (2) the clkout0p and clkout0n pins are dual-purpose i/o pins that you can use as two single-ended outputs or one single-ended output and one external feedback input pin. (3) these external clock enable signals are available only when using the altclkctrl megafunction. left/right plls c2 c3 c4 c6 c5 clkena0 (3) c0 c1 internal logic pll_ chapter 5: clock networks and plls in stratix iv devices 5?25 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 pll control signals you can use the pfdena , areset , and locked signals to observe and control pll operation and resynchronization. pfdena use the pfdena signal to maintain the most recent locked frequency so your system has time to store its current settings before shutting down. the pfdena signal controls the pfd output with a programmable gate. if you disable pfd, the vco operates at its most recent set value of control voltage and frequency, with some long-term drift to a lower frequency. the pll continues running even if it goes out-of-lock or the input clock is disabled. you can use either your own control signal or the control signals available from the clock switchover circuit ( activeclock, clkbad[0] , or clkbad[1] ) to control pfdena. areset the areset signal is the reset or resynchronization input for each pll. the device input pins or internal logic can drive these input signals. when areset is driven high, the pll counters reset, clearing the pll output and placing the pll out-of-lock. the vco is then set back to its nominal setting. when areset is driven low again, the pll resynchronizes to its input as it re-locks. you must assert the areset signal every time the pll loses lock to guarantee the correct phase relationship between the pll input and output clocks. you can set up the pll to automatically reset (self reset) upon a loss-of-lock condition using the quartus ii megawizard ? areset signal in designs if either of the following conditions is true: 1 f cc r fr wr r areset signal after the input clock is stable and within specifications. locked the locked signal output of the pll indicates that the pll has locked onto the reference clock and the pll clock outputs are operating at the desired phase and frequency set in the quartus ii megawizard plug-in manager. the lock detection circuit provides a signal to the core logic that gives an indication when the feedback clock has locked onto the reference clock both in phase and frequency. 1 r rc areset and locked signals in your designs to control and observe the status of your pll. 5?26 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation clock feedback modes stratix iv plls support up to six different clock feedback modes. each mode allows clock multiplication and division, phase shifting, and programmable duty cycle. table 5?9 lists the clock feedback modes supported by the stratix iv device plls. 1 r f c w c cc c w v cc rc r w pll_t1 in normal mode, the clock delays from the input pin to the pll clock output-to-destination register are fully compensated, provided the clock input pin is one of the following four pins: clk12, clk13, clk14 , or clk15. when an rclk or gclk network drives the pll, the input and output delays may not be fully compensated in the quartus ii software. another example is when you configure pll_t2 in zero-delay buffer mode and the pll input is driven by a dedicated clock input pin, a fully compensated clock path results in zero-delay between the clock input and one of the output clocks from the pll. if the pll input is instead fed by a non-dedicated input (using the gclk network), the output clock may not be perfectly aligned with the input clock. source synchronous mode if data and clock arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any ioe input register. figure 5?22 shows an example waveform of the clock and data in this mode. altera recommends source synchronous mode for source-synchronous data transfers. data and clock signals at the ioe experience similar buffer delays as long as you use the same i/o standard. tab le 5 ?9 . clock feedback mode availability clock feedback mode availability top/bottom plls left/right plls source-synchronous yes yes no-compensation yes yes normal yes yes zero-delay buffer (zdb) yes yes external feedback (1) yes yes (2) lvds compensation no yes notes to ta bl e 5? 9 : (1) the high-bandwidth pll setting is not supported in the external feedback mode. (2) external feedback mode is supported for single-ende d inputs and outputs only on the left and right plls. chapter 5: clock networks and plls in stratix iv devices 5?27 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 source-synchronous mode compensates for the delay of the clock network used plus any difference in the delay between these two paths: source-synchronous mode for lvds compensation the goal of source-synchronous mode is to maintain the same data and clock timing relationship seen at the pins of the internal serializer/deserializer (serdes) capture register, except that the clock is inverted (180 phase shift). thus, source-synchronous mode ideally compensates for the delay of the lvds clock network plus any difference in delay between these two paths: figure 5?22. phase relationship between clock and data in source-synchronous mode data pin pll reference clock at input pin data at register clock at register 5?28 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation figure 5?23 shows an example waveform of the clock and data in lvds mode. no-compensation mode in no-compensation mode, the pll does not compensate for any clock networks. this mode provides better jitter performance because the clock feedback into the pfd passes through less circuitry. both the pll internal- and external-clock outputs are phase-shifted with respect to the pll clock input. figure 5?24 shows an example waveform of the pll clocks? phase relationship in no-compensation mode. figure 5?23. phase relationship between the clock and data in lvds mode figure 5?24. phase relationship between the pll clocks in no compensation mode note to figure 5?24 (1) the pll clock outputs lag the pll input clocks depending on routine delays. data pin pll reference clock at input pin data at register clock at register pll reference clock at the input pin pll clock at the register clock port (1) external pll clock outputs (1) phase aligned chapter 5: clock networks and plls in stratix iv devices 5?29 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 normal mode an internal clock in normal mode is phase-aligned to the input clock pin. the external clock-output pin has a phase delay relative to the clock input pin if connected in this mode. the quartus ii software timing analyzer reports any phase difference between the two. in normal mode, the delay introduced by the gclk or rclk network is fully compensated. figure 5?25 shows an example waveform of the pll clocks? phase relationship in normal mode. zero-delay buffer mode in zdb mode, the external clock output pin is phase-aligned with the clock input pin for zero-delay through the device. when using this mode, you must use the same i/o standard on the input clocks and output clocks to guarantee clock alignment at the input and output pins. zdb mode is supported on all stratix iv plls. when using stratix iv plls in zdb mode, along with single-ended i/o standards, to ensure phase alignment between the clk pin and the external clock output ( clkout) pin, you must instantiate a bi-directional i/o pin in the design to serve as the feedback path connecting the fbout and fbin ports of the pll. the pll uses this bi-directional i/o pin to mimic, and compensate for, the output delay from the clock output port of the pll to the external clock output pin. figure 5?26 shows zdb mode in stratix iv plls. when using zdb mode, you cannot use differential i/o standards on the pll clock input or output pins. 1 rc r w r 1 v rfc c r rc rc figure 5?25. phase relationship between the pll clocks in normal mode note to figure 5?25 : (1) the external clock output can lead or lag the pll internal clock signals. pll clock at the register clock port dedicated pll clock outputs (1) phase aligned pll reference clock at the input pin 5?30 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation figure 5?27 shows an example waveform of the pll clocks? phase relationship in zdb mode. external feedback mode in external feedback mode, the external feedback input pin ( fbin ) is phase-aligned with the clock input pin, as shown in figure 5?28 . aligning these clocks allows you to remove clock delay and skew between devices. this mode is supported on all stratix iv plls. in external feedback mode, the output of the m counter ( fbout ) feeds back to the pll fbin input (using a trace on the board) becoming part of the feedback loop. also, use one of the dual-purpose external clock outputs as the fbin input pin in this mode. when using external feedback mode, you must use the same i/o standard on the input clock, feedback input, and output clocks. left and right plls support this mode when using single-ended i/o standards only. figure 5?26. zdb mode in stratix iv plls inclk fbin fbout pll_<#>_clkout# n pfd cp/lf vco c0 c1 m bidirectional i/o pin pll_<#>_clkout# figure 5?27. phase relationship between the pll clocks in zdb mode note to figure 5?27 : (1) the internal pll clock output can lead or lag the external pll clock outputs. pll clock at the register clock port (1) dedicated pll clock outputs phase aligned pll reference clock at the input pin chapter 5: clock networks and plls in stratix iv devices 5?31 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 figure 5?28 shows an example waveform of the phase relationship between the pll clocks in external feedback mode. figure 5?29 shows external feedback mode implementation in stratix iv devices. clock multiplication and division each stratix iv pll provides clock synthesis for pll output ports using m /( n * post-scale counter) scaling factors. the input clock is divided by a pre-scale factor, n , and is then multiplied by the m feedback factor. the control loop drives the vco to match f in ( m / n ). each output port has a unique post-scale counter that divides down the high-frequency vco. for multiple pll outputs with different frequencies, the vco is set to the least common multiple of the output frequencies that meets its frequency specifications. for example, if the output frequencies required from one pll are 33 and 66 mhz, the quartus ii software sets the vco to 660 mhz (the least common multiple of 33 and 66 mhz within the vco range). then the post-scale counters scale down the vco frequency for each output port. figure 5?28. phase relationship between the pll clocks in external feedback mode note to figure 5?28 : (1) the pll clock outputs can lead or lag the fbin clock input. dedicated pll clock outputs (1) pll clock at the register clock port (1) fbin clock input pin phase aligned pll reference clock at the input pin figure 5?29. external feedback mode in stratix iv devices inclk fbin fbout external board trace pll_<#>_clkout# pll_<#>_clkout# n pfd cp/lf vco c0 c1 m 5?32 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation each pll has one pre-scale counter, n , and one multiply counter, m , with a range of 1 to 512 for both m and n . the n counter does not use duty-cycle control because the only purpose of this counter is to calculate frequency division. there are seven generic post-scale counters per left or right pll and ten post-scale counters per top or bottom pll that can feed the gclks, rclks, or external clock outputs. these post-scale counters range from 1 to 512 with a 50% duty cycle setting. the high- and low-count values for each counter range from 1 to 256. the sum of the high- and low-count values chosen for a design selects the divide value for a given counter. the quartus ii software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered into the altpll megafunction. post-scale counter cascading stratix iv plls support post-scale counter cascading to create counters larger than 512. this is automatically implemented in the quartus ii software by feeding the output of one c counter into the input of the next c counter, as shown in figure 5?30 . when cascading post-scale counters to implement a larger division of the high-frequency vco clock, the cascaded counters behave as one counter with the product of the individual counter settings. for example, if c0 = 40 and c1 = 20, the cascaded value is c0 c1 = 800. 1 c cr cc cfr f c rcfr figure 5?30. counter cascading note to figure 5?30 : (1) n = 6 or n = 9 c0 c1 c2 cn c3 c4 vco output vco output vco output vco output vco output vco output (1) from preceding post-scale counter chapter 5: clock networks and plls in stratix iv devices 5?33 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 programmable duty cycle the programmable duty cycle allows plls to generate clock outputs with a variable duty cycle. this feature is supported on the pll post-scale counters. the duty-cycle setting is achieved by a low and high time-count setting for the post-scale counters. to determine the duty cycle choices, the quartus ii software uses the frequency input and the required multiply or divide rate. the post-scale counter value determines the precision of the duty cycle. the precision is defined as 50% divided by the post-scale counter value. for example, if the c0 counter is 10, steps of 5% are possible for duty-cycle choices from 5% to 90%. if the pll is in external feedback mode, set the duty cycle for the counter driving the fbin pin to 50%. combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks. programmable phase shift use phase shift to implement a robust solution for clock delays in stratix iv devices. implement phase shift by using a combination of the vco phase output and the counter starting time. a combination of vco phase output and counter starting time is the most accurate method of inserting delays because it is only based on counter settings, which are independent of process, voltage, and temperature (pvt). you can phase-shift the output clocks from the stratix iv plls in either of these two resolutions: c[n..0]) or the m counter to use any of the eight phases of the vco as the reference clock. this allows you to adjust the delay time with a fine resolution. equation 5?1 shows the minimum delay time that you can insert using this method. where f ref is the input reference clock frequency. for example, if f ref is 100 mhz, n is 1, and m is 8, then f vco is 800 mhz and fine equals 156.25 ps. this phase shift is defined by the pll operating frequency, which is governed by the reference clock frequency and the counter settings. equation 5?1. fine-resolution phase shift fine = t vco = = 1 8 1 8f vco n 8mf ref 5?34 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation equation 5?2 shows the coarse-resolution phase shifts are implemented by delaying the start of the counters for a predetermined number of counter clocks. where c is the count value set for the counter delay time (this is the initial setting in the ?pll usage? section of the compilation report in the quartus ii software). if the initial value is 1, c ? 1 = 0 phase shift. figure 5?31 shows an example of phase-shift insertion with fine resolution using the vco phase-taps method. the eight phases from the vco are shown and labeled for reference. for this example, clk0 is based on the 0phase from the vco and has the c value for the counter set to one. the clk1 signal is divided by four, two vco clocks for high time and two vco clocks for low time. clk1 is based on the 135 phase tap from the vco and also has the c value for the counter set to one. in this case, the two clocks are offset by 3 fine . clk2 is based on the 0phase from the vco but has the c value for the counter set to three . this arrangement creates a delay of 2 coarse (two complete vco periods). you can use coarse- and fine-phase shifts to implement clock delays in stratix iv devices. stratix iv devices support dynamic phase-shifting of vco phase taps only. you can reconfigure the phase shift any number of times. each phase shift takes about one scanclk cycle, allowing you to implement large phase shifts quickly. equation 5?2. coarse-resolution phase shift coarse = = c ? 1 f (c ? 1) n mf ref v co figure 5?31. delay insertion using vco phase output and counter delay time t d0-1 t d0-2 1/8 t vco t vco 0 90 135 180 225 270 315 clk0 clk1 clk2 45 chapter 5: clock networks and plls in stratix iv devices 5?35 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 programmable bandwidth stratix iv plls provide advanced control of the pll bandwidth using the pll loop?s programmable characteristics, including loop filter and charge pump. background pll bandwidth is the measure of the pll?s ability to track the input clock and its associated jitter. the closed-loop gain 3 db frequency in the pll determines pll bandwidth. bandwidth is approximately the unity gain point for open loop pll response. as figure 5?32 shows, these points correspond to approximately the same frequency. stratix iv plls provide three bandwidth settings?low, medium (default), and high. figure 5?32. open- and closed-loop response bode plots increasing the pll's bandwidth in effect pushes the open loop response out. gain gain 0 db frequency frequency open-loop reponse bode plot closed-loop reponse bode plot 5?36 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation a high-bandwidth pll provides a fast lock time and tracks jitter on the reference clock source, passing it through to the pll output. a low-bandwidth pll filters out reference clock jitter but increases lock time. stratix iv plls allow you to control the bandwidth over a finite range to customize the pll characteristics for a particular application. the programmable bandwidth feature in stratix iv plls benefits applications requiring clock switchover. a high-bandwidth pll can benefit a system that must accept a spread-spectrum clock signal. stratix iv plls can track a spread-spectrum clock by using a high-bandwidth setting. using a low-bandwidth setting in this case could cause the pll to filter out the jitter on the input clock. a low-bandwidth pll can benefit a system using clock switchover. when clock switchover occurs, the pll input temporarily stops. a low-bandwidth pll reacts more slowly to changes on its input clock and takes longer to drift to a lower frequency (caused by the input stopping) than a high-bandwidth pll. implementation traditionally, external components such as the vco or loop filter control a pll?s bandwidth. most loop filters consist of passive components such as resistors and capacitors that take up unnecessary board space and increase cost. with stratix iv plls, all the components are contained within the device to increase performance and decrease cost. when you specify the bandwidth setting (low, medium, or high) in the altpll megawizard , icp, r, c ) values to achieve the desired bandwidth range. figure 5?33 shows the loop filter and components that you can set using the quartus ii software. the components are the loop filter resistor, r, the high frequency capacitor, c h , and the charge pump current, i up or i dn . figure 5?33. loop filter programmable components i up i dn c h pfd r c chapter 5: clock networks and plls in stratix iv devices 5?37 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 spread-spectrum tracking stratix iv devices can accept a spread-spectrum input with typical modulation frequencies. however, the device cannot automatically detect that the input is a spread-spectrum signal. instead, the input signal looks like deterministic jitter at the input of the pll. stratix iv plls can track a spread-spectrum input clock as long as it is within the input-jitter tolerance specifications. stratix iv devices cannot internally generate spread-spectrum clocks. clock switchover the clock switchover feature allows the pll to switch between two reference input clocks. use this feature for clock redundancy or for a dual-clock domain application such as in a system that turns on the redundant clock if the previous clock stops running. the design can perform clock switchover automatically when the clock is no longer toggling or based on a user control signal, clkswitch. the following clock switchover modes are supported in stratix iv plls: inclk0 or inclk1 clock. clkswitch signal. when the clkswitch signal goes from logic low to logic high, and stays high for at least three clock cycles, the reference clock to the pll is switched from inclk0 to inclk1 , or vice-versa. clkswitch signal goes high, it overrides the automatic clock switchover mode. stratix iv plls support a fully configurable clock switchover capability. figure 5?34 shows a block diagram of the automatic switchover circuit built into the pll. when the current reference clock is not present, the clock sense block automatically switches to the backup clock for pll reference. the clock switchover circuit also sends out three status signals? clkbad[0], clkbad[1] , and activeclock ?from the pll to implement a custom switchover circuit in the logic array. you can select a clock source as the backup clock by connecting it to the inclk1 port of the pll in your design. 5?38 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation automatic clock switchover use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current reference clock to the pll stops toggling. for example, in applications that require a redundant clock with the same frequency as the reference clock, the switchover state machine generates a signal ( clksw ) that controls the multiplexer select input, as shown in figure 5?34 . in this case, inclk1 becomes the reference clock for the pll. when using automatic switchover mode, you can switch back and forth between inclk0 and inclk1 any number of times when one of the two clocks fails and the other clock is available. when using automatic clock switchover mode, the following requirements must be satisfied: clkbad[0..1] signals are not valid. also, if both clock inputs are not the same frequency, but their period difference is within 100%, the clock sense block detects when a clock stops toggling, but the pll may lose lock after the switchover is completed and needs time to re-lock. 1 r rc r areset signal to maintain the phase relationships between the pll input and output clocks when using clock switchover. in automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two clock inputs. when they are asserted, the clock sense block has detected that the corresponding clock input has stopped toggling. these two signals are not valid if the frequency difference between inclk0 and inclk1 is greater than 20%. figure 5?34. automatic clock switchover circuit block diagram switchover state machine clock sense n counter pfd clkswitch activeclock clkbad[1] clkbad[0] muxout inclk0 inclk1 refclk fbclk clksw clock s witch control logic chapter 5: clock networks and plls in stratix iv devices 5?39 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 the activeclock signal indicates which of the two clock inputs ( inclk0 or inclk1 ) is being selected as the reference clock to the pll. when the frequency difference between the two clock inputs is more than 20%, the activeclock signal is the only valid status signal. figure 5?35 shows an example waveform of the switchover feature when using automatic switchover mode. in this example, the inclk0 signal is stuck low. after the inclk0 signal is stuck at low for approximately two clock cycles, the clock sense circuitry drives the clkbad[0] signal high. also, because the reference clock signal is not toggling, the switchover state machine controls the multiplexer through the clkswitch signal to switch to the backup clock, inclk1. manual override in automatic switchover with manual override mode, you can use the clkswitch input for user- or system-controlled switch conditions. you can use this mode for same-frequency switchover, or to switch between inputs of different frequencies. for example, if inclk0 is 66 mhz and inclk1 is 200 mhz, you must control switchover using clkswitch because the automatic clock-sense circuitry cannot monitor clock input ( inclk0 and inclk1 ) frequencies with a frequency difference of more than 100% (2). this feature is useful when the clock sources originate from multiple cards on the backplane, requiring a system-controlled switchover between the frequencies of operation. you must choose the backup clock frequency and set the m, n, c , and k counters accordingly so the vco operates within the recommended operating frequency range of 600 to 1,600 mhz. the altpll megawizard plug-in manager notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement. figure 5?35. automatic switchover upon loss of clock detection note to figure 5?35 : (1) switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. in this figure, switchover is enabled on the falling edge of inclk1. inclk0 inclk1 muxout clkbad0 clkbad1 (1) activeclock 5?40 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation figure 5?36 shows an example of a waveform showing the switchover feature when controlled by clkswitch . in this case, both clock sources are functional and inclk0 is selected as the reference clock; clkswitch goes high, which starts the switchover sequence. on the falling edge of inclk0 , the counter ?s reference clock, muxout , is gated off to prevent clock glitching. on the falling edge of inclk1 , the reference clock multiplexer switches from inclk0 to inclk1 as the pll reference and the activeclock signal changes to indicate which clock is currently feeding the pll. in automatic override with manual switchover mode, the activeclock signal mirrors the clkswitch signal. as both clocks are still functional during the manual switch, neither clkbad signal goes high. because the switchover circuit is positive-edge sensitive, the falling edge of the clkswitch signal does not cause the circuit to switch back from inclk1 to inclk0 . when the clkswitch signal goes high again, the process repeats. clkswitch and automatic switch only work if the clock being switched to is available. if the clock is not available, the state machine waits until the clock is available. manual clock switchover in manual clock switchover mode, the clkswitch signal controls whether inclk0 or inclk1 is selected as the input clock to the pll. by default, inclk0 is selected. a low-to-high transition on clkswitch and clkswitch being held high for at least three inclk cycles initiates a clock switchover event. you must bring clkswitch back low again in order to perform another switchover event in the future. if you do not require another switchover event in the future, you can leave clkswitch in a logic high state after the initial switch. pulsing clkswitch high for at least three inclk cycles performs another switchover event. if inclk0 and inclk1 are different frequencies and are always running, the clkswitch minimum high time must be greater than or equal to three of the slower frequency inclk0 or inclk1 cycles. figure 5?37 shows a block diagram of the manual switchover circuit. figure 5?36. clock switchover using the clkswitch (manual) control (note 1) note to figure 5?36 : (1) to initiate a manual clock switchover event, both inclk0 and inclk1 must be running when the clkswitch signal goes high. inclk0 inclk1 muxout clkswitch activeclock clkbad0 clkbad1 chapter 5: clock networks and plls in stratix iv devices 5?41 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 f for more information about pll software support in the quartus ii software, refer to the phase-locked loop (altpll) megafunction user guide . guidelines when implementing clock switchover in stratix iv plls, use the following guidelines: automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 100% (2) of each other. failing to meet this requirement causes the clkbad[0] and clkbad[1] signals to not function properly. when using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100% (2). however, differences in frequency, phase, or both, of the two clock sources will likely cause the pll to lose lock. resetting the pll ensures that the correct phase relationships are maintained between input and output clocks. 1 both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate the manual clock switchover event. failing to meet this requirement causes the clock switchover to not function properly. applications that require a clock switchover feature and a small frequency drift must use a low-bandwidth pll. the low-bandwidth pll reacts more slowly than a high-bandwidth pll to reference input clock changes. when switchover happens, a low-bandwidth pll propagates the stopping of the clock to the output more slowly than a high-bandwidth pll. however, be aware that the low-bandwidth pll also increases lock time. after a switchover occurs, there may be a finite resynchronization period for the pll to lock onto a new clock. the exact amount of time it takes for the pll to re-lock depends on the pll configuration. the phase relationship between the input clock to the pll and the output clock from the pll is important in your design. assert areset for at least 10 ns after performing a clock switchover. wait for the locked signal to go high and be stable before re-enabling the output clocks from the pll. figure 5?37. manual clock switchover circuitry in stratix iv plls n counter pfd fbcl k clkswitch inclk0 inclk1 muxout refclk clock s witch control logic 5?42 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation figure 5?38 shows how the vco frequency gradually decreases when the current clock is lost and then increases as the vco locks on to the backup clock. disable the system during clock switchover if it is not tolerant of frequency variations during the pll resynchronization period. you can use the clkbad[0] and clkbad[1] status signals to turn off the pfd ( pfdena = 0 ) so the vco maintains its most recent frequency. you can also use the state machine to switch over to the secondary clock. when the pfd is re-enabled, output clock-enable signals ( clkena ) can disable clock outputs during the switchover and resynchronization period. when the lock indication is stable, the system can re-enable the output clocks. pll reconfiguration plls use several divide counters and different vco phase taps to perform frequency synthesis and phase shifts. in stratix iv plls, you can reconfigure both the counter settings and phase-shift the pll output clock in real time. you can also change the charge pump and loop-filter components, which dynamically affects pll bandwidth. you can use these pll components to update the output-clock frequency and pll bandwidth and to phase-shift in real time, without reconfiguring the entire stratix iv device. the ability to reconfigure the pll in real time is useful in applications that operate at multiple frequencies. it is also useful in prototyping environments, allowing you to sweep pll output frequencies and adjust the output-clock phase dynamically. for instance, a system generating test patterns is required to generate and transmit patterns at 75 or 150 mhz, depending on the requirements of the device under test. reconfiguring the pll components in real time allows you to switch between two such output frequencies within a few microseconds. you can also use this feature to adjust clock-to-out ( tco ) delays in real time by changing the pll output clock phase shift. this approach eliminates the need to regenerate a configuration file with the new pll settings. pll reconfiguration hardware implementation the following pll components are reconfigurable in real time: pre-scale counter ( n) feedback counter ( m) figure 5?38. vco switchover operating frequency f vco primary clock stops running switchover occurs vco tracks secondary clock chapter 5: clock networks and plls in stratix iv devices 5?43 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 post-scale output counters ( c0 - c9) post vco divider ( k) dynamically adjust the charge-pump current ( icp ) and loop-filter components ( r, c ) to facilitate reconfiguration of the pll bandwidth figure 5?39 shows how you can dynamically adjust the pll counter settings by shifting their new settings into a serial shift-register chain or scan chain. serial data is input to the scan chain using the scandata port. shift registers are clocked by scanclk . the maximum scanclk frequency is 100 mhz. serial data is shifted through the scan chain as long as the scanclkena signal stays asserted. after the last bit of data is clocked, asserting the configupdate signal for at least one scanclk clock cycle causes the pll configuration bits to be synchronously updated with the data in the scan registers. 1 the counter settings are updated synchronously to the clock frequency of the individual counters. therefore, all counters are not updated simultaneously. figure 5?39. pll reconfiguration scan chain (note 1) notes to figure 5?39 : (1) stratix iv left and right plls support c0 - c6 counters. (2) i = 6 or i = 9. (3) this figure shows the corresponding scan register for the k counter in between the scan registers for the charge pump and loop filter. the k counter is physically located after the vco. /ci (2) /ci-1 /c2 /c1 /c0 /m /n scanclk scandone scandata lf/k/cp (3) configupdate inclk pfd vco scanclkena scandataout from m counter from n counter 5?44 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation table 5?10 lists how these signals can be driven by the pld logic array or i/o pins. to reconfigure the pll counters, perform the following steps: 1. the scanclkena signal is asserted at least one scanclk cycle prior to shifting in the first bit of scandata ( d0). 2. serial data ( scandata ) is shifted into the scan chain on the second rising edge of scanclk. 3. after all 234 bits (top and bottom plls) or 180 bits (left and right plls) have been scanned into the scan chain, the scanclkena signal is de-asserted to prevent inadvertent shifting of bits in the scan chain. 4. the configupdate signal is asserted for one scanclk cycle to update the pll counters with the contents of the scan chain. 5. the scandone signal goes high, indicating the pll is being reconfigured. a falling edge indicates the pll counters have been updated with new settings. 6. reset the pll using the areset signal if you make any changes to the m, n, or post-scale output c counters or to the icp, r, or c settings. 7. you can repeat steps 1-5 to reconfigure the pll any number of times. table 5?10. real-time pll reconfiguration ports pll port name description source destination scandata serial input data stream to scan chain. logic array or i/o pin pll reconfiguration circuit scanclk serial clock input signal. this clock can be free running. gclk, rclk or i/o pins pll reconfiguration circuit scanclkena enables scanclk and allows the scandata to be loaded in the scan chain. active high. logic array or i/o pin pll reconfiguration circuit configupdate writes the data in the scan chain to the pll. active high. logic array or i/o pin pll reconfiguration circuit scandone indicates when the pll has finished reprogramming. a rising edge indicates the pll has begun reprogramming. a falling edge indicates the pll has finished reprogramming. pll reconfiguration circuit logic array or i/o pins scandataout used to output the contents of the scan chain. pll reconfiguration circuit logic array or i/o pins chapter 5: clock networks and plls in stratix iv devices 5?45 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 figure 5?40 shows a functional simulation of the pll reconfiguration feature. 1 rcfr cr cc frc c rcfr crr cr f rfc rcfr f r c f rcfr rfc f rcfr cr frc w r f fr cc rcfr f fr rcfr cr cc frc post-scale counters (c0 to c9) you can reconfigure the multiply or divide values and duty cycle of post-scale counters in real time. each counter has an 8-bit high-time setting and an 8-bit low-time setting. the duty cycle is the ratio of output high- or low-time to the total cycle time, which is the sum of the two. additionally, these counters have two control bits, rbypass , for bypassing the counter, and rselodd , to select the output clock duty cycle. when the rbypass bit is set to 1, it bypasses the counter, resulting in a divide by 1. when the rbypass bit is set to 0, the high- and low-time counters are added to compute the effective division of the vco output frequency. for example, if the post-scale divide factor is 10, the high- and low-count values can be set to 5 and 5, respectively, to achieve a 50% - 50% duty cycle. the pll implements this duty cycle by transitioning the output clock from high to low on the rising edge of the vco output clock. however, a 4 and 6 setting for the high- and low-count values, respectively, produces an output clock with a 40% - 60% duty cycle. figure 5?40. pll reconfiguration waveform scandata scanclk scanclkena scandataout configupdate scandone areset d0_old dn_old dn dn (msb) (lsb) d0 5?46 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation the rselodd bit indicates an odd divide factor for the vco output frequency along with a 50% duty cycle. for example, if the post-scale divide factor is 3, the high- and low-time count values could be set to 2 and 1, respectively, to achieve this division. this implies a 67% - 33% duty cycle. if you need a 50% - 50% duty cycle, you can set the rselodd control bit to 1 to achieve this duty cycle despite an odd division factor. the pll implements this duty cycle by transitioning the output clock from high to low on a falling edge of the vco output clock. when you set rselodd = 1, you subtract 0.5 cycles from the high time and you add 0.5 cycles to the low time. for example: rselodd = 1 effectively equals: scan chain description the length of the scan chain varies for different stratix iv plls. the top and bottom plls have ten post-scale counters and a 234-bit scan chain, while the left and right plls have seven post-scale counters and a 180-bit scan chain. table 5?11 lists the number of bits for each component of a stratix iv pll. table 5?11. top and bottom pll reprogramming bits (part 1 of 2) block name number of bits total counter other (1) c9 (2) 16 2 18 c8 16 2 18 c7 16 2 18 c6 (3) 16 2 18 c5 16 2 18 c4 16 2 18 c3 16 2 18 c2 16 2 18 c1 16 2 18 c0 16 2 18 m1 621 8 n1 621 8 charge pump current 0 3 3 vco post-scale divider ( k )101 loop filter capacitor (4) 022 loop filter resistor 0 5 5 unused cp/lf 0 7 7 chapter 5: clock networks and plls in stratix iv devices 5?47 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 table 5?11 lists the scan chain order of pll components for the top and bottom plls, which have 10 post-scale counters. the order of bits is the same for the left and right plls, but the reconfiguration bits start with the c6 post-scale counter. figure 5?41 shows the scan-chain order of pll components for the top and bottom plls. figure 5?42 shows the scan-chain bit-order sequence for post-scale counters in all stratix iv plls. total number of bits ? ? 234 notes to ta bl e 5? 11 : (1) includes two control bits, rbypass , for bypassing the counter, and rselodd , to select the output clock duty cycle. (2) the lsb for the c9 low-count value is the first bit shifted into the scan chain for the top and bottom plls. (3) the lsb for the c6 low-count value is the first bit shifted into the scan chain for the left and right plls. (4) the msb for the loop filter is the last bit shifted into the scan chain. table 5?11. top and bottom pll reprogramming bits (part 2 of 2) block name number of bits total counter other (1) figure 5?41. scan-chain order of pll components for top and bottom plls (note 1) note to figure 5?41 : (1) left and right plls have the same scan-chain order. the post-scale counters end at c6. datain msb lf k cp lsb n m c0 c1 c2 c3 c4 c5 c6 c7 c8 datao u t c9 figure 5?42. scan-chain bit-order sequence for post-scale counters in stratix iv plls datain rbypass hb 7 hb 6 hb 5 hb 4 hb 3 hb 2 hb 1 hb 0 rselodd lb 7 lb 6 lb 5 lb 4 lb 3 lb 2 lb 1 lb 0 datao u t 5?48 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation charge pump and loop filter you can reconfigure the charge-pump and loop-filter settings to update the pll bandwidth in real time. table 5?12 lists the possible settings for charge pump current ( icp ) values for stratix iv plls. table 5?13 lists the possible settings for loop-filter resistor ( r ) values for stratix iv plls. table 5?14 lists the possible settings for loop-filter capacitor ( c ) values for stratix iv plls. table 5?12. charge pump current bit settings cp[2] cp[1] cp[0] decimal value for setting 000 0 001 1 011 3 111 7 table 5?13. loop-filter resistor bit settings lfr[4] lfr[3] lfr[2] lfr[1] lfr[0] decimal value for setting 0 0 000 0 0 0 011 3 0 0 100 4 0 1 000 8 1 0 000 16 1 0 011 19 1 0 100 20 1 1 000 24 1 1 011 27 1 1 100 28 1 1 110 30 table 5?14. loop-filter capacitor bit settings lfc[1] lfc[0] decimal value for setting 00 0 01 1 11 3 chapter 5: clock networks and plls in stratix iv devices 5?49 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 bypassing a pll bypassing a pll counter results in a multiply ( m counter) or a divide ( n and c0 to c9 counters) factor of one. table 5?15 lists the settings for bypassing the counters in stratix iv plls. 1 f cr 1 . the values on the other bits are ignored. to bypass the vco post-scale counter ( k ), set the corresponding bit to 0. dynamic phase-shifting the dynamic phase-shifting feature allows the output phases of individual pll outputs to be dynamically adjusted relative to each other and to the reference clock, without having to send serial data through the scan chain of the corresponding pll. this feature simplifies the interface and allows you to quickly adjust the clock-to-out ( t co ) delays by changing the output clock phase-shift in real time. this adjustment is achieved by incrementing or decrementing the vco phase-tap selection to a given c counter or to the m counter. the phase is shifted by 1/8 of the vco frequency at a time. the output clocks are active during this phase-reconfiguration process. table 5?16 lists the control signals that are used for dynamic phase-shifting. table 5?15. pll counter settings pll scan chain bits [0..8] settings lsb msb description x xxxxxxx1 (1) pll counter bypassed x xxxxxxx0 (1) pll counter not bypassed because bit 8 (msb) is set to 0 notes to ta bl e 5? 15 : (1) counter-bypass bit. table 5?16. dynamic phase-shifting control signals (part 1 of 2) signal name description source destination phasecounter select[3..0] counter select. four bits decoded to select either the m or one of the c counters for phase adjustment. one address maps to select all c counters. this signal is registered in the pll on the rising edge of scanclk . logic array or i/o pins pll reconfiguration circuit phaseupdown selects dynamic phase shift direction; 1 = up; 0 = down. signal is registered in the pll on the rising edge of scanclk . logic array or i/o pin pll reconfiguration circuit phasestep logic high enables dynamic phase shifting. logic array or i/o pin pll reconfiguration circuit 5?50 chapter 5: clock networks and plls in stratix iv devices plls in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation table 5?17 lists the pll counter selection based on the corresponding phasecounterselect setting. to perform one dynamic phase-shift, follow these steps: 1. set phaseupdown and phasecounterselect as required. 2. assert phasestep . each phasestep pulse enables one phase shift. the phasestep pulses must be at least one scanclk cycle apart. 3. wait for phasedone to go low. 4. de-assert phasestep. 5. wait for phasedone to go high. 6. repeat steps 1-5 as many times as required to perform multiple phase-shifts. all signals are synchronous to scanclk and are latched on the scanclk edges and must meet tsu/th requirements with respect to scanclk edges. scanclk free running clock from the core used in combination with phasestep to enable and disable dynamic phase shifting. shared with scanclk for dynamic reconfiguration. gclk, rclk or i/o pin pll reconfiguration circuit phasedone when asserted, this indicates to core-logic that the phase adjustment is complete and the pll is ready to act on a possible second adjustment pulse. asserts based on internal pll timing. de-asserts on the rising edge of scanclk . pll reconfiguration circuit logic array or i/o pins table 5?16. dynamic phase-shifting control signals (part 2 of 2) signal name description source destination table 5?17. phase counter select mapping phasecounterselect[3] [2] [1] [0] selects 0 0 0 0 all output counters 00 0 1 m counter 00 1 0 c0 counter 00 1 1 c1 counter 01 0 0 c2 counter 01 0 1 c3 counter 01 1 0 c4 counter 01 1 1 c5 counter 10 0 0 c6 counter 10 0 1 c7 counter 10 1 0 c8 counter 10 1 1 c9 counter chapter 5: clock networks and plls in stratix iv devices 5?51 plls in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 1 you can repeat dynamic phase-shifting indefinitely. for example, in a design where the vco frequency is set to 1000 mhz and the output clock frequency is 100 mhz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift) results in shifting the output clock by 180, which is a phase shift of 5 ns. the phasestep signal is latched on the negative edge of scanclk . in figure 5?43 , this is shown by the second scanclk falling edge. phasestep must stay high for at least two scanclk cycles. on the second scanclk rising edge after phasestep is latched (the fourth scanclk rising edge in figure 5?43 ), the values of phaseupdown and phasecounterselect are latched and the pll starts dynamic phase-shifting for the specified counter(s) and in the indicated direction. on the fourth scanclk rising edge, phasedone goes from high to low and remains low until the pll finishes dynamic phase-shifting. you can perform another dynamic phase shift after the phasedone signal goes from low to high. depending on the vco and scanclk frequencies, phasedone low time may be greater than or less than one scanclk cycle. after phasedone goes from low to high, you can perform another dynamic phase shift. phasestep pulses must be at least one scanclk cycle apart. f for information about the altpll_reconfig megawizard plug-in manager, refer to the phase-locked loops reconfiguration (altpll_reconfig) megafunction user guide . figure 5?43. dynamic phase shifting waveform scanclk phasestep phaseupdown phasecounterselect phasedone phasedone goes low synchronous with scanclk ab cd 5?52 chapter 5: clock networks and plls in stratix iv devices chapter revision history stratix iv device handbook volume 1 ? march 2010 altera corporation pll specifications f for information about pll timing specifications, refer to the dc and switching characteristics of stratix iv devices chapter. chapter revision history table 5?18 lists the revision history for this chapter. table 5?18. chapter revision history (part 1 of 2) date and document version changes made summary of changes march 2010, v3.1 updated tab le 5 ?3 . updated notes to figure 5?2 , figure 5?3 , figure 5?4 , and figure 5?9 . added a note to ta ble 5? 5 and table 5?6 . added two notes to tab le 5 ?4 . updated figure 5?43 . updated the ?dynamic phase-shifting? section. minor text edits. ? november 2009 v3.0 updated table 5?1 and table 5?7. updated ?clock networks in stratix iv devices?, ?periphery clock networks?, and ?cascading plls? sections. added figure 5?5, figure 5?6, figure 5?7, figure 5?8, and figure 5?9. added ?clock sources per region? section. updated figure 5?40. removed ep4se110, ep4se290, and ep4se680 devices. added ep4s40g2, ep4s100g2, ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5, and ep4se820 devices. ? june 2009 v2.3 updated table 5?7. updated the ?pll reconfiguration hardware implementation? and ?zero-delay buffer mode? sections. added introductory sentences to improve search ab ility. removed the conclusion section. minor text edits. ? april 2009 v2.2 updated table 5?1 and table 5?7. updated figure 5?3 and figure 5?4. updated the ?periphery clock networks? section. ? march 2009 v2.1 updated table 5?7. updated figure 5?34. updated ?guidelines? section. removed ?referenced documents? section. ? chapter 5: clock networks and plls in stratix iv devices 5?53 chapter revision history ? march 2010 altera corporation stratix iv device handbook volume 1 november 2008 v2.0 updated table 5?7. updated note 1 of figure 5?10. updated figure 5?15. updated figure 5?20 . added figure 5?21 . made minor editorial changes. ? may 2008 v1.0 initial release. ? table 5?18. chapter revision history (part 2 of 2) date and document version changes made summary of changes 5?54 chapter 5: clock networks and plls in stratix iv devices chapter revision history stratix iv device handbook volume 1 ? march 2010 altera corporation ? march 2010 altera corporation stratix iv device handbook volume 1 section ii. i/o interfaces this section provides information on stratix ? iv device i/o features, external memory interfaces, and high-speed differential interfaces with dpa. this section includes the following chapters: revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook. ii?2 section ii: i/o interfaces revision history stratix iv device handbook volume 1 ? march 2010 altera corporation ? march 2010 altera corporation stratix iv device handbook volume 1 6. i/o features in stratix iv devices this chapter describes how stratix ? , ? , , siv51006-3.1 6?2 chapter 6: i/o features in stratix iv devices i/o standards support stratix iv device handbook volume 1 ? march 2010 altera corporation open-drain output serial, parallel, and dynamic on-chip termination (oct) differential oct programmable pre-emphasis programmable equalization programmable differential output voltage (v od ) this chapter contains the following sections: ?i/o standards support? ?i/o banks? on page 6?5 ?i/o structure? on page 6?17 ?on-chip termination support and i/o termination schemes? on page 6?24 ?oct calibration? on page 6?31 ?termination schemes for i/o standards? on page 6?38 ?design considerations? on page 6?45 i/o standards support stratix iv devices support a wide range of industry i/o standards. table 6?1 lists the i/o standards stratix iv devices support, as well as the typical applications. these devices support v ccio voltage levels of 3.0, 2.5, 1.8, 1.5, and 1.2 v. tab le 6 ?1 . stratix iv i/o standards and applications (part 1 of 2) i/o standard application 3.3-v lvttl/lvcmos (1) , (2) general purpose 2.5-v lvcmos general purpose 1.8-v lvcmos general purpose 1.5-v lvcmos general purpose 1.2-v lvcmos general purpose 3.0-v pci/pci-x pc and embedded system sstl-2 class i and ii ddr sdram sstl-18 class i and ii ddr2 sdram sstl-15 class i and ii ddr3 sdram hstl-18 class i and ii qdrii/rldram ii hstl-15 class i and ii qdrii/qdrii+/rldram ii hstl-12 class i and ii general purpose differential sstl-2 class i and ii ddr sdram differential sstl-18 class i and ii ddr2 sdram differential sstl-15 class i and ii ddr3 sdram differential hstl-18 class i and ii clock interfaces differential hstl-15 class i and ii clock interfaces chapter 6: i/o features in stratix iv devices 6?3 i/o standards support ? march 2010 altera corporation stratix iv device handbook volume 1 f for more information about transceiver supported i/o standards, refer to the stratix iv transceiver architecture chapter. i/o standards and voltage levels stratix iv devices support a wide range of industry i/o standards, including single-ended, voltage-referenced single-ended, and differential i/o standards. table 6?2 lists the supported i/o standards and typical values for input and output v ccio , v ccpd , v ref , and board v tt . differential hstl-12 class i and ii clock interfaces lvds high-speed communications rsds flat panel display mini-lvds flat panel display lvpecl video graphics and clock distribution notes to ta bl e 6? 1 : (1) the 3.3-v lvttl/lvcmos standard is supported using v ccio at 3.0 v. (2) for more information about the 3.3-v lvttl/lvcmos standard supported in stratix iv devices, refer to ?3.3-v i/o interface? on page 6?19 . tab le 6 ?1 . stratix iv i/o standards and applications (part 2 of 2) i/o standard application tab le 6 ?2 . stratix iv i/o standards and voltage levels (note 1) (part 1 of 3) i/o standard standard support v ccio (v) v ccpd (v) (pre-driver voltage) v ref (v) (input ref voltage) v tt (v) (board termination voltage) input operation output operation column i/o banks row i/o banks column i/o banks row i/o banks 3.3-v lvttl jesd8-b 3.0/2.5 3.0/2.5 3.0 3.0 3.0 ? ? 3.3-v lvcmos (3) jesd8-b 3.0/2.5 3.0/2.5 3.0 3.0 3.0 ? ? 2.5-v lvcmos jesd8-5 3.0/2.5 3.0/2.5 2.5 2.5 2.5 ? ? 1.8-v lvcmos jesd8-7 1.8/1.5 1.8/1.5 1.8 1.8 2.5 ? ? 1.5-v lvcmos jesd8-11 1.8/1.5 1.8/1.5 1.5 1.5 2.5 ? ? 1.2-v lvcmos jesd8-12 1.2 1.2 1.2 1.2 2.5 ? ? 3.0-v pci pci rev 2.1 3.0 3.0 3.0 3.0 3.0 ? ? 3.0-v pci-x pci-x rev 1.0 3.0 3.0 3.0 3.0 3.0 ? ? sstl-2 class i jesd8-9b (2) (2) 2.5 2.5 2.5 1.25 1.25 sstl-2 class ii jesd8-9b (2) (2) 2.5 2.5 2.5 1.25 1.25 sstl-18 class i jesd8-15 (2) (2) 1.8 1.8 2.5 0.90 0.90 sstl-18 class ii jesd8-15 (2) (2) 1.8 1.8 2.5 0.90 0.90 sstl-15 class i ? (2) (2) 1.5 1.5 2.5 0.75 0.75 sstl-15 class ii ? (2) (2) 1.5 ? 2.5 0.75 0.75 hstl-18 class i jesd8-6 (2) (2) 1.8 1.8 2.5 0.90 0.90 hstl-18 class ii jesd8-6 (2) (2) 1.8 1.8 2.5 0.90 0.90 6?4 chapter 6: i/o features in stratix iv devices i/o standards support stratix iv device handbook volume 1 ? march 2010 altera corporation hstl-15 class i jesd8-6 (2) (2) 1.5 1.5 2.5 0.75 0.75 hstl-15 class ii jesd8-6 (2) (2) 1.5 ? 2.5 0.75 0.75 hstl-12 class i jesd8-16a (2) (2) 1.2 1.2 2.5 0.6 0.6 hstl-12 class ii jesd8-16a (2) (2) 1.2 ? 2.5 0.6 0.6 differential sstl-2 class i jesd8-9b (2) (2) 2.5 2.5 2.5 ? 1.25 differential sstl-2 class ii jesd8-9b (2) (2) 2.5 2.5 2.5 ? 1.25 differential sstl-18 class i jesd8-15 (2) (2) 1.8 1.8 2.5 ? 0.90 differential sstl-18 class ii jesd8-15 (2) (2) 1.8 1.8 2.5 ? 0.90 differential sstl-15 class i ? (2) (2) 1.5 1.5 2.5 ? 0.75 differential sstl-15 class ii ? (2) (2) 1.5 ? 2.5 ? 0.75 differential hstl-18 class i jesd8-6 (2) (2) 1.8 1.8 2.5 ? 0.90 differential hstl-18 class ii jesd8-6 (2) (2) 1.8 1.8 2.5 ? 0.90 differential hstl-15 class i jesd8-6 (2) (2) 1.5 1.5 2.5 ? 0.75 differential hstl-15 class ii jesd8-6 (2) (2) 1.5 ? 2.5 ? 0.75 differential hstl-12 class i jesd8-16a (2) (2) 1.2 1.2 2.5 ? 0.60 differential hstl-12 class ii jesd8-16a (2) (2) 1.2 ? 2.5 ? 0.60 lvds (4) , (5) , ( 8 ) ansi/tia/ eia-644 (2) (2) 2.5 2.5 2.5 ? ? rsds (6) , (7) , ( 8 ) ? (2) (2) 2.5 2.5 2.5 ? ? mini-lvds (6) , (7) , ( 8 ) ? (2) (2) 2.5 2.5 2.5 ? ? tab le 6 ?2 . stratix iv i/o standards and voltage levels (note 1) (part 2 of 3) i/o standard standard support v ccio (v) v ccpd (v) (pre-driver voltage) v ref (v) (input ref voltage) v tt (v) (board termination voltage) input operation output operation column i/o banks row i/o banks column i/o banks row i/o banks chapter 6: i/o features in stratix iv devices 6?5 i/o banks ? march 2010 altera corporation stratix iv device handbook volume 1 f for more information about electrical characteristics of each i/o standard, refer to the dc and switching characteristics chapter. i/o banks stratix iv devices contain up to 24 i/o banks, as shown in figure 6?1 and figure 6?2 . the row i/o banks contain true differential input and output buffers and dedicated circuitry to support differential standards at speeds up to 1.6 gbps. each i/o bank in stratix iv devices can support high-performance external memory interfaces with dedicated circuitry. the i/o pins are organized in pairs to support differential standards. each i/o pin pair can support both differential input and output buffers. the only exceptions are the clk[1,3,8,10] , pll_l[1,4]_clk, and pll_r[1,4]_clk pins, which support differential input operations only. f for the number of channels available for the lvds i/o standard, refer to the high-speed differential i/o interface and dpa in stratix iv devices chapter. for more information about transceiver-bank-related features, refer to the stratix iv transceiver architecture chapter. lvpecl ? (4) 2.5 ? ? 2.5 ? ? notes to ta bl e 6? 2 : (1) v ccpd is either 2.5 or 3.0 v. for v ccio = 3.0 v, v ccpd = 3.0 v. for v ccio = 2.5 v or less, v ccpd = 2.5 v. (2) single-ended hstl/sstl, differential sstl/hstl, and lvds input buffers are powered by v ccpd . row i/o banks support both true differential input buffers and true differential output buffers. column i/o banks support true differential input buffers, but not true differential output buffers. i/o pins are organized in pairs to support differential standards. column i/o differential hstl and sstl inputs use lvds differential input buffers without on-chip r d support. (3) for more information about the 3.3-v lvttl/lvcmos standard supported in stratix iv devices, refer to ?3.3-v i/o interface? on page 6?19 . (4) column i/o banks support lvpecl i/o standards for input clock operation. clock inputs on column i/os are powered by v ccclkin when configured as differential clock inputs. they are powered by v ccio when configured as single-ended clock inputs. differential clock inputs in row i/os are powered by v ccpd . (5) column and row i/o banks support lvds outputs using two single-ended output buffers, an external one-resistor (lvds_e_1r), and a three-resistor (lvds_e_3r) network. (6) row i/o banks support rsds and mini-lvds i/o standards using a true lvds output buffer without a resistor network. (7) column and row i/o banks support rsds and mini-lvds i/o standards using two single-ended output buffers with one-resistor (rsds_e_1r and mini-lvds_e_1r) and three-resistor (rsds_e_3r and mini-lvds_e_3r) networks. (8) the emulated differential output standard that supports the tri-state feature includes: lvds_e_1r, lvds_e_3r, rsds_e_1r, rsds_e_3r, mini_lvds_e_1r, and mini_lvds_e_3r. for more information, refer to the i/o buffer (altiobuf) megafunction user guide . tab le 6 ?2 . stratix iv i/o standards and voltage levels (note 1) (part 3 of 3) i/o standard standard support v ccio (v) v ccpd (v) (pre-driver voltage) v ref (v) (input ref voltage) v tt (v) (board termination voltage) input operation output operation column i/o banks row i/o banks column i/o banks row i/o banks 6?6 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook volume 1 ? march 2010 altera corporation figure 6?1. stratix iv e devices i/0 banks (note 1) , (2) , (3) , (4) , (5) , (6) , (7), ( 8 ) notes to figure 6?1 : (1) differential hstl and sstl outputs are not true differential outputs. they use two single-ended outputs with the second output programmed as inverted. (2) column i/o differential hstl and sstl inputs use lvds differential input buffers without differential oct support. (3) column i/o supports lvds outputs using single-ended buffers and external resistor networks. (4) column i/o supports pci/pci-x with on-chip clamp diode. row i/o supports pci/pci-x with external clamp diode. (5) clock inputs on column i/os are powered by v ccclkin when configured as differential clock inputs. they are powered by v ccio when configured as single-ended clock inputs. all outputs use the corresponding bank v ccio . (6) row i/o supports the true lvds output buffer. (7) column and row i/o banks support lvpecl standards for input clock operation. (8) figure 6?1 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. it is a graphical representation o nly. bank 1a bank 8a bank 1c bank 1b bank 2c bank 2a bank 2b bank 8b bank 7b bank 7a bank 7c bank 8c bank 3a bank 3b bank 4b bank 4a bank 4c bank 3c bank 6a bank 6c bank 6b bank 5c bank 5a bank 5b i/o banks 8a, 8b, and 8c support all single-ended and differential input and output operations except lvpecl, which is supported on clk input pins only. i/o banks 7a, 7b, and 7c support all single-ended and differential input and output operations except lvpecl, which is supported on clk input pins only. i/o banks 3a, 3b, and 3c support all single-ended and differential input and output operations except lvpecl, which is supported on clk input pins only. i/o banks 4a, 4b, and 4c support all single-ended and differential input and output operations except lvpecl, which is supported on clk input pins only. row i/o banks support lvttl, lvcmos, 2.5-v, 1.8-v, 1.5-v, 1.2-v, sstl-2 class i & ii, sstl-18 class i & ii, sstl-15 class i, hstl-18 class i & ii, hstl-15 class i, hstl-12 class i, lvds, rsds, mini-lvds, differential sstl-2 class i & ii, differential sstl-18 class i & ii, differential sstl-15 class i, differential hstl-18 class i & ii, differential hstl-15 class i, and differential hstl -12 class i standards for input and output operations. lvpecl i/o standard for input operation on dedicated clock input pins. sstl-15 class ii, hstl-15 class ii, hstl-12 class ii, differential sstl-15 class ii, differential hstl-15 class ii, differential hstl-12 class ii standards are only supported for input operations. chapter 6: i/o features in stratix iv devices 6?7 i/o banks ? march 2010 altera corporation stratix iv device handbook volume 1 figure 6?2. stratix iv gx devices i/o banks (note 1) , (2) , (3) , (4) , (5) , (6) , (7) , ( 8 ) notes to figure 6?2 : (1) differential hstl and sstl outputs are not true differential outputs. they use two single-ended outputs with the second output programmed as inverted. (2) column i/o differential hstl and sstl inputs use lvds differential input buffers without differential oct support. (3) column i/o supports lvds outputs using single-ended buffers and external resistor networks. (4) column i/o supports pci/pci-x with an on-chip clamp diode. row i/o supports pci/pci-x with an external clamp diode. (5) clock inputs on column i/os are powered by v ccclkin when configured as differential clock inputs. they are powered by v ccio when configured as single-ended clock inputs. all outputs use the corresponding bank v ccio . (6) row i/o supports the true lvds output buffer. (7) column and row i/o banks support lvpecl standards for input clock operation. (8) figure 6?2 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. it is a graphical representation o nly. bank 3a bank 3b bank 4b bank 4a bank 4c bank 3c i/o banks 8a, 8b & 8c support all single-ended and differential input and output operation. i/o banks 7a, 7b & 7c support all single-ended and differential input and output operation. i/o banks 3a, 3b & 3c support all single-ended and differential input and output operation. i/o banks 4a, 4b & 4c support all single-ended and differential input and output operation. bank 1a bank 1c bank 2c bank 2b bank 2a bank 5a bank 5b bank5c bank 6c bank 6a transceiver bank gxbr3 transceiver bank gxbr2 transceiver bank gxbr1 transceiver bank gxbr0 transceiver bank gxbl3 transceiver bank gxbl2 transceiver bank gxbl1 transceiver bank gxbl0 row i/o banks support lvttl, lvcmos, 2.5-v, 1.8- v, 1.5-v, 1.2-v, sstl-2 class i & ii, sstl-18 class i & ii, sstl-15 class i, hstl-18 class i & ii, hstl-15 class i, hstl-12 class i, lvds, rsds, mini-lvds, differential sstl-2 class i & ii, differential sstl-18 class i & ii, differential sstl-15 class i, differential hstl-18 class i & ii, differential hstl-15 class i and differential hstl-12 class i standards for input and output operation. sstl-15 class ii, hstl-15 class ii, hstl-12 class ii, differential sstl-15 class ii, differential hstl-15 class ii, differential hstl-12 class ii standards are only supported for input operations bank 1b bank 6b bank 8a bank 8b bank 7b bank 7a bank 7c bank 8c 6?8 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook volume 1 ? march 2010 altera corporation modular i/o banks the i/o pins in stratix iv devices are arranged in groups called modular i/o banks. depending on device densities, the number of stratix iv device i/o banks range from 16 to 24. the number of i/o pins on each bank is 24, 32, 36, 40, or 48. figure 6?4 through figure 6?16 show the number of i/o pins available in each i/o bank. in stratix iv devices, the maximum number of i/o banks per side is either four or six, depending on the device density. when migrating between devices with a different number of i/o banks per side, it is the middle or ?b? bank that is removed or inserted. for example, when moving from a 24-bank device to a 16-bank device, the banks that are dropped are ?b? banks, namely: 1b, 2b, 3b, 4b, 5b, 6b, 7b, and 8b. similarly, when moving from a 16-bank device to a 24-bank device, the banks that are added are the same ?b? banks. after migration from a smaller device to a larger device, the bank size increases or remains the same, but never decreases. for example, the number of i/o pins to a bank may increase from 24 to 26, 32, 36, 40, 42, or 48, but will never decrease. this is shown in figure 6?3 . figure 6?3. bank migration path with increasing device size 24 26 32 36 40 42 48 chapter 6: i/o features in stratix iv devices 6?9 i/o banks ? march 2010 altera corporation stratix iv device handbook volume 1 figure 6?4 through figure 6?16 show the number of i/o pins and packaging information for different sets of available devices. they show the top view of the silicon die that corresponds to a reverse view for flip chip packages. they are graphical representations only. 1 r r r r 1 c c r r c cc r cfr rcvr c cfr r c c figure 6?4. number of i/os in each bank in ep4se230 and ep4se360 devices in the 780-pin fineline bga package figure 6?5. number of i/os in each bank in ep4se360, ep4se530, and ep4se820 devices in the 1152-pin fineline bga package ep4se230 ep4se360 bank 7a 40 bank 7c 24 26 bank 1c 26 bank 2c 40 bank 4a 24 bank 4c bank 5c 26 32 bank 2a bank 8c 24 bank 8a 40 24 bank 3c 40 bank 3a bank 5a 32 bank 6a 32 bank name number of i/os bank name number of i/os 32 bank 1a bank 6c 26 ep4se360 ep4se530 ep4se820 bank 8b 24 bank 7a 40 bank 7b 24 bank 7c 32 42 bank 1c 42 bank 2c 24 bank 3b 40 bank 4a 24 bank 4b 32 bank 4c bank 6c 42 bank 5c 42 48 bank 2a bank 8c 32 bank 8a 40 32 bank 3c 40 bank 3a bank 5a 48 bank 6a 48 bank name number of i/os bank name number of i/os 48 bank 1a 6?10 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook volume 1 ? march 2010 altera corporation figure 6?6. number of i/os in each bank in ep4se530 and ep4se820 devices in the 1517-pin fineline bga package figure 6?7. number of i/os in each bank in ep4se530 and ep4se820 devices in the 1760-pin fineline bga package ep4se530 ep4se820 bank 8b 48 bank 7a 48 bank 7b 48 bank 7c 32 42 bank 1c 24 bank 1b 24 bank 2b 42 bank 2c 48 bank 3b 48 bank 4a 48 bank 4b 32 bank 4c bank 6c 42 bank 6b 24 bank 5b 24 bank 5c 42 50 bank 1a 50 bank 2a bank 8c 32 bank 8a 48 32 bank 3c 48 bank 3a bank 5a 50 bank 6a 50 bank name number of i/os bank name number of i/os ep4se530 ep4se820 bank 8b 48 bank 7a 48 bank 7b 48 bank 7c 48 50 bank 1c 36 bank 1b 36 bank 2b 50 bank 2c 48 bank 3b 48 bank 4a 48 bank 4b 48 bank 4c bank 6c 50 bank 6b 36 bank 5b 36 bank 5c 50 50 bank 1a 50 bank 2a bank 8c 48 bank 8a 48 48 bank 3c 48 bank 3a bank 5a 50 bank 6a 50 bank name number of i/os bank name number of i/os chapter 6: i/o features in stratix iv devices 6?11 i/o banks ? march 2010 altera corporation stratix iv device handbook volume 1 figure 6?8. number of i/os in each bank in ep4sgx70, ep4sgx110, ep4sgx180, and ep4sgx230 devices in the 780-pin fineline bga package figure 6?9. number of i/os in each bank in ep4sgx290 and ep4sgx360 devices in the 780-pin fineline bga package bank 7a 40 bank 7c 24 26 bank 1c 26 bank 2c 40 bank 4a 24 bank 4c 32 bank 2a bank 8c 24 bank 8a 40 24 bank 3c 40 bank 3a bank name number of i/os bank name number of i/os 32 bank 1a number of transceiver channels bank gxbr0 4 4 bank gxbr1 ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 40 bank 4a 32 bank 4c 32 bank 3c 40 bank 3a 4 4 4 4 number of i/os bank name number of transceiver channels bank name number of i/os bank gxbr1 bank gxbr0 bank gxbl1 bank gxbl0 number of transceiver channels bank 1c bank 7a 40 bank 7c 32 bank 8c 32 bank 8a 40 1 ep4sgx290 ep4sgx360 6?12 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook volume 1 ? march 2010 altera corporation figure 6?10. number of i/os in each bank in ep4sgx70 and ep4sgx110 devices in the 1152-pin fineline bga package figure 6?11. number of i/os in each bank in ep4sgx180, ep4sgx230, ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1152-pin fineline bga package (note 1) , (2) notes to figure 6?11 : (1) except for the ep4sgx530 device, all listed devices have two variants in the f1152 package option?one with no pma-only trans ceiver channels and the other with two pma-only transceiver channels for each tr ansceiver bank. the ep4sgx530 device is only offered with two p ma-only transceiver channels for each transceiver bank in the f1152 package option. (2) there are two additional pma-only transceiver channels in each transceiver bank for devices with the pma-only transceiver pa ckage option. bank 7a 40 bank 7c 24 40 bank 4a 24 bank 4c bank 8c 24 bank 8a 40 24 bank 3c 40 bank 3a bank name number of i/os number of i/os bank name *number of transceiver channels 4* 4* 4* 4* 32 26 bank 1a bank 1c bank gxbl1 bank gxbl0 bank gxbr1 bank gxbr0 bank 6a bank 6c 32 26 ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx290 ep4sgx360 bank 8b 24 bank 7a 40 bank 7b 24 bank 7c 32 24 bank 3b 40 bank 4a 24 bank 4b 32 bank 4c bank 8c 32 bank 8a 40 32 bank 3c 40 bank 3a bank name number of i/os bank name number of i/os 4 (2) 4 (2) 48 42 bank gxbl1 bank gxbl0 bank 1a bank 1c 48 42 bank gxbr1 bank gxbr0 bank 6a bank 6c ep4sgx230 ep4sgx530 4 (2) 4 (2) chapter 6: i/o features in stratix iv devices 6?13 i/o banks ? march 2010 altera corporation stratix iv device handbook volume 1 figure 6?12. number of i/os in each bank in ep4sgx180, ep4sgx230, ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1517-pin fineline bga package (note 1) note to figure 6?12 : (1) there are two additional pma-only transceiver channels in each transceiver bank. bank 8b 24 bank 7a 40 bank 7b 24 bank 7c 32 42 bank 1c 42 bank 2c 24 bank 3b 40 bank 4a 24 bank 4b 32 bank 4c bank 6c 42 bank 5c 42 48 bank 2a bank 8c 32 bank 8a 40 32 bank 3c 40 bank 3a bank 5a 48 bank 6a 48 bank name number of i/os bank name number of i/os 48 bank 1a bank gxbl2 bank gxbl1 bank gxbl0 4 (1) bank gxbr2 bank gxbr1 bank gxbr0 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 6?14 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook volume 1 ? march 2010 altera corporation figure 6?13. number of i/os in each bank in ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1932-pin fineline bga package (note 1) note to figure 6?13 : (1) there are two additional pma-only transceiver channels in each transceiver bank. ep4sgx530 ep4sgx290 ep4sgx360 bank 8b 48 bank 7a 48 bank 7b 48 bank 7c 32 48 bank 3b 48 bank 4a 48 bank 4b 32 bank 4c bank 8c 32 bank 8a 48 32 bank 3c 48 bank 3a number of i/os bank name bank name number of i/os bank 1a bank 1c bank 2c bank 2b bank 2a bank gxbl3 bank gxbl2 bank gxbl1 bank gxbl0 50 50 42 42 20 4 (1) bank 6a bank 6c bank 5c bank 5b bank 5a bank gxbr3 bank gxbr2 bank gxbr1 bank gxbr0 50 50 42 42 20 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) chapter 6: i/o features in stratix iv devices 6?15 i/o banks ? march 2010 altera corporation stratix iv device handbook volume 1 figure 6?14. number of i/os in each bank in ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1760-pin fineline bga package (note 1) note to figure 6?14 : (1) there are two additional pma-only transceiver channels in each transceiver bank. bank 8b 48 bank 7a 48 bank 7b 48 bank 7c 32 42 bank 1c 42 bank 2c 48 bank 3b 48 bank 4a 48 bank 4b 32 bank 4c bank 6c 42 bank 5c 42 50 bank 2a bank 8c 32 bank 8a 48 32 bank 3c 48 bank 3a bank 5a 50 bank 6a 50 bank name number of i/os bank name number of i/os 50 bank 1a bank gxbl2 bank gxbl1 bank gxbl0 4 (1) bank gxbr2 bank gxbr1 bank gxbr0 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) ep4sgx290 ep4sgx360 ep4sgx530 6?16 chapter 6: i/o features in stratix iv devices i/o banks stratix iv device handbook volume 1 ? march 2010 altera corporation figure 6?15. number of i/os in each bank in ep4s100g3, ep4s100g4, and ep4s100g5 devices in the 1932-pin fineline bga package (note 1) note to figure 6?15 : (1) there are two additional pma-only transceiver channels in each transceiver bank. bank 8b 48 bank 7a 48 bank 7b 48 bank 7c 32 21 bank 1c 21 bank 2c 48 bank 3b 48 bank 4a 48 bank 4b 32 bank 4c bank 6c 22 bank 5c 19 41 bank 2a bank 8c 32 bank 8a 48 32 bank 3c 48 bank 3a bank 5a 42 bank 6a 38 bank name number of i/os bank name number of i/os 40 bank 1a bank gxbl2 bank gxbl1 bank gxbl0 4 (1) bank gxbr2 bank gxbr1 bank gxbr0 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) 13 bank 2b bank 5b 12 ep4s100g3 ep4s100g4 ep4s100g5 chapter 6: i/o features in stratix iv devices 6?17 i/o structure ? march 2010 altera corporation stratix iv device handbook volume 1 i/o structure the i/o element (ioe) in stratix iv devices contain a bidirectional i/o buffer and i/o registers to support a complete embedded bidirectional single data rate or ddr transfer. the ioes are located in i/o blocks around the periphery of the stratix iv device. there are up to four ioes per row i/o block and four ioes per column i/o block. the row ioes drive row, column, or direct link interconnects. the column ioes drive column interconnects. the stratix iv bidirectional ioe also supports the following features: figure 6?16. number of i/os in each bank in ep4s40g2, ep4s40g5, ep4s100g2, and ep4s100g5 devices in the 1517-pin fineline bga package (note 1) note to figure 6?16 : (1) there are two additional pma-only transceiver channels in each transceiver bank. bank 8b 24 bank 7a 40 bank 7b 24 bank 7c 32 22 bank 1c 23 bank 2c 24 bank 3b 40 bank 4a 24 bank 4b 32 bank 4c bank 6c 23 bank 5c 23 46 bank 2a bank 8c 32 bank 8a 40 32 bank 3c 40 bank 3a bank 5a 46 bank 6a 44 bank name number of i/os bank name number of i/os 43 bank 1a bank gxbl2 bank gxbl1 bank gxbl0 4 (1) bank gxbr2 bank gxbr1 bank gxbr0 4 (1) 4 (1) 4 (1) 4 (1) 4 (1) ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g5 6?18 chapter 6: i/o features in stratix iv devices i/o structure stratix iv device handbook volume 1 ? march 2010 altera corporation on-chip series termination without calibration on-chip parallel termination with calibration on-chip differential termination pci clamping diode i/o registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output-enable (oe) path for handling the oe signal to the output buffer. these registers allow faster source-synchronous register-to-register transfers and resynchronization. the input path consists of the ddr input registers, alignment and synchronization registers, and hdr. you can bypass each block of the input path. the output and oe paths are divided into output or oe registers, alignment registers, and hdr blocks. you can bypass each block of the output and oe paths. figure 6?17 shows the stratix iv ioe structure. f for more information about i/o registers and how they are used for memory applications, refer to the external memory interfaces chapter. figure 6?17. stratix iv ioe structure (note 1) , (2) notes to figure 6?17 : (1) the d3_0 and d3_1 delays have the same available settings in the quartus ii software. (2) one dynamic oct control is available per dq/dqs group. 2 oe from core 4 open drain on-chip termination bus-hold circuit programmable current strength and slew rate control pci clamp v ccio v ccio programmable pull-up resistor half data rate block alignment registers half data rate block write data from core alignment registers 4 half data rate block alignment and synchronization registers prn dq prn dq prn dq prn dq prn dq oe register oe register output register output register clkout to core to core d5, d6 delay input register prn d q input register prn d q input register clkin d5, d6 delay read data to core from oct calibration block d2 delay d3_0 delay d3_1 delay d1 delay output buffer input buffer d5_oct d6_oct firm core dqs logic block dynamic oct control (2) d4 delay dqs cqn chapter 6: i/o features in stratix iv devices 6?19 i/o structure ? march 2010 altera corporation stratix iv device handbook volume 1 3.3-v i/o interface stratix iv i/o buffers support 3.3-v i/o standards. you can use them as transmitters or receivers in your system. the output high voltage (v oh ), output low voltage (v ol ), input high voltage (v ih ), and input low voltage (v il ) levels meet the 3.3-v i/o standards specifications defined by eia/jedec standard jesd8-b with margin when the stratix iv v ccio voltage is powered by 3.0 v. to ensure device reliability and proper op eration, when interfacing with a 3.3-v i/o system using stratix iv devices, ensure that you do not violate the absolute maximum ratings of the devices. altera recommends performing ibis simulation to determine that the overshoot and undershoot voltages are within the guidelines. when using the stratix iv device as a transmitter, you can use slow slew rate and series termination to limit overshoot and undershoot at the i/o pins, but they are not required. transmission line effects that cause large voltage deviations at the receiver are associated with an impedance mismatch between the driver and the transmission lines. by matching the impedance of the driver to the characteristic impedance of the transmission line, you can significantly reduce overshoot voltage. you can use a series termination resistor placed physically close to the driver to match the total driver impedance to the transmission line impedance. stratix iv devices support series oct for all lvttl and lvcmos i/o standards in all i/o banks. when using the stratix iv device as a receiver, you can use a clamping diode (on-chip or off-chip) to limit overshoot, though this is not required. stratix iv devices provide an optional on-chip pci-clamping diode for column i/o pins. you can use this diode to protect the i/o pins against overshoot voltage. the 3.3-v i/o standard is supported using bank supply voltage (v ccio ) at 3.0 v. in this method, the clamping diode (on-chip or off-chip), when enabled, can sufficiently clamp overshoot voltage to within the dc and ac input voltage specifications. the clamped voltage can be expressed as the sum of the supply voltage (v ccio ) and the diode forward voltage. f r r fr r w vr r r rfr dc and switching characteristics chapter. external memory interfaces in addition to the i/o registers in each ioe, stratix iv devices also have dedicated registers and phase-shift circuitry on all i/o banks for interfacing with external memory interfaces. f r r fr r r rfc rfr external memory interfaces chapter . high-speed differential i/o with dpa support stratix iv devices have the following dedicated circuitry for high-speed differential i/o support: 6?20 chapter 6: i/o features in stratix iv devices i/o structure stratix iv device handbook volume 1 ? march 2010 altera corporation data realignment dynamic phase aligner (dpa) synchronizer (fifo buffer) phase-locked loops (plls) f for more information about dpa support, refer to the high-speed differential i/o interfaces and dpa in stratix iv devices chapter. current strength the output buffer for each stratix iv device i/o pin has a programmable current strength control for certain i/o standards. use programmable current strength to mitigate the effects of high signal attenuation due to a long transmission line or a legacy backplane. the lvttl, lvcmos, sstl, and hstl standards have several levels of current strength that you can control. table 6?3 lists the programmable current strength for stratix iv devices. tab le 6 ?3 . programmable current strength (note 1) , (2) i/o standard i oh / i ol current strength setting (ma) for column i/o pins i oh / i ol current strength setting (ma) for row i/o pins 3.3-v lvttl 16, 12, 8, 4 12, 8, 4 3.3-v lvcmos 16, 12, 8, 4 8, 4 2.5-v lvcmos 16, 12, 8, 4 12, 8, 4 1.8-v lvcmos 12, 10, 8, 6, 4, 2 8, 6, 4, 2 1.5-v lvcmos 12, 10, 8, 6, 4, 2 8, 6, 4, 2 1.2-v lvcmos 8, 6, 4, 2 4, 2 sstl-2 class i 12, 10, 8 12, 8 sstl-2 class ii 16 16 sstl-18 class i 12, 10, 8, 6, 4 12, 10, 8, 6, 4 sstl-18 class ii 16, 8 16, 8 sstl-15 class i 12, 10, 8, 6, 4 8, 6, 4 sstl-15 class ii 16, 8 ? hstl-18 class i 12, 10, 8, 6, 4 12, 10, 8, 6, 4 hstl-18 class ii 16 16 hstl-15 class i 12, 10, 8, 6, 4 8, 6, 4 hstl-15 class ii 16 ? hstl-12 class i 12, 10, 8, 6, 4 8, 6, 4 hstl-12 class ii 16 ? notes to ta bl e 6? 3 : (1) the default setting in the quartus ii software is 50- oct r s without calibration for all non-voltage reference and hstl and sstl class i i/o standards. the default setting is 25- oct r s without calibration for hstl and sstl class ii i/o standards. (2) the 3.3-v lvttl and 3.3-v lvcmos are supported using v ccio and v ccpd at 3.0 v. chapter 6: i/o features in stratix iv devices 6?21 i/o structure ? march 2010 altera corporation stratix iv device handbook volume 1 1 altera recommends performing ibis or spice simulations to determine the best current strength setting for your specific application. slew rate control the output buffer for each stratix iv device regular- and dual-function i/o pin has a programmable output slew-rate control that you can configure for low-noise or high-speed performance. a faster slew rate provides high-speed transitions for high-performance systems. a slower slew rate can help reduce system noise, but adds a nominal delay to the rising and falling edges. each i/o pin has an individual slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis. 1 you cannot use the programmable slew rate feature when using oct r s . the quartus ii software allows four settings for programmable slew rate control?0, 1, 2, and 3?where 0 is slow slew rate and 3 is fast slew rate. figure 6?4 lists the default slew rate settings from the quartus ii software. you can use faster slew rates to improve the available timing margin in memory-interface applications or when the output pin has high-capacitive loading. 1 altera recommends performing ibis or spice simulations to determine the best slew rate setting for your specific application. tab le 6 ?4 . default slew rate settings i/o standard slew rate option default slew rate 1.2-v, 1.5-v, 1.8-v, 2.5-v lvcmos, and 3.3-v lvttl/lvcmos 0, 1, 2, 3 3 sstl-2, sstl-18, sstl-15, hstl-18, hstl-15, and hstl-12 0, 1, 2, 3 3 3.0-v pci/pci-x 0, 1, 2, 3 3 lvds_e_1r, mini-lvds_e_1r, and rsds_e_1r 0, 1, 2, 3 3 lvds_e_3r, mini-lvds_e_3r, and rsds_e_3r 0, 1, 2, 3 3 6?22 chapter 6: i/o features in stratix iv devices i/o structure stratix iv device handbook volume 1 ? march 2010 altera corporation i/o delay the following sections describe programmable ioe delay and programmable output buffer delay. programmable ioe delay the stratix iv device ioe includes programmable delays, shown in figure 6?17 on page 6?18 , that you can activate to ensure zero hold times, minimize setup times, or increase clock-to-output times. each pin can have a different input delay from pin-to-input register or a delay from output register-to-output pin values to ensure that the bus has the same delay going into or out of the device. this feature helps read and time margins because it minimizes the uncertainties between signals in the bus. f r r fr rr cfc rfr dc and switching characteristics chapter. programmable output buffer delay stratix iv devices support delay chains built inside the single-ended output buffer, as shown in figure 6?17 on page 6?18 . the delay chains can independently control the rising and falling edge delays of the output buffer, providing the ability to adjust the output-buffer duty cycle, compensate channel-to-channel skew, reduce simultaneous switching output (sso) noise by deliberately introducing channel-to-channel skew, and improve high-speed memory-interface timing margins. stratix iv devices support four levels of output buffer delay settings. the default setting is no delay . f r r fr rr ffr cfc rfr dc and switching characteristics chapter. open-drain output stratix iv devices provide an optional open-drain output (equivalent to an open collector output) for each i/o pin. when configured as open drain, the logic value of the output is either high-z or 0. typically, an external pull-up resistor is required to provide logic high. bus hold each stratix iv device i/o pin provides an optional bus-hold feature. bus-hold circuitry can weakly hold the signal on an i/o pin at its last-driven state. because the bus-hold feature holds the last-driven state of the pin until the next input signal is present, you do not need an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated. bus-hold circuitry also pulls non-driven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. you can select this feature individually for each i/o pin. the bus-hold output drives no higher than v ccio to prevent over-driving signals. if you enable the bus-hold feature, you cannot use the programmable pull-up option. disable the bus-hold feature if the i/o pin is configured for differential signals. bus-hold circuitry uses a resistor with a nominal resistance (r bh ) of approximately 7k chapter 6: i/o features in stratix iv devices 6?23 i/o structure ? march 2010 altera corporation stratix iv device handbook volume 1 f for more information about the specific sustaining current driven through this resistor and the overdrive current used to identify the next-driven input level, refer to the dc and switching characteristics chapter. bus-hold circuitry is active only after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. pull-up resistor each stratix iv device i/o pin provides an optional programmable pull-up resistor during user mode. if you enable this feature for an i/o pin, the pull-up resistor (typically 25 k ) weakly holds the i/o to the v ccio level. programmable pull-up resistors are only supported on user i/o pins and are not supported on dedicated configuration pins, jtag pins, or dedicated clock pins. if you enable the programmable pull-up option, you cannot use the bus-hold feature. pre-emphasis stratix iv lvds transmitters support programmable pre-emphasis to compensate for the frequency dependent attenuation of the transmission line. the quartus ii software allows four settings for programmable pre-emphasis. f for more information about programmable pre-emphasis, refer to the high-speed differential i/o interfaces and dpa in stratix iv devices chapter. differential output voltage stratix iv lvds transmitters support programmable v od . the programmable v od settings allow you to adjust output eye height to optimize trace length and power consumption. a higher v od swing improves voltage margins at the receiver end; a smaller v od swing reduces power consumption. the quartus ii software allows four settings for programmable v od . f for more information about programmable v od , refer to the high-speed differential i/o interfaces and dpa in stratix iv devices chapter. multivolt i/o interface the stratix iv architecture supports the multivolt i/o interface feature that allows the stratix iv devices in all packages to interface with systems of different supply voltages. you can connect the vccio pins to a 1.2-, 1.5-, 1.8-, 2.5-, or 3.0-v power supply, depending on the output requirements. the output levels are compatible with systems of the same voltage as the power supply. (for example, when vccio pins are connected to a 1.5-v power supply, the output levels are compatible with 1.5-v systems.) f for more information about pin connection guidelines, refer to the stratix iv device family pin connection guidelines . 6?24 chapter 6: i/o features in stratix iv devices on-chip termination support and i/o termination schemes stratix iv device handbook volume 1 ? march 2010 altera corporation the stratix iv vccpd power pins must be connected to a 2.5- or 3.0-v power supply. using these power pins to supply the pre-driver power to the output buffers increases the performance of the output pins. table 6?5 lists stratix iv multivolt i/o support. on-chip termination support and i/o termination schemes stratix iv devices feature dynamic series and parallel oct to provide i/o impedance matching and termination capabilities. oct maintains signal quality, saves board space, and reduces external component costs. stratix iv devices support: 1 c cfr rr crr r fr ffr tab le 6 ?5 . stratix iv multivolt i/o support (note 1) v ccio (v) (3) input signal (v) output signal (v) 1.2 1.5 1.8 2.5 3.0 3.3 1.2 1.5 1.8 2.5 3.0 3.3 1.2 v ????? v ????? 1.5 ? vv ???? v ???? 1.8 ? vv ????? v ??? 2.5 ??? vv (2) v (2) ??? v ?? 3.0 ??? vvv ???? v ? notes to ta bl e 6? 5 : (1) the pin current may be slightly higher than the default value. you must verify that the driving device?s v ol maximum and v oh minimum voltages do not violate the applicable stratix iv v il maximum and v ih minimum voltage specifications. (2) altera recommends that you use an external clamping diode on the i/o pins when the input signal is 3.0 v or 3.3 v. you have th e option to use an internal clamping diode for column i/o pins. (3) each i/o bank of a stratix iv device has its own vccio pins and supports only one v ccio , either 1.2, 1.5, 1.8, or 3.0 v. the lvds i/o standard is not supported when v ccio is 3.0 v. the lvds input operations are supported when v ccio is 1.2 v, 1.5 v, 1.8 v, or 2.5 v. the lvds output operations are only supported when v ccio is 2.5 v. chapter 6: i/o features in stratix iv devices 6?25 on-chip termination support and i/o termination schemes ? march 2010 altera corporation stratix iv device handbook volume 1 a pair of rup and rdn pins are available in a given i/o bank and are shared for series- and parallel-calibrated termination. the rup and rdn pins share the same v ccio and gnd, respectively, with the i/o bank where they are located. the rup and rdn pins are dual-purpose i/os and function as regular i/os if you do not use the calibration circuit. for calibration, the connections are as follows: rup pin is connected to v ccio through an external 25- r , rdn pin is connected to gnd through an external 25- , , rup pin is connected to v ccio through an external 50- rdn pin is connected to gnd through an external 50- on-chip series (r s ) termination without calibration stratix iv devices support driver-impedance matching to provide the i/o driver with controlled output impedance that closely matches the impedance of the transmission line. as a result, you can significantly reduce reflections. stratix iv devices support on-chip series termination for single-ended i/o standards ( figure 6?18 ). the r s shown in figure 6?18 is the intrinsic impedance of the output transistors. ty p i c a l r s values are 25 , , 50- on-chip series termination setting, thus eliminating the external 25- r r r c 25- on-chip series termination setting (to match the 50- figure 6?18. on-chip series termination without calibration stratix iv driver series termination receiving device v ccio r s r s gnd = 50 z o 6?26 chapter 6: i/o features in stratix iv devices on-chip termination support and i/o termination schemes stratix iv device handbook volume 1 ? march 2010 altera corporation on-chip series termination with calibration stratix iv devices support on-chip series termination with calibration in all banks. the on-chip series termination calibration circuit compares the total impedance of the i/o buffer to the external 25- rup and rdn pins and dynamically enables or disables the transistors until they match. the r s shown in figure 6?19 is the intrinsic impedance of the transistors. calibration occurs at the end of device configuration. when the calibration circuit finds the correct impedance, it powers down and stops changing the characteristics of the drivers. table 6?6 lists the i/o standards that support on-chip series termination with and without calibration. figure 6?19. on-chip series termination with calibration tab le 6 ?6 . selectable i/o standards for on-chip series termination with and without calibration (part 1 of 2) i/o standard on-chip series termination setting row i/o ( ) column i/o ( ) 3.3-v lvttl/lvcmos 50 50 25 25 2.5-v lvcmos 50 50 25 25 1.8-v lvcmos 50 50 25 25 1.5-v lvcmos 50 50 25 1.2-v lvcmos 50 50 25 sstl-2 class i 50 50 sstl-2 class ii 25 25 sstl-18 class i 50 50 sstl-18 class ii 25 25 sstl-15 class i 50 50 stratix iv driver series termination receiving device v ccio r s r s gnd = 50 z o chapter 6: i/o features in stratix iv devices 6?27 on-chip termination support and i/o termination schemes ? march 2010 altera corporation stratix iv device handbook volume 1 left-shift series termination control stratix iv devices support left-shift series termination control. you can use left-shift series termination control to get the calibrated oct r s with half of the impedance value of the external reference resistors connected to the rup and rdn pins. this feature is useful in applications that require both 25- , , rup and rdn pins. you can only use left-shift series termination control for the i/o standards that support 25- 1 fr c f r rc w f r r fr w ff r r fr fc rfr i/o buffer (altiobuf) megafunction user guide . on-chip parallel termination with calibration stratix iv devices support on-chip parallel te rmination with calibration in all banks. on-chip parallel termination with calibration is only supported for input configuration of input and bidirectional pins. output pin configurations do not support on-chip parallel termination with calibration. figure 6?20 shows on-chip parallel termination with calibration. when you use parallel oct, the v ccio of the bank must match the i/o standard of the pin where the parallel oct is enabled. sstl-15 class ii ?2 5 hstl-18 class i 50 50 hstl-18 class ii 25 25 hstl-15 class i 50 50 hstl-15 class ii ?2 5 hstl-12 class i 50 50 hstl-12 class ii ?2 5 tab le 6 ?6 . selectable i/o standards for on-chip series termination with and without calibration (part 2 of 2) i/o standard on-chip series termination setting row i/o ( ) column i/o ( ) 6?28 chapter 6: i/o features in stratix iv devices on-chip termination support and i/o termination schemes stratix iv device handbook volume 1 ? march 2010 altera corporation the on-chip parallel termination calibration circuit compares the total impedance of the i/o buffer to the external 50- rup and rdn pins and dynamically enables or disables the transistors until they match. calibration occurs at the end of device configuration. when the calibration circuit finds the correct impedance, it powers down and stops changing the characteristics of the drivers. table 6?7 lists the i/o standards that support on-chip parallel termination with calibration. expanded on-chip series termination with calibration oct calibration circuits always adjust oct r s to match the external resistors connected to the rup and rdn pin; however, it is possible to achieve oct r s values other than the 25- , , rup and rdn pins accordingly. practically, the oct r s range that stratix iv devices support is limited because of output buffer size and granularity limitations. figure 6?20. on-chip parallel termination with calibration tab le 6 ?7 . selectable i/o standards with on-chip parallel termination with calibration i/o standard on-chip parallel termination setting (column i/o) ( ) on-chip parallel termination setting (row i/o) ( ) sstl-2 class i, ii 50 50 sstl-18 class i, ii 50 50 sstl-15 class i, ii 50 50 hstl-18 class i, ii 50 50 hstl-15 class i, ii 50 50 hstl-12 class i, ii 50 50 differential sstl-2 class i, ii 50 50 differential sstl-18 class i, ii 50 50 differential sstl-15 class i, ii 50 50 differential hstl-18 class i, ii 50 50 differential hstl-15 class i, ii 50 50 differential hstl-12 class i, ii 50 50 transmitter receiver gnd = 50 z o v ccio 100 100 stratix iv oct v ref chapter 6: i/o features in stratix iv devices 6?29 on-chip termination support and i/o termination schemes ? march 2010 altera corporation stratix iv device handbook volume 1 the quartus ii software only allows discrete oct r s calibration settings of 25, 40, 50, and 60 , , 25- oct r s with calibration setting in the quartus ii software to achieve the closest timing. table 6?8 lists expanded oct r s with calibration supported in stratix iv devices. use expanded on-chip series termination with calibration of sstl and hstl for impedance matching to improve signal integrity but do not use it to meet the jedec standard. dynamic on-chip termination stratix iv devices support on and off dynamic termination, both series and parallel, for a bidirectional i/o in all i/o banks. figure 6?21 shows the termination schemes supported in stratix iv devices. dynamic parallel termination is enabled only when the bidirectional i/o acts as a receiver and is disabled when it acts as a driver. similarly, dynamic series termination is enabled only when the bidirectional i/o acts as a driver and is disabled when it acts as a receiver. this feature is useful for terminating any high-performance bidirectional path because signal integrity is optimized depending on the direction of the data. using dynamic oct helps save power because device termination is internal instead of external. termination only switches on during input operation, thus drawing less static power. tab le 6 ?8 . selectable i/o standards with expanded on-chip series termination with calibration range i/o standard expanded oct r s range row i/o ( ) column i/o ( ) 3.3-v lvttl/lvcmos 20?60 20?60 2.5-v lvttl/lvcmos 20?60 20?60 1.8-v lvttl/lvcmos 20?60 20?60 1.5-v lvttl/lvcmos 40?60 20?60 1.2-v lvttl/lvcmos 40?60 20?60 sstl-2 20?60 20?60 sstl-18 20?60 20?60 sstl-15 40?60 20?60 hstl-18 20?60 20?60 hstl-15 40?60 20?60 hstl-12 40?60 20?60 6?30 chapter 6: i/o features in stratix iv devices on-chip termination support and i/o termination schemes stratix iv device handbook volume 1 ? march 2010 altera corporation f for more information about tolerance specifications for oct with calibration, refer to the dc and switching characteristics chapter. lvds input oct (r d ) stratix iv devices support oct for differential lvds input buffers with a nominal resistance value of 100 , as shown in figure 6?22 . differential oct r d can be enabled in row i/o banks when both the v ccio and v ccpd is set to 2.5 v. column i/o banks do not support oct r d. dedicated clock input pairs clk[1,3,8,10][p,n] , pll_l[1,4]_clk[p,n] , and pll_r[1,4]_clk[p,n] on the row i/o banks of stratix iv devices do not support r d termination. f for more information about differential on-chip termination, refer to the high speed differential i/o interfaces and dpa in stratix iv devices chapter . figure 6?21. dynamic parallel oct in stratix iv devices receiver stratix iv oct vccio gnd stratix iv oct transmitter receiver stratix iv oct stratix iv oct transmitter vccio gnd vccio gnd gnd vccio 100 100 100 100 100 100 100 100 100 100 100 100 100 100 50 50 50 50 50 50 = 50 z o = 50 z o figure 6?22. differential input oct transmitter receiver 100 = 50 z o = 50 z o chapter 6: i/o features in stratix iv devices 6?31 oct calibration ? march 2010 altera corporation stratix iv device handbook volume 1 summary of oct assignments table 6?9 lists the oct assignments for the quartus ii software version 9.1 and later. oct calibration stratix iv devices support calibrated on-chip series termination (r s ) and calibrated on-chip parallel termination (r t ) on all i/o pins. you can calibrate the device?s i/o bank with any of the oct calibration blocks available in the device provided the v ccio of the i/o bank with the pins using calibrated oct matches the v ccio of the i/o bank with the calibration block and its associated rup and rdn pins. oct calibration block location table 6?10 and table 6?11 list the location of oct calibration blocks in stratix iv devices. for both tables, the following legend applies: v c w cr c 1 1 11 w rcvr rcvr cr c 1 cr c 1 r tab le 6 ?9 . summary of oct assignments in the quartus ii software assignment name value applies to input termination parallel 50 with calibration input buffers for single-ended and differential hstl/sstl standards differential input buffers for lvds receivers on row i/o banks (1) output termination series 25 without calibration output buffers for single-ended lvttl/lvcmos and hstl/sstl standards as well as differential hstl/sstl standards series 50 without calibration series 25 with calibration series 40 with calibration series 50 with calibration series 60 with calibration note to tab l e 6 ?9 : (1) you can enable differential oct r d in row i/o banks when both v ccio and v ccpd are set to 2.5 v . table 6?10. oct calibration block counts and placement in stratix iv devices (1a through 4c) (part 1 of 2) device pin number of oct blocks bank 1a 1b 1c 2a 2b 2c 3a 3b 3c 4a 4b 4c ep4se230 780 8 v ?x v ?x v ?x v ?x ep4se360 780 8 v ?x v ?x v ?x v ?x 1152 8 v ?x v ?x v xx v xx 6?32 chapter 6: i/o features in stratix iv devices oct calibration stratix iv device handbook volume 1 ? march 2010 altera corporation ep4se530 1152 8 v ?x v ?x v xx v xx 1517 10 v xx v xx v x vv xx 1760 10 v xx v xx v x vv xx ep4se820 1152 8 v ?x v ?x v xx v xx 1517 10 v xx v xx v x vv xx 1760 10 v xx v xx v x vv xx ep4sgx70 780 8 v ?x v ?x v ?x v ?x ep4sgx110 780 8 v ?x v ?x v ?x v ?x 1152 8 v ?x??? v ?x v ?x ep4sgx180 780 8 v ?x v ?x v ?x v ?x 1152 8 v ?x??? v xx v xx 1517 8 v ?x v ?x v xx v xx ep4sgx230 780 8 v ?x v ?x v ?x v ?x 1152 8 v ?x??? v xx v xx 1517 8 v ?x v ?x v xx v xx ep4sgx290 780 8 ?????? v ?x v ?x 1152 8 v ?x??? v xx v xx 1517 8 v ?x v ?x v xx v xx 1760 8 v ?x v ?x v xx v xx 1932 10 v xx v ?x v x vv xx ep4sgx360 780 8 ?????? v ?x v ?x 1152 8 v ?x??? v xx v xx 1517 8 v ?x v ?x v xx v xx 1760 8 v ?x v ?x v xx v xx 1932 10 v xx v ?x v x vv xx ep4sgx530 1152 8 v ?x??? v x vv xx 1517 10 v ?x v ?x v x vv xx 1760 10 v ?x v ?x v x vv xx 1932 10 v ?x v xx v x vv xx ep4s40g2 1517 8 v ?x v ?x v xx v xx ep4s40g5 1517 10 v ?x v ?x v x vv xx ep4s100g2 1517 8 v ?x v ?x v xx v xx ep4s100g3 1932 10 v ?x v xx v x vv xx ep4s100g4 1932 10 v ?x v xx v x vv xx ep4s100g5 1517 10 v ?x v ?x v x vv xx 1932 10 v ?x v xx v x vv xx table 6?10. oct calibration block counts and placement in stratix iv devices (1a through 4c) (part 2 of 2) device pin number of oct blocks bank 1a 1b 1c 2a 2b 2c 3a 3b 3c 4a 4b 4c chapter 6: i/o features in stratix iv devices 6?33 oct calibration ? march 2010 altera corporation stratix iv device handbook volume 1 table 6?11 lists the oct calibration blocks in banks 5a through 8c. table 6?11. oct calibration block counts and placement in stratix iv devices (5a through 8c) device pin number of oct blocks bank 5a 5b 5c 6a 6b 6c 7a 7b 7c 8a 8b 8c ep4se230 780 8 v ?x v ?x v ?x v ?x ep4se360 780 8 v ?x v ?x v ?x v ?x 1152 8 v ?x v ?x v xx v xx ep4se530 1152 8 v ?x v ?x v xx v xx 1517 10 v xx v xx v xx v x v 1760 10 v xx v xx v xx v x v ep4se820 1152 8 v ?x v ?x v xx v xx 1517 10 v xx v xx v xx v x v 1760 10 v xx v xx v xx v x v ep4sgx70 780 8 ?????? v ?x v ?x ep4sgx110 780 8 ?????? v ?x v ?x 1152 8 ? ? ? v ?x v ?x v ?x ep4sgx180 780 8 ?????? v ?x v ?x 1152 8 ? ? ? v ?x v xx vv x 1517 8 v ?x v ?x v xx v xx ep4sgx230 780 8 ?????? v ?x v ?x 1152 8 ? ? ? v ?x v xx vv x 1517 8 v ?x v ?x v xx v xx ep4sgx290 780 8 ?????? v ?x v ?x 1152 8 ? ? ? v ?x v xx v xx 1517 8 v ?x v ?x v xx v xx 1760 8 v ?x v ?x v xx v xx 1932 10 v ?x v xx v xx v x v ep4sgx360 780 8 ?????? v ?x v ?x 1152 8 ? ? ? v ?x v xx v xx 1517 8 v ?x v ?x v xx v xx 1760 8 v ?x v ?x v xx v xx 1932 10 v ?x v xx v xx v x v ep4sgx530 1152 8 ? ? ? v ?x v xx v x v 1517 10 v ?x v ?x v xx v x v 1760 10 v ?x v ?x v xx v x v 1932 10 v xx v ?x v xx v x v ep4s40g2 1517 8 v ?x v ?x v xx v xx ep4s40g5 1517 10 v ?x v ?x v xx v x v ep4s100g2 1517 8 v ?x v ?x v xx v xx ep4s100g3 1932 10 v xx v ?x v xx v x v ep4s100g4 1932 10 v xx v ?x v xx v x v ep4s100g5 1517 10 v ?x v ?x v xx v x v 1932 10 v xx v ?x v xx v x v 6?34 chapter 6: i/o features in stratix iv devices oct calibration stratix iv device handbook volume 1 ? march 2010 altera corporation sharing an oct calibration block on multiple i/o banks an oct calibration block has the same v ccio as the i/o bank that contains the block. oct r s calibration is supported on all i/o banks with different v ccio voltage standards, up to the number of available oct calibration blocks. you can configure the i/o banks to receive calibration codes from any oct calibration block with the same v ccio . all i/o banks with the same v ccio can share one oct calibration block, even if that particular i/o bank has an oct calibration block. for example, figure 6?23 shows a group of i/o banks that has the same v ccio voltage. if a group of i/o banks has the same v ccio voltage, you can use one oct calibration block to calibrate the group of i/o banks placed around the periphery. because 3b, 4c, 6c, and 7b have the same v ccio as bank 7a, you can calibrate all four i/o banks (3b, 4c, 6c, and 7b) with the oct calibration block (cb7) located in bank 7a. you can enable this by serially shifting out oct r s calibration codes from the oct calibration block located in bank 7a to the i/o banks located around the periphery. 1 c cr c r cr c w c cr c r vw f c crr rvr vw fr f c c rc rr fr w rcvr rcvr cr c figure 6?23. example of calibrating multiple i/o banks with one shared oct calibration block stratix iv bank 8a bank 8c bank 8b bank 7b bank 7c bank 1a bank 1c bank 1b bank 2a bank 2b bank 2c bank 3a bank 3c bank 3b bank 4a bank 4b bank 4c bank 6a bank 6c bank 6b bank 5a bank 5b bank 5c bank 7a cb 7 i/o bank with the same v ccio i/o bank with different v ccio chapter 6: i/o features in stratix iv devices 6?35 oct calibration ? march 2010 altera corporation stratix iv device handbook volume 1 oct calibration block modes of operation stratix iv devices support oct r s and oct r t on all i/o banks. the calibration can occur in either power-up or user mode. power-up mode in power-up mode, oct calibration is automatically performed at power up. calibration codes are shifted to selected i/o buffers before transitioning to user mode. user mode in user mode, the octusrclk, enaoct , nclrusr , and enaser[9..0] signals are used to calibrate and serially transfer calibration codes from each oct calibration block to any i/o. table 6?12 lists the user-controlled calibration block signal names and their descriptions. figure 6?24 shows the flow of the user signal. when enaoct is 1, all oct calibration blocks are in calibration mode; when enaoct is 0, all oct calibration blocks are in serial data transfer mode. the octusrclk clock frequency must be 20 mhz or less. 1 r r r f octusrclk. table 6?12. oct calibration block ports for user control signal name description octusrclk clock for oct block. enaoct enable oct termination (generated by user ip). enaser[9..0] when enoct = 0, each signal enables the oct serializer for the corresponding oct calibration block. when enaoct = 1, each signal enables oct calibration for the corresponding oct calibration block. s2pena_< bank# > serial-to-parallel load enable per i/o bank. nclrusr clear user. 6?36 chapter 6: i/o features in stratix iv devices oct calibration stratix iv device handbook volume 1 ? march 2010 altera corporation figure 6?24 does not show transceiver banks and transceiver calibration blocks. oct calibration figure 6?25 shows user mode signal-timing waveforms. to calibrate oct block[n] (where n is a calibration block number), you must assert enaoct one cycle before asserting enaser[n] . also, nclrusr must be set to low for one octusrclk cycle before the enaser[n] signal is asserted. assert the enaser[n] signals for 1000 octusrclk cycles to perform octrs and octrt calibration. you can de-assert enaoct one clock cycle after the last enaser is de-asserted. serial data transfer after you complete calibration, you must serially shift out the 28-bit oct calibration codes (14-bit oct r s and 14-bit oct r t ) from each oct calibration block to the corresponding i/o buffers. only one oct calibration block can send out the codes at any time by asserting only one enaser[n] signal at a time. after you de-assert enaoct , wait at least one octusrclk cycle to enable any enaser[n] signal to begin serial transfer. to shift the 28-bit code from the oct calibration block[n], you must assert enaser[n] for exactly 28 octusrclk cycles. between two consecutive asserted enaser signals, there must be at least one octusrclk cycle gap. ( figure 6?25 ). figure 6?24. signals used for user mode calibration bank 8a bank 8c bank 8b bank 7b bank 7c bank 1a bank 1c bank 1b bank 2a bank 2b bank 2c bank 3a bank 3c bank 3b bank 4a bank 4b bank 4c bank 6a bank 6c bank 6b bank 5a bank 5b bank 5c bank 7a stratix iv core s2pena_1c s2pena_6c s2pena_4c cb0 cb9 cb1 cb2 cb4 cb3 cb5 cb6 cb7 cb8 enaoct, nclrusr, octusrclk, enaser[n] chapter 6: i/o features in stratix iv devices 6?37 oct calibration ? march 2010 altera corporation stratix iv device handbook volume 1 after calibrated codes are shifted in serially to each i/o bank, the calibrated codes must be converted from serial to parallel format before being used in the i/o buffers. figure 6?25 shows the s2pena signals that can be asserted at any time to update the calibration codes in each i/o bank. all i/o banks that received the codes from the same oct calibration block can have s2pena asserted at the same time, or at a different time, even while another oct calibration block is calibrating and serially shifting codes. the s2pena signal is asserted one octusrclk cycle after enaser is de-asserted for at least 25 ns. you cannot use i/os for transmitting or receiving data when their s2pena is asserted for parallel codes transfer. example of using multiple oct calibration blocks figure 6?26 shows a signal timing waveform for two oct calibration blocks doing r s and r t calibration. calibration blocks can start calibrating at different times by asserting the enaser signals at different times. enaoct must remain asserted while any calibration is ongoing. you must set nclrusr low for one octusrclk cycle before each enaser[n] signal is asserted. in figure 6?26 , when you set nclrusr to 0 for the second time to initialize oct calibration block 0, this does not affect oct calibration block 1, whose calibration is already in progress. figure 6?25. oct user mode signal?timing waveform for one oct block note to figure 6?25 : (1) t s2p octusrclk nclrusr enaoct enaser0 calibration phase s2pena_1a 28 octusrclk cycles t s2p (1) 1000 octusrclk cycles figure 6?26. oct user-mode signal timing waveform for two oct blocks notes to figure 6?26 : (1) ts2p (2) s2pena_1a is asserted in bank 1a for calibration block 0. (3) s2pena_2a is asserted in bank 2a for calibration block 1. octusrclk enaoct nclrusr enaser0 enaser1 s2pena_1a (2) s2pena_2a (3) ts2p (1) ts2p (1) calibration phase 1000 cycles octusrclk 1000 cycles octusrclk 28 cycles octusrclk 28 cycles octusrclk 6?38 chapter 6: i/o features in stratix iv devices termination schemes for i/o standards stratix iv device handbook volume 1 ? march 2010 altera corporation r s calibration if only r s calibration is used for an oct calibration block, its corresponding enaser signal only requires to be asserted for 240 octusrclk cycles. 1 r enaser signal for 28 octusrclk cycles for serial transfer. termination schemes for i/o standards the following sections describe the different termination schemes for the i/o standards used in stratix iv devices. single-ended i/o standards termination voltage-referenced i/o standards require both an input reference voltage, v ref , and a termination voltage, v tt . the reference voltage of the receiving device tracks the termination voltage of the transmitting device. chapter 6: i/o features in stratix iv devices 6?39 termination schemes for i/o standards ? march 2010 altera corporation stratix iv device handbook volume 1 figure 6?27 and figure 6?28 show the details of sstl and hstl i/o termination on stratix iv devices. 1 r vc c r r r r fr rfr c r figure 6?27. sstl i/o standard termination sstl class i sstl class ii external on-board termination oct transmit oct receive oct in bi- directional pins v tt 50 25 50 v tt 50 25 50 v tt 50 transmitter transmitter receiver receiver v tt 50 50 8 50 transmitter receiver stratix iv series oct 50 v tt 50 50 v tt 50 transmitter receiver 25 stratix iv series oct v ccio 100 25 50 transmitter receiver stratix iv parallel oct 100 v ccio 100 25 50 8 transmitter receiver stratix iv parallel oct 100 v tt 50 v ccio 100 50 stratix iv 100 v ccio 100 100 stratix iv v ref v ref v ref v ref v ref v ref v ref termination series oct 50 series oct 50 v ccio 100 50 stratix iv 100 v ccio 100 100 stratix iv series oct 25 series oct 25 6?40 chapter 6: i/o features in stratix iv devices termination schemes for i/o standards stratix iv device handbook volume 1 ? march 2010 altera corporation differential i/o standards termination stratix iv devices support differential sstl-18 and sstl-2, differential hstl-18, hstl-15, hstl-12, lvds, lvpecl, rsds, and mini-lvds. figure 6?29 through figure 6?35 show the details of various differential i/o terminations on these devices. 1 ffr r r ffr w w c rr vr figure 6?28. hstl i/o standard termination hstl class i hstl class ii external on-board termination oct transmit oct receive oct in bi- directional pins v tt 50 50 v tt 50 50 v tt 50 transmitter transmitter receiver receiver v tt 50 50 transmitter receiver v tt 50 50 v tt 50 transmitter receiver v ccio 100 50 transmitter receiver stratix iv parallel oct 100 v ccio 100 50 transmitter receiver stratix iv parallel oct 100 v tt 50 v ccio 100 50 stratix iv 100 v ccio 100 100 stratix iv stratix iv series oct 50 stratix iv series oct 25 v ref v ref v ref v ref v ref v ref termination series oct 50 series oct 50 v ccio 100 50 8 stratix iv 100 v ccio 100 100 stratix iv series oct 25 series oct 25 chapter 6: i/o features in stratix iv devices 6?41 termination schemes for i/o standards ? march 2010 altera corporation stratix iv device handbook volume 1 figure 6?29. differential sstl i/o standard termination figure 6?30. differential hstl i/o standard termination differential sstl class i differential sstl class ii external on-board termination oct transmitter receiver 50 50 50 50 v tt v tt 25 25 transmitter receiver 50 50 50 50 v tt v tt 25 25 50 50 v tt v tt 50 50 transmitter receiver z 0 = 50 z 0 = 50 100 100 100 100 v ccio v ccio 25 series oct gnd gnd v tt v tt differential sstl class ii transmitter receiver z 0 = 50 z 0 = 50 100 100 100 100 v ccio v ccio 50 series oct gnd gnd differential sstl class i differential hstl class i differential hstl class ii external on-board termination oct transmitter receiver 50 50 50 50 v tt v tt transmitter receiver 50 50 50 50 v tt v tt 50 50 v tt v tt termination transmitter receiver z 0 = 50 z 0 = 50 100 100 100 100 v ccio v ccio 50 series oct gnd gnd differential hstl class i 50 50 transmitter receiver z 0 = 50 z 0 = 50 100 100 100 100 v ccio v ccio 25 series oct gnd gnd v tt v tt differential hstl class ii 6?42 chapter 6: i/o features in stratix iv devices termination schemes for i/o standards stratix iv device handbook volume 1 ? march 2010 altera corporation lvds the lvds i/o standard is a differential high-speed, low-voltage swing, low-power, general-purpose i/o interface standard. in stratix iv devices, the lvds i/o standard requires a 2.5-v v ccio level. the lvds input buffer requires 2.5-v v ccpd . use this standard in applications requiring high-bandwidth data transfer, such as backplane drivers and clock distribution. lvds requires a 100- ffr r rr vc c ffr r r 1 w r c ffr rr v rw figure 6?31. lvds i/o standard termination (note 1) notes to figure 6?31 : (1) for lvds output with a three-resistor network, the r s and r p values are 120 and 170 , respectively. for lvds output with a one-resistor network, the r p value is 120 . (2) side i/o banks support true lvds output buffers. (3) column and side i/o banks support lvds_e_1r and lvds_e_3r i/o standards using two single-ended output buffers. differential outputs differential inputs 100 single-ended outputs differential inputs 100 rp external resistor single-ended outputs differential inputs 100 rp external resistor rs rs stratix iv oct stratix iv oct stratix iv oct differential outputs differential inputs 100 external on-board termination oct receive (true lvds output) (2) termination lvds 50 50 50 50 50 50 50 50 oct receive (single-ended lvds output with one-resistor network, lvds_e_1r) (3) oct receive (single-ended lvds output with three-resistor network, lvds_e_3r) (3) 1 inch 1 inch chapter 6: i/o features in stratix iv devices 6?43 termination schemes for i/o standards ? march 2010 altera corporation stratix iv device handbook volume 1 differential lvpecl in stratix iv devices, the lvpecl i/o standard is supported on input clock pins on column and row i/o banks. lvpecl output operation is not supported in stratix iv devices. lvds input buffers are used to support lvpecl input operation. ac coupling is required when the lvpecl common-mode voltage of the output buffer is higher than the lvpecl input common-mode voltage. figure 6?32 shows the ac-coupled termination scheme. the 50- rsds stratix iv devices support the rsds output standard with data rates up to 230 mbps using lvds output buffer types. for transmitters, use two single-ended output buffers with the external one- or three-resistor networks in the column i/o bank, as shown in figure 6?34 . the one-resistor topology is for data rates up to 200 mbps. the three-resistor topology is for data rates above 200 mbps. the row i/o banks support rsds output using true lvds output buffers without an external resistor network. figure 6?32. lvpecl ac-coupled termination figure 6?33. lvpecl dc-coupled termination lvpecl output buffer stratix iv lvpecl input buffer 50 = 50 = 50 0.1 f 0.1 f 50 v icm z o z o lvpecl output buffer stratix iv lvpecl input buffer 100 = 50 z o = 50 z o 6?44 chapter 6: i/o features in stratix iv devices termination schemes for i/o standards stratix iv device handbook volume 1 ? march 2010 altera corporation a resistor network is required to attenuate the lvds output-voltage swing to meet rsds specifications. you can modify the three-resistor network values to reduce power or improve noise margin. the resistor values chosen must satisfy equation 6?1 . 1 r rc rfr v c rr v rr f r r fr r rfr rsds specification from the national semiconductor website at www.national.com . mini-lvds stratix iv devices support the mini-lvds output standard with data rates up to 340 mbps using lvds output buffer types. for transmitters, use two single-ended output buffers with external one- or three-resistor networks, as shown in figure 6?35 . the one-resistor topology is for data rates up to 200 mbps. the three-resistor topology is for data rates above 200 mbps. the row i/o banks support mini-lvds output using true lvds output buffers without an external resistor network. figure 6?34. rsds i/o standard termination (note 1) note to figure 6?34 : (1) the r s and r p values are pending characterization. 50 50 r s r s r p transmitter receiver 1 inch 50 50 r p transmitter 1 inch 50 50 100 r p transmitter receiver 1 inch 50 50 r s r s r p transmitter receiver 1 inch termination external on-board termination oct one-resistor network (rsds_e_1r) three-resistor network (rsds_e_3r) 100 receiver stratix iv oct stratix iv oct 100 100 equation 6?1. r s r p 2 ------ - r s r p 2 ------ - + -------------------- -50 = chapter 6: i/o features in stratix iv devices 6?45 design considerations ? march 2010 altera corporation stratix iv device handbook volume 1 a resistor network is required to attenuate the lvds output voltage swing to meet the mini-lvds specifications. you can modify the three-resistor network values to reduce power or improve noise margin. the resistor values chosen must satisfy equation 6?1 on page 6?44 . 1 r rc rfr v c rr v rr f r r fr r mini-lvds specification from the texas instruments website at www.ti.com . design considerations although stratix iv devices feature various i/o capabilities for high-performance and high-speed system designs, there are several other design considerations that require your attention to ensure the success of your designs. i/o bank restrictions each i/o bank can simultaneously support multiple i/o standards. the following sections provide guidelines for mixing non-voltage-referenced and voltage-referenced i/o standards in stratix iv devices. non-voltage-referenced standards each i/o bank of a stratix iv device has its own vccio pins and supports only one v ccio , either 1.2, 1.5, 1.8, 2.5, or 3.0 v. an i/o bank can simultaneously support any number of input signals with different i/o standard assignments if it meets the v ccio and v ccpd requirement, as shown in table 6?2 on page 6?3 . figure 6?35. mini-lvds i/o standard termination (note 1) note to figure 6?35 : (1) the r s and r p values are pending characterization. 50 50 r s r s r p transmitter receiver 1 inch 50 r p transmitter receiver 1 inch 50 50 r p transmitter receiver 1 inch 50 50 r s r s r p transmitter receiver 1 inch termination external on-board termination oct one-resistor network (mini-lvds_e_1r) three-resistor network (mini-lvds_e_3r) 50 100 stratix iv oct stratix iv oct 100 100 100 6?46 chapter 6: i/o features in stratix iv devices design considerations stratix iv device handbook volume 1 ? march 2010 altera corporation for output signals, a single i/o bank supports non-voltage-referenced output signals that are driving at the same voltage as v ccio . because an i/o bank can only have one v ccio value, it can only drive out that one value for non-voltage-referenced signals. for example, an i/o bank with a 2.5-v v ccio setting can support 2.5-v standard inputs and outputs as well as 3.0-v lvcmos inputs (but not output or bidirectional pins). voltage-referenced standards to accommodate voltage-referenced i/o standards, each stratix iv device?s i/o bank supports multiple vref pins feeding a common v ref bus. the number of available vref pins increases as device density increases. if these pins are not used as vref pins, they cannot be used as generic i/o pins and must be tied to v ccio or gnd. each bank can only have a single v ccio voltage level and a single v ref voltage level at a given time. an i/o bank featuring single-ended or differential standards can support voltage-referenced standards if all voltage-referenced standards use the same v ref setting. for performance reasons, voltage-referenced input standards use their own v ccpd level as the power source. this feature allows you to place voltage-referenced input signals in an i/o bank with a v ccio of 2.5 v or below. for example, you can place hstl-15 input pins in an i/o bank with 2.5-v v ccio . however, the voltage-referenced input with parallel oct enabled requires the v ccio of the i/o bank to match the voltage of the input standard. voltage-referenced bidirectional and output signals must be the same as the i/o bank?s v ccio voltage. for example, you can only place sstl-2 output pins in an i/o bank with a 2.5-v v ccio . mixing voltage-referenced and non-voltage-referenced standards an i/o bank can support both voltage-referenced and non-voltage-referenced pins by applying each of the rule sets individually. for example, an i/o bank can support sstl-18 inputs and 1.8-v inputs and outputs with a 1.8-v v ccio and a 0.9-v v ref . similarly, an i/o bank can support 1.5-v standards, 1.8-v inputs (but not outputs), and hstl and hstl-15 i/o standards with a 1.5-v v ccio and 0.75-v v ref . chapter 6: i/o features in stratix iv devices 6?47 document revision history ? march 2010 altera corporation stratix iv device handbook volume 1 document revision history table 6?13 shows the revision history for this chapter. table 6?13. document revision history (part 1 of 2) date and document version changes made summary of changes march 2010 v3.1 updated tab le 6 ?2 and tab le 6 ?5 . updated figure 6?18 , figure 6?19, figure 6?27 , figure 6?28 , and figure 6?31 . added the ?summary of oct assignments? section. added a note to the ?sharing an oct calibration block on multiple i/o banks? section. updated the ?oct calibration? section. minor text edits. ? november 2009 v3.0 updated table 6?2, table 6?4, table 6?6, table 6?9, and table 6?10. updated figure 6?1, figure 6?2, figure 6?4, figure 6?5, figure 6?6, figure 6?8, figure 6?9, figure 6?10, figure 6?11, figure 6?12, figure 6?13, and figure 6?31. added table 6?8. added figure 6?7, figure 6?14, figure 6?15, and figure 6?16. added ?left-shift series termination control? and ?expanded on-chip series termination with calibration? sections. updated ?multivolt i/o interface?, ?rsds?, ?mini-lvds?, and ?non- voltage-referenced standards? sections. deleted figure 6-5: number of i/os in each bank in ep4se290 and ep4se360 in the 1517-pin fineline bga package. minor text edits. ? june 2009 v2.3 added introductory sentences to improve search ability. removed the conclusion section. ? april 2009 v2.2 updated figure 6?2. updated table 6?8 and table 6?9. deleted figure 6-14. ? march 2009 v2.1 updated table 6?1, table 6?2,table 6?3, table 6?4, table 6?6, table 6?8, and table 6?9. updated figure 6?2, figure 6?7, figure 6?8, figure 6?9, figure 6?10, figure 6?11, and figure 6?12. added figure 6?14. removed equation 6?2. removed ?referenced documents? section. ? 6?48 chapter 6: i/o features in stratix iv devices document revision history stratix iv device handbook volume 1 ? march 2010 altera corporation november 2008 v2.0 updated ?modular i/o banks? on page 6?7. updated figure 6?3. updated figure 6?21. made minor editorial changes. ? may 2008 v1.0 initial release. ? table 6?13. document revision history (part 2 of 2) date and document version changes made summary of changes ? march 2010 altera corporation stratix iv device handbook volume 1 7. external memory interfaces in stratix iv devices this chapter describes external memory interfaces available with the stratix ? ? , , , , , +, , , , , , , , , , f r r fr r r rfrc cfc r fr rfr external memory interface handbook . siv51007-3.1 7?2 chapter 7: external memory interfaces in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?1 shows an overview of the memory interface data path that uses all the stratix iv i/o element (ioe) features. memory interfaces use stratix iv device features such as delay-locked loops (dlls), dynamic oct control, read- and write-leveling circuitry, and i/o features such as oct, programmable input delay chains, programmable output delay, slew rate adjustment, and programmable drive strength. f r r fr fr rfr i/o features in stratix iv devices chapter. the altmemphy megafunction instantiates a phase-locked loop (pll) and pll reconfiguration logic to adjust the phase shift based on vt variation. f r r fr r rfr clock networks and plls in stratix iv devices chapter. for more information about the altmemphy megafunction, refer to the external memory phy interface (altmemphy) (nonafi) megafunction user guide . figure 7?1. external memory interface data path overview (note 1) , (2) notes to figure 7?1 : (1) you can bypass each register block. (2) the blocks used for each memory interface may differ slightly. the shaded blocks are part of the stratix iv ioe. (3) these signals may be bidirectional or unidirectional, depending on the memory standard. when bidirectional, the signal is ac tive during both read and write operations. ddr output and output enable registers memory stratix iv fpga dll ddr input registers alignment & synchronization registers half data rate output registers clock management & reset 4n 2n n n 2n 4n dpram (2) dq (read) (3) dq (write) (3) dqs logic block dqs (read) (3) half data rate input registers 2n half data rate output registers 42 dqs (write) (3) resynchronization clock alignment clock dqs write clock half-rate resynchronization clock half-rate clock alignment registers alignment registers 2n 2 dq write clock dqs enable circuit postamble control circuit postamble enable postamble clock ddr output and output enable registers chapter 7: external memory interfaces in stratix iv devices 7?3 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 memory interfaces pin support a typical memory interface requires data (d, q, or dq), data strobe (dqs/cq and dqsn/cqn), address, command, and clock pins. some memory interfaces use data mask (dm, bwsn, or nwsn) pins to enable write masking and qvld pins to indicate that the read data is ready to be captured. this section describes how stratix iv devices support all these different pins. 1 f v r cc r c r r f v w cc r c f r f r r fr cc rfr stratix iv device family pin connection guidelines . table 7?1 lists the pin connections between a stratix iv device and an external memory device. tab le 7 ?1 . stratix iv memory interface pin utilization (part 1 of 2) pin description memory standard stratix iv pin utilization read data all dq write data all dq (1) parity, dm, bwsn, nwsn, qvld, ecc all dq (1) , (2) , (3) read data strobes/clocks ddr3 sdram ddr2 sdram (with differential dqs signaling) (5) rldram ii differential dqs/dqsn (also used as a write data clock) ddr2 sdram (with single-ended dqs signaling) (5) ddr sdram single-ended dqs (also used as a write data clock) qdr ii+ sram qdr ii sram complementary cq/cqn write data clocks qdr ii+ sram (6) qdr ii sram (6) rldram ii separate i/o (sio) any dqs and dqsn pin pairs associated with the dq groups used for the write data pins (1) rldram ii common i/o (cio) (7) any dq pin with diffout capability within the same dqs/dq group or adjacent group as the read data (q) pins, or in the same bank as the address and command pins 7?4 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation memory clocks (for address and command) ( 8 ) ddr3 sdram with leveling any unused dq or dqs pins with diffio_rx capability for the mem_clk[0] and mem_clk_n[0] signals (4) any unused dq or dqs pins with diffout capability for the mem_clk[n:1] and mem_clk_n[n:1] signals (where n is greater than or equal to 1) (4) ddr3 sdram without leveling ddr2 sdram (with differential dqs signaling) (5) any unused pins with diffio_rx capability for the mem_clk[0] and mem_clk_n[0] signals any unused pins with diffout capability for the mem_clk[n:1] and mem_clk_n[n:1] signals (where n is greater than or equal to 1) ddr2 sdram (with single-ended dqs signaling) (5) ddr sdram rldram ii any diffout pins notes to ta bl e 7? 1 : (1) if the write data signals are unidirectional, connect them, including the data mask pins, to a separate dqs/dq group other t han the read dqs/dq group. connect the write clock to the dqs and dqsn pin-pair associated with that dqs/dq group. do not use the cq and cqn pin-pa ir as write clocks. (2) the bwsn, nwsn, and dm pins must be part of the write dqs/dq group, while parity, qvld, and ecc pins must be part of the rea d dqs/dq group. the altmemphy megafunction does not s upport the qvld pin. however, if your design supports the qvld pin, the qvld pin mu st be part of the read dqs/dq group as well. (3) altera?s external memory interface ips do not support placement of the bwsn pins outside the dqs/dq group adjacent to the 3 2/36 dqs/dq groups where the write data pins reside. when using 32/36 dqs/ dq groups that have 40 pins, bwsn inputs are not supported. how ever, if you are not using altera?s memory interface ips and you ar e using 32/36 dqs/dq groups that have 40 pins, you can place the bw sn pins in a separate 4 dqs/dq group adjacent to the 32/36 dqs/dq group where the write data pins reside. (4) the dq or dqs pins can be from 4 or larger dqs/dq groups. altera?s memory interface ips assign the memory clock signals to the smallest possible group size that can fit the signals. (5) ddr2 sdram supports either single-ended or differential dqs signaling. (6) qdr ii+/qdr ii sram devices use the k/k# clock pin-pair to latch write data, address, and command signals. the clocks must be part of the dqs/dq group and follow the write data clock rules. (7) when interfacing with rldram ii 36 cio devices, use two dq pins in the 16/ 18 dqs/dq groups, which are the dqs/dqsn pins in the 4 or 8/ 9 dqs/dq groups for the write data clock. (8) altmemphy megafunction implementation for a ddr3, ddr2, or ddr sdram interface requires that you place all memory clock pin- pairs in a single dq group of adequate width to minimize skew. for example, dimms requiring three memory clock pin-pairs must use a 4 d qs/dq group. tab le 7 ?1 . stratix iv memory interface pin utilization (part 2 of 2) pin description memory standard stratix iv pin utilization chapter 7: external memory interfaces in stratix iv devices 7?5 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 ddr3, ddr2, ddr sdram, and rldram ii devices use the ck and ck# signals to capture the address and command signals. generate these signals to mimic the write-data strobe using stratix iv ddr i/o registers (ddios) to ensure that the timing relationships between the ck/ck# and dqs signals (t dqss , t dss , and t dsh in ddr3, ddr2, and ddr sdram devices or t ckdk in rldram ii devices) are met. qdr ii+ and qdr ii sram devices use the same clock (k/k#) to capture write data, address, and command signals. memory clock pins in stratix iv devices are generated using a ddio register going to differential output pins (refer to figure 7?2 ), marked in the pin table with diffout , diffio_tx , or diffio_rx prefixes. for more information about which pins to use for memory clock pins, refer to table 7?1 . stratix iv devices offer differential input buffers for differential read-data strobe and clock operations. in addition, stratix iv devices also provide an independent dqs logic block for each cqn pin for complementary read-data strobe and clock operations. in the stratix iv pin tables, the differential dqs pin pairs are denoted as dqs and dqsn pins, while the complementary cq signals are denoted as cq and cqn pins. dqsn and cqn pins are marked separately in the pin table. each cqn pin connects to a dqs logic block and the shifted cqn signals go to the negative-edge input registers in the dq ioe registers. 1 ffr fr rfc r r v c rc c rfc r rc r vc c rc r r rc wr ffr r r r rrr wr cc c wr r r fr wr cc figure 7?2. memory clock generation (note 1) notes to figure 7?2 : (1) for pin location requirements, refer to table 7?1 on page 7?3 . (2) the mem_clk[0] and mem_clk_n[0] pins for ddr3, ddr2, and ddr sdram interfaces use the i/o input buffer for feedback required by the altmemphy megafunction for tracking; therefore, use bidirectional i/o buffers for these pins. for memory interfaces using a differential dqs input, the input feedback buffer is configured as differential input. for memory interfaces usi ng a single-ended dqs input, the input buffer is configured as a single-ended input. using a single-ended input feedback buffer requires that i/o standard?s vref voltage is provided to that i/o bank?s vref pins. (3) to minimize jitter, regional clock networks are required for memory output clock generation. mem_clk (2) qd qd system clock (3) fpga les i/o elements v cc mem_clk_n (2) 1 0 7?6 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation 1 using a dqs/dq group for the write-data signals minimizes output skew, allows access to the write-leveling circuitry (for ddr3 sdram interfaces), and allows vertical migration. these pins also have access to deskewing circuitry (using programmable delay chains) that can compensate for delay mismatch between signals on the bus. the dqs and dq pin locations are fixed in the pin table. memory interface circuitry is available in every stratix iv i/o bank that does not support transceivers. all the memory interface pins support the i/o standards required to support ddr3, ddr2, ddr sdram, qdr ii+, qdr ii sram, and rldram ii devices. the stratix iv device family supports dqs and dq signals with dq bus modes of 4, 8/9, 16/18, or 32/36, although not all devices support dqs bus mode 32/36. when any of these pins are not used for memory interfacing, you can use them as user i/os. in addition, you can use any dqsn or cqn pins not used for clocking as dq (data) pins. table 7?2 lists pin support per dqs/dq bus mode, including the dqs/cq and dqsn/cqn pin pair. tab le 7 ?2 . stratix iv dqs/dq bus mode pins mode dqsn support cqn support parity or dm (optional) qvld (optional) (1) typical number of data pins per group maximum number of data pins per group (2) 4 yes no no (6) n o45 8/9 (3) ye s yes ye s yes 8 or 9 1 1 16/18 (4) yes yes yes yes 16 or 18 23 32/36 (5) yes yes yes yes 32 or 36 47 32/36 (7) ye s yes n o ( 8 ) yes 32 or 36 39 notes to ta bl e 7? 2 : (1) the qvld pin is not used in the altmemphy megafunction. (2) this represents the maximum number of dq pins (including parity, data mask, and qvld pins) c onnected to the dqs bus network with single-ended dqs signaling. when you use differential or complementary dqs signaling, the maximum number of data per group decr eases by one. this number may vary per dqs/dq group in a particular device. check the pin table for the exact number per group. for d dr3, ddr2, and ddr interf aces, the number of pins is further reduced for an interface larger than 8 due to the need of one dqs pin for each 8/9 group that is used to form the x16/18 and 32/36 groups. (3) two 4 dqs/dq groups are stitched to make a 8/9 group so there are a total of 12 pins in this group. (4) four 4 dqs/dq groups are st itched to make a 16/18 group. (5) eight 4 dqs/dq groups are stitched to make a 32/36 group. (6) the dm pin can be supported if differential dqs is not used and the group does not have additional signals. (7) these 32/36 dqs/dq groups are available in ep4sgx290, ep4sgx 360, and ep4sgx530 devices in 1152- and 1517-pin fineline bga packages. there are 40 pins in each of these dqs/dq groups. (8) there are 40 pins in each of these dqs/dq groups. the bwsn pins cannot be placed within the same dqs/dq group as the write d ata pins because of insufficient pins available. chapter 7: external memory interfaces in stratix iv devices 7?7 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 table 7?3 lists the number of dqs/dq groups available per side in each stratix iv device. for a more detailed listing of the number of dqs/dq groups available per bank in each stratix iv device, see figure 7?3 through figure 7?19 . these figures represent the die-top view of the stratix iv device. tab le 7 ?3 . number of dqs/dq groups in stratix iv devices per side (part 1 of 2) (note 1) device package side 4 (2) 8/9 16/18 32/36 (3) refer to: ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 780-pin fineline bga left 14 6 2 0 figure 7?3 top/bottom 17 8 2 0 right 0 0 0 0 ep4sgx290 ep4sgx360 780-pin fineline bga left/right 0 0 0 0 figure 7?5 top/bottom 18 8 2 0 ep4se230 ep4se360 780-pin fineline bga left/right 14 6 2 0 figure 7?4 top/bottom 17 8 2 0 ep4sgx110 1152-pin fineline bga (with 16 transceivers) right/left 7 3 1 0 figure 7?6 top/bottom 17 8 2 0 ep4sgx70 ep4sgx110 1152-pin fineline bga (with 24 transceivers) right/left 14 6 2 0 figure 7?7 top/bottom 17 8 2 0 ep4sgx180 ep4sgx230 1152-pin fineline bga right/left 13 6 2 0 figure 7?8 top/bottom 26 12 4 0 ep4sgx290 ep4sgx360 ep4sgx530 1152-pin fineline bga right/left 13 6 2 0 figure 7?9 top/bottom 26 12 4 2 (4) ep4se360 ep4se530 ep4se820 1152-pin fineline bga all sides 26 12 4 0 figure 7?10 ep4sgx180 ep4sgx230 1517-pin fineline bga all sides 26 12 4 0 figure 7?11 ep4sgx290 ep4sgx360 ep4sgx530 1517-pin fineline bga right/left 26 12 4 0 figure 7?12 top/bottom 26 12 4 2 (4) ep4se530 ep4se820 1517-pin fineline bga right/left 34 16 6 0 figure 7?13 top/bottom 38 18 8 4 ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g5 1517-pin fineline bga left 12 3 1 0 figure 7?14 top/bottom 26 12 4 0 right 11 4 1 0 ep4sgx290 ep4sgx360 ep4sgx530 1760-pin fineline bga right/left 26 12 4 0 figure 7?15 top/bottom 38 18 8 4 ep4se530 1760-pin fineline bga right/left 34 16 6 0 figure 7?16 top/bottom 38 18 8 4 7?8 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation ep4se820 1760-pin fineline bga right/left 40 18 6 0 figure 7?17 top/bottom 44 22 10 4 ep4sgx290 ep4sgx360 ep4sgx530 1932-pin fineline bga right/left 29 13 4 0 figure 7?18 top/bottom 38 18 8 4 ep4s100g3 ep4s100g4 ep4s100g5 1932-pin fineline bga left 8 2 0 0 figure 7?19 top/bottom 38 18 8 4 right 7 1 0 0 notes to ta bl e 7? 3 : (1) these numbers are preliminary until the devices are available. (2) some of the 4 groups may use r up and r dn pins. you cannot use these groups if you use the stratix iv calibrated oct feature. (3) to interface with a 36 qdr ii+/qdr ii sram device in a stratix iv fpga that does not support the 32/36 dqs/dq group, refer to ?combining 16/18 dqs/dq groups for a 36 qd r ii+/qdr ii sram interface? on page 7?27 . (4) these 32/36 dqs/dq groups have 40 pins instead of 48 pins per group. bwsn pins cannot be placed within the same dqs/dq group as the write data pins because of insufficient pins available. tab le 7 ?3 . number of dqs/dq groups in stratix iv devices per side (part 2 of 2) (note 1) device package side 4 (2) 8/9 16/18 32/36 (3) refer to: chapter 7: external memory interfaces in stratix iv devices 7?9 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?3. number of dqs/dq groups per bank in ep4sgx70, ep4sgx110, ep4sgx180, and ep4sgx230 devices in the 780-pin fineline bga package (note 1) , (2) , (3) , (4) . (5) notes to figure 7?3 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx70, ep4sgx110, ep4sgx180, and ep4sgx230 devices do not support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qd r ii+/qdr ii sram interface? on page 7?27 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group; however, there are restrictions on using 8/9 groups that in clude that 4 group. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. (5) all i/o pin counts include dedicated clock inputs that you can use for data inputs. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 8c 24 user i/os x4=2 x8/x9=1 x16/x18=0 i/o bank 7c 24 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 7a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 4a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 4c 24 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 3c 24 user i/os x4=2 x8/x9=1 x16/x18=0 i/o bank 3a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 2a 32 user i/os x4=4 x8/x9=2 x16/x18=1 i/o bank 2c 26 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 1c 26 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 1a 32 user i/os x4=4 x8/x9=2 x16/x18=1 ep4sgx70, ep4sgx110, ep4sgx180, and ep4sgx230 devices in the 780-pin fineline bga 7?10 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?4. number of dqs/dq groups per bank in ep4se230 and ep4se360 devices in the 780-pin fineline bga package (note 1) , (2) , (3) , (4) , (5) notes to figure 7?4 : (1) these numbers are preliminary until the devices are available. (2) ep4se230 and ep4se360 devices do not support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+ /qdr ii sram interface? on page 7?27 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group; however, there are restrictions on using 8/9 groups that include that 4 group. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. (5) all i/o pin counts include dedicated clock inputs that you can use for data inputs. dll0 dll3 i/o bank 8a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 8c 24 user i/os x4=2 x8/x9=1 x16/x18=0 i/o bank 7c 24 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 7a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 1a 32 user i/os x4=4 x8/x9=2 x16/x18=1 i/o bank 1c 26 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 2c 26 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 2a 32 user i/os x4=4 x8/x9=2 x16/x18=1 dll1 i/o bank 3a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 3c 24 user i/os x4=2 x8/x9=1 x16/x18=0 i/o bank 4c 24 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 4a 40 user i/os x4=6 x8/x9=3 x16/x18=1 dll2 i/o bank 6a 32 user i/os x4=4 x8/x9=2 x16/x18=1 i/o bank 6c 26 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 5c 26 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 5a 32 user i/os x4=4 x8/x9=2 x16/x18=1 ep4se230 and ep4se360 devices in the 780-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?11 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?5. number of dqs/dq groups per bank in ep4sgx290 and ep4sgx360 devices in the 780-pin fineline bga package (note 1) , (2) notes to figure 7?5 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx290 and ep4sgx360 devices do not support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+ /qdr ii sram interface? on page 7?27 . dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 8c i/o bank 7c i/o bank 7a i/o bank 4a i/o bank 4c i/o bank 3c i/o bank 3a 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16//x18=0 40 user i/os x4=6 x8/x9=3 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 40 user i/os x4=6 x8/x9=3 x16/x18=1 ep4sgx290 and ep4sgx360 devices in the 780-pin fineline bga 7?12 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?6. number of dqs/dq groups per bank in ep4sgx110 devices with 16 transceivers in the 1152-pin fineline bga package (note 1) , (2) , (3) , (4) , (5) notes to figure 7?6 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx110 devices do not support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?27 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group; however, there are restrictions on using 8/9 groups that include that 4 group. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. (5) all i/o pin counts include dedicated clock inputs that you can use for data inputs . dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 8c 24 user i/os x4=2 x8/x9=1 x16/x18=0 i/o bank 7c 24 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 7a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 6a 32 user i/os x4=4 x8/x9=2 x16/x18=1 i/o bank 6c 26 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 4a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 4c 24 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 3c 24 user i/os x4=2 x8/x9=1 x16/x18=0 i/o bank 3a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 1c 26 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 1a 32 user i/os x4=4 x8/x9=2 x16/x18=1 ep4sgx110 devices in the 1152-pin fineline bga (with 16 transceivers) chapter 7: external memory interfaces in stratix iv devices 7?13 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?7. number of dqs/dq groups per bank in ep4sgx70 and ep4sgx110 devices with 24 transceivers in the 1152-pin fineline bga package (note 1) , (2) , (3) , (4) , (5) notes to figure 7?7 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx70 and ep4sgx110 devices do not support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+ /qdr ii sram interface? on page 7?27 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group; however, there are restrictions on using 8/9 groups that include that 4 group. (4) all i/o pin counts include dedicated clock inputs that you can use for data inputs . (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 i/o bank 8a (3) 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 8c 24 user i/os x4=2 x8/x9=1 x16/x18=0 i/o bank 7c 24 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 7a (3) 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 6a (3) 32 user i/os x4=4 x8/x9=2 x16/x18=1 i/o bank 6c 26 user i/os (5) x4=3 x8/x9=1 x16/x18=0 i/o bank 1c (4) 26 user i/os (5) x4=3 x8/x9=1 x16/x18=0 i/o bank 1a (3) 32 user i/os x4=4 x8/x9=2 x16/x18=1 ep4sgx70 and ep4sgx110 devices in the 1152-pin fineline bga (with 24 transceivers) dll1 dll2 i/o bank 4a (3) 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 4c 24 user i/os x4=3 x8/x9=1 x16/x18=0 i/o bank 3c 24 user i/os x4=2 x8/x9=1 x16/x18=0 i/o bank 3a (3) 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 6a (3) 32 user i/os x4=4 x8/x9=2 x16/x18=1 i/o bank 6c 26 user i/os (5) x4=3 x8/x9=1 x16/x18=0 i/o bank 1c (4) 26 user i/os (5) x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=4 x8/x9=2 x16/x18=1 7?14 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?8. number of dqs/dq groups per bank in ep4sgx180 and ep4sgx230 devices in the 1152-pin fineline bga package (note 1) , (2) , (3) , (4) , (5) notes to figure 7?8 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx180 and ep4sgx230 devices do not support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+ /qdr ii sram interface? on page 7?27 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group; however, there are restrictions on using 8/9 groups that include that 4 group. (4) all i/o pin counts include dedicated clock inputs that you can use for data inputs. (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 1c i/o bank 1a 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16//x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x6/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 ep4sgx180 and ep4sgx230 devices in the 1152-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?15 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?9. number of dqs/dq groups per bank in ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1152-pin fineline bga package (note 1) , (3), (4) , (5) notes to figure 7?9 : (1) these numbers are preliminary until the devices are available. (2) these 32/36 dqs/dq groups have 40 pins instead of 48 pins per group. (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group; however, there are restrictions on using 8/9 groups that include that 4 group. (4) all i/o pin counts include dedicated clock inputs that you can use for data inputs. (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=1 (2) i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 1c i/o bank 1a 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16//x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=1 (2) 48 user i/os x4=7 x8/x9=3 x6/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=1 (2) 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=1 (2) 48 user i/os x4=7 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1152-pin fineline bga 7?16 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?10. number of dqs/dq groups per bank in ep4se360, ep4se530, and ep4se820 devices in the 1152-pin fineline bga package (note 1) , (2) , (3) , (4) , (5) notes to figure 7?10 : (1) these numbers are preliminary until the devices are available. (2) ep4se360, ep4se530, and ep4se820 devices do not support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refe r to ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? on page 7?27 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group, however there are restrictions on using 8/9 groups that include that 4 group. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. (5) all i/o pin counts include dedicated clock inputs that you can use for data inputs. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 5a i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2a i/o bank 2c i/o bank 1c i/o bank 1a 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16//x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x6/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x6/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x16/x18=1 ep4se360, ep4se530 and ep4se820 devices in the 1152-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?17 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?11. number of dqs/dq groups per bank in ep4sgx180 and ep4sgx230 devices in the 1517-pin fineline bga package (note 1) , (2) , (3) , (4) , (5) notes to figure 7?11 : (1) these numbers are preliminary until the devices are available. (2) ep4sgx180 and ep4sgx230 devices do not support 32/36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qdr ii+ /qdr ii sram interface? on page 7?27 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group, however there are restrictions on using 8/9 groups that include that 4 group. (4) all i/o pin counts include dedicated clock inputs that you can use for data inputs. (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 5a i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2a i/o bank 2c i/o bank 1c i/o bank 1a 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16//x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x6/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x6/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x16/x18=1 ep4sgx180 and ep4sgx230 devices in the 1517-pin fineline bga 7?18 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?12. number of dqs/dq groups per bank in ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1517-pin fineline bga package (note 1) , (3) , (4) , (5) notes to figure 7?12 : (1) these numbers are preliminary until the devices are available. (2) these 32/36 dqs/dq groups have 40 pins instead of 48 pins per group. (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group, however there are restrictions on using 8/9 groups that include that 4 group. (4) all i/o pin counts include dedicated clock inputs that you can use for data inputs. (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 40 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=1 (2) i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 5a i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2a i/o bank 2c i/o bank 1c i/o bank 1a 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16//x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=1 (2) 48 user i/os x4=7 x8/x9=3 x6/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x6/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=1 (2) 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=1 (2) 48 user i/os x4=7 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 42 user i/os x4=6 x8/x9=3 x16/x18=1 48 user i/os x4=7 x8/x9=3 x16/x18=1 ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1517-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?19 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?13. number of dqs/dq groups per bank in ep4se530 and ep4se820 devices in the 1517-pin fineline bga package (note 1) , (2) , (3) , (4) notes to figure 7?13 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group, however there are restrictions on using 8/9 groups that include that 4 group. (3) all i/o pin counts include dedicated clock inputs and dedicated corner pll clock inputs that you can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6b i/o bank 6c i/o bank 5c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2c i/o bank 1c i/o bank 1b i/o bank 1a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 user i/os x 4=3 x8/x9=1 x16/x18=0 x32/x36=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 i/o bank 5b 24 user i/os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 i/o bank 5a 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 i/o bank 2b 24 user i/os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 i/o bank 2a 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 ep4se530 and ep4se820 de vices in the 1517-pin fineline bga 7?20 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?14. number of dqs/dq groups per bank in ep4s40g2, ep4s40g5, ep4s100g2, and ep4s100g5 devices in the 1517-pin fineline bga package (note 1) , (2) , (3) , (4) , (5) notes to figure 7?14 : (1) these numbers are preliminary until the devices are available. (2) ep4s40g2, ep4s40g5, ep4s100g2, a nd ep4s100g5 devices do not support 32/ 36 mode. to interface with a 36 qdr ii+/qdr ii sram device, refer to ?combining 16/18 dqs/dq groups for a 36 qd r ii+/qdr ii sram interface? on page 7?27 . (3) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group, however there are restrictions on using 8/9 groups that include that 4 group. (4) all i/o pin counts include dedicated clock inputs that you can use for data inputs. (5) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. make sure that the dqs/dq groups that you have chosen are not used for configuration as you ma y lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 i/o bank 8a 40 user i/os x4=6 x8/x9=3 x16/x18=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 5a i/o bank 2a i/o bank 2c i/o bank 1c i/o bank 1a 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 44 user i/os x4=5 x8/x9=1 x16/x18=0 21 user i/os x4=0 x8/x9=0 x16/x18=0 21 user i/os x4=0 x8/x9=0 x16/x18=0 46 user i/os x4=6 x8/x9=3 x16/x18=1 dll1 dll2 i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a 40 user i/os x4=6 x8/x9=3 x16/x18=1 24 user i/os x4=4 x8/x9=2 x16/x18=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 40 user i/os x4=6 x8/x9=3 x16/x18=1 43 user i/os x4=5 x8/x9=1 x16/x18=0 20 user i/os x4=0 x8/x9=0 x16/x18=0 21 user i/os x4=1 x8/x9=0 x16/x18=0 46 user i/os x4=6 x8/x9=2 x16/x18=1 ep4s40g2, ep4s40g5, ep4s100g2, and ep4s100g5 de vices in the 1517-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?21 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?15. number of dqs/dq groups per bank in ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1760-pin fineline bga package (note 1) , (2), (3) , (4) notes to figure 7?15 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group, however there are restrictions on using 8/9 groups that include that 4 group. (3) all i/o pin counts include dedicated clock inputs and dedicated corner pll clock inputs that you can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 5a i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2a i/o bank 2c i/o bank 1c i/o bank 1a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 32 user i/os x4=3 x8/x9=1 x16//x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 50 user i/os x4=7 x8/x9=3 x6/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1760-pin fineline bga 7?22 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?16. number of dqs/dq groups per bank in ep4se530 devices in the 1760-pin fineline bga package (note 1) , (2) , (3) , (4) notes to figure 7?16 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group, however there are restrictions on using 8/9 groups that include that 4 group. (3) all i/o pin counts include dedicated clock inputs and dedicated corner pll clock inputs that you can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6b i/o bank 6c i/o bank 5c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2c i/o bank 1c i/o bank 1b i/o bank 1a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 user i/os x 4=3 x8/x9=1 x16/x18=0 x32/x36=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 24 user i/os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 i/o bank 5b 24 user i/os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 i/o bank 5a 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 i/o bank 2b 24 user i/os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 i/o bank 2a 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 ep4se530 de vices in the 1760-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?23 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?17. number of dqs/dq groups per bank in ep4se820 devices in the 1760-pin fineline bga package (note 1) , (2) , (3) , (4) notes to figure 7?17 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group, however there are restrictions on using 8/9 groups that include that 4 group. (3) all i/o pin counts include dedicated clock inputs and dedicated corner pll clock inputs that you can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6b i/o bank 6c i/o bank 5c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2c i/o bank 1c i/o bank 1b i/o bank 1a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 48 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 36 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 48 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 36 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 i/o bank 5b 36 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 i/o bank 5a 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 i/o bank 2b 36 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 i/o bank 2a 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 ep4se820 de vices in the 1760-pin fineline bga 7?24 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?18. number of dqs/dq groups per bank in ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1932-pin fineline bga package (note 1) , (2), (3) , (4) notes to figure 7?18 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group, however there are restrictions on using 8/9 groups that include that 4 group. (3) all i/o pin counts include dedicated clock inputs and dedicated corner pll clock inputs that you can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2c i/o bank 1c i/o bank 1a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 42 user i/os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 i/o bank 5b 20 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 i/o bank 5a 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 i/o bank 2b 20 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 i/o bank 2a 50 user i/os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 ep4sgx290, ep4sgx360, and ep4sgx530 de vices in the 1932-pin fineline bga chapter 7: external memory interfaces in stratix iv devices 7?25 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 the dqs and dqsn pins are listed in the stratix iv pin tables as dqsxy and dqsnxy , respectively, where x indicates the dqs/dq grouping number and y indicates whether the group is located on the top (t), bottom (b), left (l), or right (r) side of the device. the dqs/dq pin numbering is based on 4 mode. the corresponding dq pins are marked as dqxy , where x indicates which dqs group the pins belong to and y indicates whether the group is located on the top (t), bottom (b), left (l), or right (r) side of the device. for example, dqs1l indicates a dqs pin located on the left side of the device. the dq pins belonging to that group are shown as dq1l in the pin table. for more information, refer to figure 7?20 . figure 7?19. number of dqs/dq groups per bank in ep4s100g3, ep4s100g4, and ep4s100g5 devices in the 1932-pin fineline bga package (note 1) , (2) , (3) , (4) notes to figure 7?19 : (1) these numbers are preliminary until the devices are available. (2) you can also use dqs/dqsn pins in some of the 4 groups as r up and r dn pins, but you cannot use a 4 group for memory interfaces if two pins of the 4 group are used as r up and r dn pins for oct calibration. if two pins of a 4 group are used as r up and r dn pins for oct calibration, you can use the 16/18 or 32/36 groups that include that 4 group, however there are restrictions on using 8/9 groups that include that 4 group. (3) all i/o pin counts include dedicated clock inputs and dedicated corner pll clock inputs that you can use for data inputs. (4) you can also use some of the dqs/dq pins in i/o bank 1c as configuration pins. you cannot use a 4 dqs/dq group with any of its pin members used for configuration purposes. ensure that the dqs/dq groups that you have chosen are not also used for configuration because you may lose up to four 4 dqs/dq groups, depending on your configuration scheme. dll0 dll3 dll1 dll2 i/o bank 8a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 i/o bank 8b i/o bank 8c i/o bank 7c i/o bank 7b i/o bank 7a i/o bank 6a i/o bank 6c i/o bank 5c i/o bank 4a i/o bank 4b i/o bank 4c i/o bank 3c i/o bank 3b i/o bank 3a i/o bank 2c i/o bank 1c i/o bank 1a 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 38 user i/os x4=3 x8/x9=0 x16/x18=0 x32/x36=0 20 user i/os x4=0 x8/x9=0 x16/x18=0 x32/x36=0 17 user i/os x4=0 x8/x9=0 x16/x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 32 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 48 user i/os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 40 user i/os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 19 user i/os x4=0 x8/x9=0 x16/x18=0 x32/x36=0 19 user i/os x4=0 x8/x9=0 x16/x18=0 x32/x36=0 i/o bank 5b 12 user i/os x4=0 x8/x9=0 x16/x18=0 x32/x36=0 i/o bank 5a 40 user i/os x4=4 x8/x9=1 x16/x18=0 x32/x36=0 i/o bank 2b 13 user i/os x4=1 x8/x9=0 x16/x18=0 x32/x36=0 i/o bank 2a 39 user i/os x4=4 x8/x9=1 x16/x18=0 x32/x36=0 ep4s100g3, ep4s100g4, and ep4s100g5 de vices in the 1932-pin fineline bga 7?26 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation 1 the parity, dm, bwsn, nwsn, ecc, and qvld pins are shown as dq pins in the pin table. the numbering scheme starts from the top-left corner of the device going counter-clockwise in a die-top view. figure 7?20 shows how the dqs/dq groups are numbered in a die-top view of the device. the top and bottom sides of the device can contain up to 38 4 dqs/dq groups. the left and right sides of the device can contain up to 34 4 dqs/dq groups. figure 7?20. dqs pins in stratix iv i/o banks 8a 8b 8c 7c 7b 7a dqs38t dqs1l 1a 1b 1c 2c 2b 2a dqs34l 3a 3b 3c 4c 4b 4a 5a 5b 5c 6c 6b 6a dqs17l dqs20t dqs19t dqs1t dqs34r dqs18r dqs1r dqs1b dqs19b dqs20b dqs38b dqs17r dqs18l stratix iv device pll_l1 dll0 pll_l4 dll1 pll_r4 dll2 dll3 pll_r1 pll_l2 pll_l3 pll_r2 pll_r3 pll_t1 pll_t2 pll_b2 pll_b1 chapter 7: external memory interfaces in stratix iv devices 7?27 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 using the r up and r dn pins in a dqs/dq group used for memory interfaces you can use the dqs/dqsn pins in some of the 4 groups as r up and r dn pins (listed in the pin table). you cannot use a 4 dqs/dq group for memory interfaces if any of its pin members are used as r up and r dn pins for oct calibration. you may be able to use the 8/9 group that includes this 4 dqs/dq group, if either of the following applies: 1 r 11 r r w r r fr r fwr c w r f combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface this implementation combines 16/18 dqs/dq groups to interface with a 36 qdr ii+/qdr ii sram device. the 36 read data bus uses two 16/18 groups while the 36 write data uses another two 16/18 or four 8/9 groups. the cq/cqn signal traces are split on the board trace to connect to two pairs of cq/cqn pins in the fpga. this is the only connection on the board that you need to change for this implementation. other qdr ii+/qdr ii sram interface rules for stratix iv devices also apply for this implementation. 1 fc r r rfc c v cc rfc f r r fr fc r rfr external memory interface handbook . 7?28 chapter 7: external memory interfaces in stratix iv devices memory interfaces pin support stratix iv device handbook volume 1 ? march 2010 altera corporation rules to combine groups in 780-, 1152-, and some 1517-pin package devices, there is at most one 16/18 group per i/o sub-bank. you can combine two 16/18 groups from a single side of the device for a 36 interface. for devices that do not have four 16/18 groups in a single side of the device to form two 36 groups for read and write data, you can form one 36 group on one side of the device and another 36 group on the other side of the device. for vertical migration with the 36 emulation implementation, check if migration is possible by enabling device migration in the quartus ii project. the quartus ii software supports the use of four 8/9 dq groups for write data pins and migration of these groups across device density. table 7?4 lists the possible combinations to use two 16/18 dqs/dq groups to form a 32/36 group on stratix iv devices lacking a native 32/36 dqs/dq group. tab le 7 ?4 . possible group combinations in stratix iv devices (part 1 of 2) package device density i/o sub-bank combinations 780-pin fineline bga ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 3a and 4a, 7a and 8a (bottom and top i/o banks) (1) ep4se230 ep4se360 1a and 2a, 5a and 6a (left and right i/o banks) 3a and 4a, 7a and 8a (bottom and top i/o banks) (1) 1152-pin fineline bga ep4sgx70 ep4sgx110 3a and 4a, 7a and 8a (bottom and top i/o banks) (1) ep4sgx180 ep4sgx230 ep4sgx290 (2) ep4sgx360 (2) ep4sgx530 (2) 1a and 1c, 6a and 6c (left and right i/o banks) 3a and 3b, 4a and 4b (bottom i/o banks) 7a and 7b, 8a and 8b (top i/o banks) ep4se360 ep4se530 ep4se820 1a and 1c, 2a and 2c (left i/o banks) 3a and 3b, 4a and 4b (bottom i/o banks) 5a and 5c, 6a and 6c (right i/o banks) 7a and 7b, 8a and 8b (top i/o banks) chapter 7: external memory interfaces in stratix iv devices 7?29 memory interfaces pin support ? march 2010 altera corporation stratix iv device handbook volume 1 1517-pin fineline bga ep4sgx180 ep4sgx230 ep4sgx290 (2) ep4sgx360 (2) ep4sgx530 (2) 1a and 1c, 2a and 2c (left i/o banks) 3a and 3b, 4a and 4b (bottom i/o banks) 5a and 5c, 6a and 6c (right i/o banks) 7a and 7b, 8a and 8b (top i/o banks) ep4se530 (2) ep4se820 (2) 1a and 1b, 2a and 2b or 1b and 1c, 2b and 2c (left i/o banks) (3) 5a and 5b, 6a and 6b or 5b and 5c, 6b and 6c (right i/o banks) (3) ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g5 3a and 3b, 4a and 4b (bottom i/o banks) 7a and 7b, 8a and 8b (top i/o banks) 1760-pin fineline bga ep4sgx290 ep4sgx360 ep4sgx530 1a and 1c, 2a and 2c (left i/o banks) 3a and 3b, 4a and 4b (bottom i/o banks) 5a and 5c, 6a and 6c (right i/o banks) 7a and 7b, 8a and 8b (top i/o banks) ep4se530 (2) ep4se820 (2) 1a and 1b, 2a and 2b or 1b and 1c, 2b and 2c (left i/o banks) (3) 5a and 5b, 6a and 6b or 5b and 5c, 6b and 6c (right i/o banks) (3) 1932-pin fineline bga ep4sgx290 (2) ep4sgx360 (2) ep4sgx530 (2) 1a and 1c, 2a and 2c (left i/o banks) 5a and 5c, 6a and 6c (right i/o banks) notes to ta bl e 7? 4 : (1) each side of the device in these packages has four remaining 8/9 groups. you can combine them for the write side (only) if you want to keep the 36 qdr ii+/qdr ii sram interface on one side of the device. you must change the memory interface data group default assignment from the default 18 to 9 in this case. (2) this device supports 36 dqs/dq groups on the top and bottom i/o banks natively. (3) although it is possible to combine the 16/18 dqs/dq groups from i/o banks 1a and 1c, 2a and 2c, 5a and 5c, and 6a and 6c, altera does not recommend this due to the size of the package. similarly, crossing a bank number (for example, combining groups from i/o banks 6c and 5c) is not supported in this package. tab le 7 ?4 . possible group combinations in stratix iv devices (part 2 of 2) package device density i/o sub-bank combinations 7?30 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation stratix iv external memory interface features stratix iv devices are rich with features that allow robust high-performance external memory interfacing. the altmemphy megafunction allows you to use these external memory interface features and helps set up the physical interface (phy) best suited for your system. this section describes each stratix iv device feature that is used in external memory interfaces from the dqs phase-shift circuitry, dqs logic block, leveling multiplexers, and dynamic oct control block. 1 fc r r crr r fc c r f frc f rfc f r vc w r r rfc r vc v rr cvr fr fr frc fr crr frc vc vr c rr f r r crr r f r f frc r r crr r fc fc fr f r r fr fc rfr external memory phy interface (altmemphy) (nonafi) megafunction user guide . dqs phase-shift circuitry stratix iv phase-shift circuitry provides phase shift to the dqs/cq and cqn pins on read transactions when the dqs/cq and cqn pins are acting as input clocks or strobes to the fpga. the dqs phase-shift circuitry consists of dlls that are shared between multiple dqs pins and the phase-offset module to further fine-tune the dqs phase shift for different sides of the device. figure 7?21 shows how the dqs phase-shift circuitry is connected to the dqs/cq and cqn pins in the device where memory interfaces are supported on all sides of the stratix iv device. chapter 7: external memory interfaces in stratix iv devices 7?31 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 dqs phase-shift circuitry is connected to the dqs logic blocks that control each dqs/cq or cqn pin. the dqs logic blocks allow the dqs delay settings to be updated concurrently at every dqs/cq or cqn pin. figure 7?21. dqs/cq and cqn pins and dqs phase-shift circuitry (note 1) , (2) notes to figure 7?21 : (1) for possible reference input clock pins for each dll, refer to ?dll? on page 7?32 . (2) you can configure each dqs/cq and cqn pin with a phase shift based on one of two possible dll output settings. dll reference clock dqs phase-shift circu itry dqs/cq pin cqn pin cqn pin dqs/cq pin to ioe t t t t dqs phase-shift circu itry dll reference clock dll reference clock dqs/cq pin cqn pin dqs/cq pin cqn pin to ioe to ioe to ioe t t t to ioe t dqs logic blocks dqs/cq pin cqn pin cqn pin dqs/cq pin to ioe to ioe to ioe to ioe t t t t dqs/cq pin cqn pin dqs/cq pin cqn pin t t t t dqs logic blocks dll reference clock dqs phase-shift circu itry to ioe to ioe to ioe dqs phase-shift circu itry to ioe to ioe to ioe to ioe 7?32 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation dll dqs phase-shift circuitry uses a dll to dynamically control the clock delay needed by the dqs/cq and cqn pin. the dll, in turn, uses a frequency reference to dynamically generate control signals for the delay chains in each of the dqs/cq and cqn pins, allowing it to compensate for pvt variations. the dqs delay settings are gray-coded to reduce jitter when the dll updates the settings. the phase-shift circuitry needs 1280 clock cycles to lock and calculate the correct input clock period when the dll is in low jitter mode. otherwise, only 256 clock cycles are needed. do not send data during these clock cycles because there is no guarantee that it will be captured properly. as the settings from the dll may not be stable until this lock period has elapsed, be aware that anything using these settings (including the leveling delay system) may be unstable during this period. 1 c f crcr fr r rfc r 1 wvr f vr v f f c f v ww cr wfrc c wc r f r v r r f fr r vc c c crr f vc fr r f fr frc w c r frc c c v w w ffr ff wc w r vc v ffr f chapter 7: external memory interfaces in stratix iv devices 7?33 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?22 shows the dll and i/o bank locations in stratix iv devices from a die-top view if all sides of the device support external memory interfaces. the dll can access the two adjacent sides from its location within the device. for example, dll0 on the top left of the device can access the top side (i/o banks 7a, 7b, 7c, 8a, 8b, and 8c) and the left side of the device (i/o banks 1a, 1b, 1c, 2a, 2b, and 2c). this means that each i/o bank is accessible by two dlls, giving more flexibility to create multiple frequencies and multiple-type interfaces. you can have two different interfaces with the same frequency on the two sides adjacent to a dll, where the dll controls the dqs delay settings for both interfaces. each bank can use settings from either or both dlls the bank is adjacent to. for example, dqs1l can get its phase-shift settings from dll0, while dqs2l can get its phase-shift settings from dll1. table 7?5 lists the dll location and supported i/o banks for stratix iv devices. 1 c v r rfc c c 1 1 1 w v c c r v c r figure 7?22. stratix iv dll and i/o bank locations (die-top view) pll_t1 pll_t2 pll_b1 pll_b2 stratix iv fpga 8a 8b 8c 7c 7b 7a 3a 3b 3c 4c 4b 4a 2a 2b 2c pll_l2 1c 1b 1a 5a 5b 5c 6c 6b 6a 6 6 6 6 6 6 6 6 dll0 pll_l1 dll3 pll_r1 dll2 pll_r4 dll1 pll_l4 pll_r3 pll_r2 pll_l3 7?34 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation the reference clock for each dll may come from pll output clocks or any of the two dedicated clock input pins located in either side of the dll. table 7?6 through table 7?18 show the available dll reference clock input resources for the stratix iv device family. 1 v c r rfrc cc no compensation to achieve better performance or the quartus ii software changes it automatically. because the pll does not use any other outputs, it does not need to compensate for any clock paths. tab le 7 ?5 . dll location and supported i/o banks dll location accessible i/o banks (1) dll0 top-left corner 1a, 1b, 1c, 2a, 2b, 2c, 7a, 7b, 7c, 8a, 8b, 8c dll1 bottom-left corner 1a, 1b, 1c, 2a, 2b, 2c, 3a, 3b, 3c, 4a, 4b, 4c dll2 bottom-right corner 3a, 3b, 3c, 4a, 4b, 4c, 5a, 5b, 5c, 6a, 6b, 6c dll3 top-right corner 5a, 5b, 5c, 6a, 6b, 6c, 7a, 7b, 7c, 8a, 8b, 8c note to tab l e 7 ?5 : (1) the dll can access these i/o banks if they are available for memory interfacing. tab le 7 ?6 . dll reference clock input for ep4sgx70 and ep4sgx110 devices in the 780-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 ? ? dll2 clk4p clk5p clk6p clk7p ? pll_b1 ? ? dll3 clk12p clk13p clk14p clk15p ? pll_t1 ? ? chapter 7: external memory interfaces in stratix iv devices 7?35 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 tab le 7 ?7 . dll reference clock input for ep4sgx180 and ep4sgx230 devices in the 780-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 ? ? dll2 clk4p clk5p clk6p clk7p ???? dll3 clk12p clk13p clk14p clk15p ???? tab le 7 ?8 . dll reference clock input for ep4se230 and ep4se360 devices in the 780-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 ? ? dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p ??? dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p ? pll_r2 ? 7?36 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation tab le 7 ?9 . dll reference clock input for ep4sgx290 and ep4sgx360 devices in the 780-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p ? pll_t1 ? ? dll1 clk4p clk5p clk6p clk7p ? pll_b1 ? ? dll2 clk4p clk5p clk6p clk7p ? pll_b2 ? ? dll3 clk12p clk13p clk14p clk15p ? pll_t2 ? ? table 7?10. dll reference clock input for ep4sgx70 and ep4sgx110 devices in the 1152-pin fineline bga package (with 24 transceivers) dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l2 ? dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b1 pll_r2 ? dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t1 pll_r2 ? chapter 7: external memory interfaces in stratix iv devices 7?37 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 table 7?11. dll reference clock input for ep4sgx110 devices in the 1152-pin fineline bga package (with 16 transceivers) dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p pll_b1 ? ? dll2 clk4p clk5p clk6p clk7p clk10p clk11p pll_b1 ? ? dll3 clk12p clk13p clk14p clk15p clk10p clk11p pll_t1 pll_r2 ? table 7?12. dll reference clock input for ep4sgx180, ep4sgx230, ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1152-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p pll_b1 ? ? dll2 clk4p clk5p clk6p clk7p clk10p clk11p pll_b2 ? ? dll3 clk12p clk13p clk14p clk15p clk10p clk11p pll_t2 pll_r2 ? 7?38 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation table 7?13. dll reference clock input for ep4se530 and ep4se820 devices in the 1152-, 1517-, and 1760-pin fineline bga packages dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l3 ? dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b2 pll_r3 ? dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t2 pll_r2 ? table 7?14. dll reference clock input for ep4sgx180, ep4sgx230, ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1517-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l3 ? dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b2 pll_r3 ? dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t2 pll_r2 ? chapter 7: external memory interfaces in stratix iv devices 7?39 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 table 7?15. dll reference clock input for ep4s40g2, ep4s40g5, ep4s100g2, and ep4s100g5 devices in the 1517-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk1p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk1p clk3p pll_b1 pll_l3 ? dll2 clk4p clk5p clk6p clk7p clk8p clk10p pll_b2 pll_r3 ? dll3 clk12p clk13p clk14p clk15p clk8p clk10p pll_t2 pll_r2 ? table 7?16. dll reference clock input for ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1760-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 ? dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l3 ? dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b2 pll_r3 ? dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t2 pll_r2 ? 7?40 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation table 7?17. dll reference clock input for ep4sgx290, ep4sgx360, and ep4sgx530 devices in the 1932-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p clk0p clk1p clk2p clk3p pll_t1 pll_l2 pll_l1 dll1 clk4p clk5p clk6p clk7p clk0p clk1p clk2p clk3p pll_b1 pll_l3 pll_l4 dll2 clk4p clk5p clk6p clk7p clk8p clk9p clk10p clk11p pll_b2 pll_r3 pll_r4 dll3 clk12p clk13p clk14p clk15p clk8p clk9p clk10p clk11p pll_t2 pll_r2 pll_r1 table 7?18. dll reference clock input for ep4s100g3, ep4s100g4, and ep4s100g5 devices in the 1932-pin fineline bga package dll clkin (top/bottom) clkin (left/right) pll (top/bottom) pll (left/right) pll (corner) dll0 clk12p clk13p clk14p clk15p ? pll_t1 pll_l2 pll_l1 dll1 clk4p clk5p clk6p clk7p ? pll_b1 pll_l3 pll_l4 dll2 clk4p clk5p clk6p clk7p clk9p clk11p pll_b2 pll_r3 pll_r4 dll3 clk12p clk13p clk14p clk15p clk9p clk11p pll_t2 pll_r2 pll_r1 chapter 7: external memory interfaces in stratix iv devices 7?41 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?23 shows a simple block diagram of the dll. the input reference clock goes into the dll to a chain of up to 16 delay elements. the phase comparator compares the signal coming out of the end of the delay chain block to the input reference clock. the phase comparator then issues the upndn signal to the gray-code counter. this signal increments or decrements a six-bit delay setting (dqs delay settings) that increases or decreases the delay through the delay element chain to bring the input reference clock and the signals coming out of the delay element chain in phase. 1 ff cr c dlloffsetctrl_ 7?42 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation all dqs/cq and cqn pins, referenced to the same dll, can have their input signal phase shifted by a different degree amount but all must be referenced at one particular frequency. for example, you can have a 90 phase shift on dqs1t and a 60 phase shift on dqs2t , referenced from a 200-mhz clock. not all phase-shift combinations are supported. the phase shifts on the dqs pins referenced by the same dll must all be a multiple of 22.5 (up to 90), 30 (up to 120), 36 (up to 144), 45 (up to 180), or 60 (up to 240). there are eight different frequency modes for the stratix iv dll, as shown in table 7?19 . each frequency mode provides different phase shift selections. in frequency mode 0, 1, 2, and 3, the 6-bit dqs delay settings vary with pvt to implement the phase-shift delay. in frequency modes 4, 5, 6, and 7, only 5 bits of the dqs delay settings vary with pvt to implement the phase-shift delay; the most significant bit of the dqs delay setting is set to 0. f r frc r f c rfr dc and switching characteristics chapter. for 0 shift, the dqs/cq signal bypasses both the dll and dqs logic blocks. the quartus ii software automatically sets the dq input delay chains so that the skew between the dq and dqs/cq pin at the dq ioe registers is negligible when 0 shift is implemented. you can feed the dqs delay settings to the dqs logic block and logic array. the shifted dqs/cq signal goes to the dqs bus to clock the ioe input registers of the dq pins. the signal can also go into the logic array for resynchronization if you are not using ioe resynchronization registers. the shifted cqn signal can only go to the negative-edge input register in the dq ioe and is only used for qdr ii+ and qdr ii sram interfaces. phase offset control each dll has two phase-offset modules and can provide two separate dqs delay settings with independent offsets, one for the top and bottom i/o bank and one for the left and right i/o bank, so you can fine-tune the dqs phase-shift settings between two different sides of the device. even though you have independent phase offset control, the frequency of the interface using the same dll must be the same. use the table 7?19. stratix iv dll frequency modes frequency mode available phase shift number of delay chains 0 22.5, 45, 67.5, 90 16 1 30, 60, 90, 120 12 2 36, 72, 108, 144 10 3 45, 90, 135, 180 8 4 30, 60, 90, 120 12 5 36, 72, 108, 144 10 6 45, 90, 135, 180 8 7 60, 120, 180, 240 6 chapter 7: external memory interfaces in stratix iv devices 7?43 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 phase offset control module for making small shifts to the input signal and use the dqs phase-shift circuitry for larger signal shifts. for example, if the dll only offers a multiple of 30 phase shift, but your interface needs a 67.5 phase shift on the dqs signal, you can use two delay chains in the dqs logic blocks to give you 60 phase shift and use the phase offset control feature to implement the extra 7.5 phase shift. you can use either a static phase offset or a dynamic phase offset to implement the additional phase shift. the available additional phase shift is implemented in 2?s: complement in gray-code between settings ?64 to +63 for frequency mode 0, 1, 2, and 3, and between settings ?32 to +31 for frequency modes 4, 5, 6, and 7. an additional bit indicates whether the setting has a positive or negative value. the settings are linear, each phase offset setting adds a delay amount specified in the dc and switching characteristics chapter. the dqs phase shift is the sum of the dll delay settings and the user-selected phase offset settings whose top setting is 64 for frequency modes 0, 1, 2, and 3; and 32 for frequency modes 4, 5, 6, and 7, so the actual physical offset setting range is 64 or 32 subtracted by the dqs delay settings from the dll. 1 fr r w w ff c rc r r c r f r f cv f frc 1 c rc ff c ff cv wvr f f cv f frc c rc ff c ff fr rc r c frc f r r fr v fr c rfr dc and switching characteristics chapter. when using static phase offset, you can specify the phase offset amount in the altmemphy megafunction as a positive number for addition or a negative number for subtraction. you can also have a dynamic phase offset that is always added to, subtracted from, or both added to and subtracted from the dll phase shift. when you always add or subtract, you can dynamically input the phase offset amount into the dll_offset[5..0] port. when you want to both add and subtract dynamically, you control the addnsub signal in addition to the dll_offset[5..0] signals. 7?44 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation dqs logic block each dqs/cq and cqn pin is connected to a separate dqs logic block, which consists of the dqs delay chains, update enable circuitry, and dqs postamble circuitry ( figure 7?24 ). figure 7?24. stratix iv dqs logic block notes to figure 7?24 : (1) the input reference clock for the dqs phase-shift circuitry can come from a pll output clock or an input clock pin. for more information, refer to table 7?6 through table 7?18 . (2) the dqsenable signal can also come from the stratix iv fpga fabric. d d update enable circuitry 6 6 6 6 4 6 6 6 dqs delay settings from the dqs phase-shift circuitry dqs/cq or cqn pin dqsin delayctrlin [5:0] offsetctrlin [5:0] chapter 7: external memory interfaces in stratix iv devices 7?45 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 dqs delay chain dqs delay chains consist of a set of variable delay elements to allow the input dqs/cq and cqn signals to be shifted by the amount specified by the dqs phase-shift circuitry or the logic array. there are four delay elements in the dqs delay chain; the first delay chain closest to the dqs/cq pin can be shifted either by the dqs delay settings or by the sum of the dqs delay setting and the phase-offset setting. the number of delay chains required is transparent because the altmemphy megafunction automatically sets it when you choose the operating frequency. the dqs delay settings can come from the dqs phase-shift circuitry on either end of the i/o banks or from the logic array. the delay elements in the dqs logic block have the same characteristics as the delay elements in the dll. when the dll is not used to control the dqs delay chains, you can input your own gray-coded 6-bit or 5-bit settings using the dqs_delayctrlin[5..0] signals available in the altmemphy megafunction. these settings control 1, 2, 3, or all 4 delay elements in the dqs delay chains. the altmemphy megafunction can also dynamically choose the number of dqs delay chains needed for the system. the amount of delay is equal to the sum of the delay element?s intrinsic delay and the product of the number of delay steps and the value of the delay steps. you can also bypass the dqs delay chain to achieve a 0 phase shift. update enable circuitry both the dqs delay settings and the phase-offset settings pass through a register before going into the dqs delay chains. the registers are controlled by the update enable circuitry to allow enough time for any changes in the dqs delay setting bits to arrive at all the delay elements. this allows them to be adjusted at the same time. the update enable circuitry enables the registers to allow enough time for the dqs delay settings to travel from the dqs phase-shift circuitry or core logic to all the dqs logic blocks before the next change. it uses the input reference clock or a user clock from the core to generate the update enable output. the altmemphy megafunction uses this circuit by default. figure 7?25 shows an example waveform of the update enable circuitry output. figure 7?25. dqs update enable waveform update enable circuitry output system clock dqs delay settings (updated every 8 cycles) dll counter update (every 8 cycles) 6 bit dll counter update (every 8 cycles) 7?46 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation dqs postamble circuitry for external memory interfaces that use a bidirectional read strobe such as in ddr3, ddr2, and ddr sdram, the dqs signal is low before going to or coming from a high-impedance state. the state in which dqs is low, just after a high-impedance state, is called the preamble; the state in which dqs is low, just before it returns to a high-impedance state, is called the postamble. there are preamble and postamble specifications for both read and write operations in ddr3, ddr2, and ddr sdram. the dqs postamble circuitry ensures that data is not lost if there is noise on the dqs line during the end of a read operation that occurs while dqs is in a postamble state. stratix iv devices have dedicated postamble registers that you can control to ground the shifted dqs signal used to clock the dq input registers at the end of a read operation. this ensures that any glitches on the dqs input signals during the end of a read operation that occurs while dqs is in a postamble state do not affect the dq ioe registers. in addition to the dedicated postamble register, stratix iv devices also have an hdr block inside the postamble enable circuitry. use these registers if the controller is running at half the frequency of the i/os. using the hdr block as the first stage capture register in the postamble enable circuitry block is optional. the hdr block is clocked by the half-rate resynchronization clock, which is the output of the i/o clock divider circuit (shown in figure 7?31 on page 7?50 ). there is an and gate after the postamble register outputs that is used to avoid postamble glitches from a previous read burst on a non-consecutive read burst. this scheme allows a half-a-clock cycle latency for dqsenable assertion and zero latency for dqsenable de-assertion, as shown in figure 7?26 . figure 7?26. avoiding glitch on a non-consecutive read burst waveform delayed by 1/2t logic preamble postamble postamble glitch dqs postamble enable dqsenable chapter 7: external memory interfaces in stratix iv devices 7?47 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 leveling circuitry ddr3 sdram unbuffered modules use a fly-by clock distribution topology for better signal integrity. this means that the ck/ck# signals arrive at each ddr3 sdram device in the module at different times. the difference in arrival time between the first ddr3 sdram device and the last device on the module can be as long as 1.6 ns. figure 7?27 shows the clock topology in ddr3 sdram unbuffered modules. because the data and read strobe signals are still point-to-point, take special care to ensure that the timing relationship between the ck/ck# and dqs signals ( tdqss, tdss , and tdsh ) during a write is met at every device on the modules. furthermore, read data coming back into the fpga from the memory is also staggered in a similar way. stratix iv fpgas have leveling circuitry to address these two situations. there is one leveling circuitry per i/o sub-bank (for example, i/o sub-bank 1a, 1b, and 1c each has one leveling circuitry). these delay chains are pvt-compensated by the same dqs delay settings as the dll and dqs delay chains. for frequencies equal to and above 400 mhz, the dll uses eight delay chains, such that each delay chain generates a 45 delay. the generated clock phases are distributed to every dqs logic block that is available in the i/o sub-bank. the delay chain taps then feeds a multiplexer controlled by the altmemphy megafunction to select which clock phases are to be used for that 4 or 8 dqs group. each group can use a different tap output from the read-leveling and write-leveling delay chains to compensate for the different ck/ck# delay going into each device on the module. figure 7?27. ddr3 sdram unbuffered module clock topology dqs/dq dqs/dq dqs/dq dqs/dq dqs/dq dqs/dq ck/ck# stratix iv device dqs/dq dqs/dq 7?48 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?28 and figure 7?29 show the stratix iv write- and read-leveling circuitry. the ?90 write clock of the altmemphy megafunction feeds the write-leveling circuitry to produce the clock to generate the dqs and dq signals. during initialization, the altmemphy megafunction picks the correct write-leveled clock for the dqs and dq clocks for each dqs/dq group after sweeping all the available clocks in the write calibration process. the dq clock output is ?90 phase-shifted compared to the dqs clock output. similarly, the resynchronization clock feeds the read-leveling circuitry to produce the optimal resynchronization and postamble clock for each dqs/dq group in the calibration process. the resynchronization and postamble clocks can use different clock outputs from the leveling circuitry. the output from the read-leveling circuitry can also generate the half-rate resynchronization clock that goes to the fpga fabric. figure 7?28. stratix iv write-leveling delay chains and multiplexers (note 1) note to figure 7?28 : (1) there is one leveling delay chain per i/o sub-bank (for example, i/o sub-banks 1a, 1b, and 1c). you can only have one memory interface in each i/o sub-bank when you use the leveling delay chain. write clk (-90 0 ) write-leveled dqs clock write-leveled dq clock figure 7?29. stratix iv read-leveling delay chains and multiplexers (note 1) note to figure 7?29 : (1) there is one leveling delay chain per i/o sub-bank (for example, i/o sub-banks 1a, 1b, and 1c). you can only have one memory interface in each i/o sub-bank when you use the leveling delay chain. (2) each divider feeds up to six pins (from a 4 dqs group) in the device. to feed wider dqs groups, you must chain multiple clock dividers together by feeding the slaveout output of one divider to the masterin input of the neighboring pins? divider. dqs half-rate resynchronization clock read-leveled resynchronization clock half-rate source synchronous clock resynchronization clock (resync_clk_2x) 6 phasectrlin phaseinvertctrl delayctrlin 0111 0110 0100 0011 0010 0001 0000 0101 0 1 4 dff 0 1 0 1 slaveout masterin i/o clock divider (2) use_masterin phaseselect clkout chapter 7: external memory interfaces in stratix iv devices 7?49 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 1 the altmemphy megafunction dynamically calibrates the alignment for read and write-leveling during the initialization process. f for more information about the altmemphy megafunction, refer to the external memory phy interface (altmemphy) (nonafi) megafunction user guide . dynamic on-chip termination control figure 7?30 shows the dynamic oct control block. the block includes all the registers needed to dynamically turn on oct rt during a read and turn oct rt off during a write. f for more information about dynamic on-chip termination control, refer to the i/o features in stratix iv devices chapter. i/o element registers the ioe registers are expanded to allow source-synchronous systems to have faster register-to-register transfers and resynchronization. both top and bottom and left and right ioes have the same capability. left and right ioes have extra features to support lvds data transfer. figure 7?31 shows the registers available in the stratix iv input path. the input path consists of the ddr input registers, resynchronization registers, and hdr block. you can bypass each block of the input path. figure 7?30. stratix iv dynamic oct control block note to figure 7?30 : (1) the write clock comes from either the pll or the write-leveling delay chain. oct control write clock (1) oct enable resynchronization registers oct half- rate clock oct control path dff dff 2 hdr block 7?50 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation there are three registers in the ddr input registers block. two registers capture data on the positive and negative edges of the clock, while the third register aligns the captured data. you can choose to use the same clock for the positive edge and negative edge registers, or two complementary clocks (dqs/cq for the positive-edge register and dqsn/cqn for the negative-edge register). the third register that aligns the captured data uses the same clock as the positive edge registers. the resynchronization registers consist of up to three levels of registers to resynchronize the data to the system clock domain. these registers are clocked by the resynchronization clock that is either generated by the pll or the read-leveling delay chain. the outputs of the resynchronization registers can go straight to the core or to the hdr blocks, which are clocked by the divided-down resynchronization clock. for more information about the read-leveling delay chain, refer to ?leveling circuitry? on page 7?47 . figure 7?31. stratix iv ioe input registers (note 1) notes to figure 7?31 : (1) you can bypass each register block in this path. (2) this is the 0-phase resynchronization clock (from the read-leveling delay chain). (3) the input clock can be from the dqs logic block (whether th e postamble circuitry is bypassed or not) or from a global clock line. (4) this input clock comes from the cqn logic block. (5) this resynchronization clock comes from a pll through the clock network (resync_ck_2x). (6) the i/o clock divider resides adjacent to the dqs logic block. in addition to the pll and read-leveled resync clock, the i/o clock divider can also be fed by the dqs bus or cqn bus. (7) the half-rate data and clock signals feed into a dual-port ram in the fpga core. (8) you can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data rate register to feed dataout . (9) the dqs and dqsn signals must be inverted for ddr, ddr2, and ddr3 interfaces. when using altera?s memory interface ips, the dqs and dqsn signals are automatically inverted. (10) the bypass_output_register option allows you to select either the output from the second mux or the output of the fourth alignment/ synchronization register to feed dataout . 1 cqn (4) dff i dff input reg a input reg b neg_reg_out i i dq dq 0 dqs/cq (3), (9) dq input reg c dff dq double data rate input registers dqsn (9) differential input buffer dff dff dq dq dff dq dff dff dq dq dff dq alignment & synchronization registers half data rate registers to core dataout[2] (7) to core dataout [0] (7) to core dataout [3] (7) to core dataout [1] (7) to core (7) 0 1 dataoutbypass (8) (2) dff d q dff dq dff dq dff dq dff dq dff dq dff dq dff dq 0 1 chapter 7: external memory interfaces in stratix iv devices 7?51 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 figure 7?32 shows the registers available in the stratix iv output and output-enable paths. the path is divided into the hdr block, resynchronization registers, and output and output-enable registers. the device can bypass each block of the output and output-enable path. 7?52 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?32. stratix iv ioe output and output-enable path registers (note 1) notes to figure 7?32 : (1) you can bypass each register block of the output and output-enable paths. (2) data coming from the fpga core are at half the frequency of the memory interface clock frequency in half-rate mode. (3) the half-rate clock comes from the pll, while the alignment clock comes from the write-leveling delay chains. (4) these registers are only used in ddr3 sdram interfa ces for write-leveling purposes. (5) the write clock can come from either the pll or from the write-leveling delay chain. the dq write clock and dqs write clock have a 90 offset between them. alignment registers (4) dff dff dq dq dff dq dff dff dq dq dff dq half data rate to single data rate output registers dff dff dq dq dff dq half data rate to single data rate output-enable registers alignment registers (4) alignment clock (3) 0 1 0 1 0 1 from core (2) from core (2) from core (wdata2) (2) from core (wdata0) (2) from core (wdata3) (2) from core (wdata1) (2) dq dff dq dff 0 1 output reg ao output reg bo dq dff dq dff or2 tri oe reg b oe oe reg a oe 0 1 double data rate output-enable registers double data rate output registers dq or dqs write clock (5) half-rate clock (3) dff dq dff dq dff dq dff dq dff dq dff dq dff dq dff dq dff dq chapter 7: external memory interfaces in stratix iv devices 7?53 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 the output path is designed to route combinatorial or registered sdr outputs and full-rate or half-rate ddr outputs from the fpga core. half-rate data is converted to full-rate using the hdr block, clocked by the half-rate clock from the pll. the resynchronization registers are also clocked by the same 0 system clock, except in the ddr3 sdram interface. in ddr3 sdram interfaces, the leveling registers are clocked by the write-leveling clock. for more information about the write-leveling delay chain, refer to ?leveling circuitry? on page 7?47 . the output-enable path has a structure similar to the output path. you can have a combinatorial or registered output in sdr applications and you can use half-rate or full-rate operation in ddr applications. also, the ouput-enable path?s resynchronization registers have a structure similar to the output path registers, ensuring that the output-enable path goes through the same delay and latency as the output path. delay chain stratix iv devices have run-time adjustable delay chains in the i/o blocks and the dqs logic blocks. you can control the delay chain setting through the i/o or the dqs configuration block output. figure 7?33 shows the delay chain ports. every i/o block contains the following: figure 7?33. delay chain t datain dataout delayctrlin [3..0] t finedelayctrlin < use finedelayctrlin> 0 1 7?54 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation figure 7?34 shows the delay chains in an i/o block. each dqs logic block contains a delay chain after the dqsbusout output and another delay chain before the dqsenable input. figure 7?35 shows the delay chains in the dqs input path. figure 7?34. delay chains in an i/o block figure 7?35. delay chains in the dqs input path (ou tpu tdelaysetting2 + o u tpu tfinedelaysetting2) octdelaysetting1 (only) d5 oct delay chain rtena oe octdelaysetting2 (only) (ou tpu tdelaysetting1 + o u tpu tfinedelaysetting1) 0 1 (padtoinpu tregisterdelaysetting + padtoinpu tregisterfinedelaysetting) (ou tpu tdelaysetting2 + o u tpu tfinedelaysetting2) or (ou tpu tonlydelaysetting2 + o u tpu tonlyfinedelaysetting2) d6 oct delay chain d5 ou tpu t- enab le delay chain d6 ou tpu t- enab le delay chain d6 delay delay chain d5 delay delay chain d1 delay delay chain (dq s busou tdelaysetting + d q s busou tfinedelaysetting) d q s busou t (dq senab ledelaysetting + d q senab lefinedelaysetting) dqs delay chain dqs enab le control dqs enab le d q sin d q senab le dqs d4 delay chain t11 delay chain chapter 7: external memory interfaces in stratix iv devices 7?55 stratix iv external memory interface features ? march 2010 altera corporation stratix iv device handbook volume 1 i/o configuration block and dqs configuration block the i/o configuration block and the dqs configuration block are shift registers that you can use to dynamically change the settings of various device configuration bits. the shift registers power-up low. every i/o pin contains one i/o configuration register, while every dqs pin contains one dqs configuration block in addition to the i/o configuration register. figure 7?36 shows the i/o configuration block and the dqs configuration block circuitry. table 7?20 lists the i/o configuration block bit sequence. figure 7?36. i/o configuration block and dqs configuration block datain update ena clk dataout msb bit 0 bit 1 bit 2 table 7?20. i/o configuration block bit sequence bit bit name 0..3 outputdelaysetting1[0..3] 4..6 outputdelaysetting2[0..2] 7..10 padtoinputregisterdelaysetting[0..3] 11 outputfinedelaysetting1 12 outputfinedelaysetting2 13 padtoinputregisterfinedelaysetting 14 outputonlyfinedelaysetting2 15..17 outputonlydelaysetting2[2..0] 18 dutycyclecorrectionmode 19..22 dutycyclecorrectionsetting[3..0] 7?56 chapter 7: external memory interfaces in stratix iv devices stratix iv external memory interface features stratix iv device handbook volume 1 ? march 2010 altera corporation table 7?21 lists the dqs configuration block bit sequence. table 7?21. dqs configuration block bit sequence bit bit name 0..3 dqsbusoutdelaysetting[0..3] 4..6 dqsinputphasesetting[0..2] 7..10 dqsenablectrlphasesetting[0..3] 11..14 dqsoutputphasesetting[0..3] 15..18 dqoutputphasesetting[0..3] 19..22 resyncinputphasesetting[0..3] 23 dividerphasesetting 24 enaoctcycledelaysetting 25 enainputcycledelaysetting 26 enaoutputcycledelaysetting 27..29 dqsenabledelaysetting[0..2] 30..33 octdelaysetting1[0..3] 34..36 octdelaysetting2[0..2] 37 enadataoutbypass 38 enadqsenablephasetransferreg 39 enaoctphasetransferreg 40 enaoutputphasetransferreg 41 enainputphasetransferreg 42 resyncinputphaseinvert 43 dqsenablectrlphaseinvert 44 dqoutputphaseinvert 45 dqsoutputphaseinvert 46 dqsbusoutfinedelaysetting 47 dqsenablefinedelaysetting chapter 7: external memory interfaces in stratix iv devices 7?57 document revision history ? march 2010 altera corporation stratix iv device handbook volume 1 document revision history table 7?22 shows the revision history for this chapter. table 7?22. document revision history (part 1 of 2) date and document version changes made summary of changes march 2010 v3.1 updated figure 7?8 , figure 7?11 , figure 7?23, figure 7?24 , figure 7?29 , figure 7?31 , and figure 7?36 . added figure 7?9 , figure 7?12 added table 7?7 . updated tab le 7 ?1 , ta ble 7? 2 , table 7?3, tab le 7 ?4 , ta ble 7? 6, tab le 7 ?8 and tab le 7 ?1 9 . added note to the ?memory interfaces pin support? section. changed ?dll1 through dll4? to ?dll0 through dll3? throughout. added frequency mode 7 throughout. minor text edits. ? november 2009 v3.0 updated the ?memory interfaces pin support? and ?combining 16/18 dqs/dq groups for a 36 qdr ii+/qdr ii sram interface? sections. updated table 7?1, table 7?2, table 7?7, and table 7?12. updated figure 7?3, figure 7?4, figure 7?5, figure 7?6, figure 7?7, figure 7?8, figure 7?9, figure 7?10, figure 7?11, figure 7?13, figure 7?14, figure 7?15, and figure 7?16. added figure 7?12 and figure 7?17. added table 7?14, table 7?17, table 7?19, and table 7?20. added ?delay chain? and ?i/o configuration block and dqs configuration block? sections. removed figure 7-8 and figure 7-12. removed table 7-1, table 7-2, and table 7-24. minor text edits. ? june 2009 v2.3 updated ?overview? and ?leveling circuitry?. updated figure 7?26 and figure 7?27. updated table 7?3. added introductory sentences to improve search ability. removed the conclusion section. ? april 2009 v2.2 updated table 7?5, table 7?6, table 7?15, and table 7?17 removed figure 7-12, figure 7-13, and figure 7-20 ? 7?58 chapter 7: external memory interfaces in stratix iv devices document revision history stratix iv device handbook volume 1 ? march 2010 altera corporation march 2009 v2.1 updated table 7?1, table 7?5, table 7?8, table 7?12, table 7?13, table 7?14, table 7?15, and table 7?17. replaced table 7?6. added table 7?11 and table 7?16. updated figure 7?3, figure 7?6, figure 7?8, figure 7?9, and figure 7?11. added figure 7?7, figure 7?11, figure 7?12, figure 7?13, and figure 7?20. updated ?combining 16/18 dqs/dq groups for 36 qdr ii+/qdr ii sram interface? on page 7?26. updated ?rules to combine groups? on page 7?27. removed ?referenced documents? section. ? november 2008 v2.0 updated table 7?1, table 7?2, table 7?3, table 7?4, table 7?5, and tab le 7 ?6 . added table 7?7. updated figure 7?1. updated ?combining 16/18 dqs/dq groups for 36 qdr ii+/qdr ii sram interface? on page 7?26. updated ?rules to combine groups? on page 7?27. updated ?dqs phase-shift circuitry? on page 7?29. updated figure 7?19. updated table 7?9, table 7?10, table 7?11, table 7?13, table 7?13, table 7?14, table 7?15, table 7?15, table 7?16, and table 7?18. updated figure 7?30. updated figure 7?31. made minor editorial changes. ? may 2008 v1.0 initial release. ? table 7?22. document revision history (part 2 of 2) date and document version changes made summary of changes ? march 2010 altera corporation stratix iv device handbook volume 1 8. high-speed differential i/o interfaces and dpa in stratix iv devices this chapter describes the significant advantages of the high-speed differential i/o interfaces and the dynamic phase aligner (dpa) over single-ended i/os and their contribution to the overall system bandwidth achievable with stratix ? iv fpgas. all references to stratix iv devices in this chapter apply to stratix iv e, gt, and gx devices. the stratix iv device family consists of the stratix iv e (enhanced) devices without high-speed clock data recovery (cdr) based transceivers, stratix iv gt devices with up to 48 cdr-based transceivers running up to 11.3 gbps, and stratix iv gx devices with up to 48 cdr-based transceivers running up to 8.5 gbps. the following sections describe the stratix iv high-speed differential i/o interfaces and dpa in detail: overview all stratix iv e, gx, and gt devices have built-in serializer/deserializer (serdes) circuitry that supports high-speed lvds interfaces at data rates of up to 1.6 gbps. serdes circuitry is configurable to support source-synchronous communication protocols such as utopia, rapid i/o, xsbi, small form factor interface (sfi), serial peripheral interface (spi), and asynchronous protocols such as sgmii and gigabit ethernet. the stratix iv device family has the following dedicated circuitry for high-speed differential i/o support: siv51008-3.1 8?2 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices overview stratix iv device handbook volume 1 ? march 2010 altera corporation dpa synchronizer (fifo buffer) phase-locked loops (plls) (located on left and right sides of the device) for high-speed differential interfaces, the stratix iv device family supports the following differential i/o standards: lv ds mini-lvds reduced swing differential signaling (rsds) in the stratix iv device family, i/os are divided into row and column i/os. figure 8?1 shows i/o bank support for the stratix iv device family. the row i/os provide dedicated serdes circuitry. figure 8?1. i/o bank support in the stratix iv device family (note 1) , (2) , (3) , (4) notes to figure 8?1 : (1) column input buffers are true lvds buffers, but do not support 100- differential on-chip termination. (2) column output buffers are single ended and need external termination schemes to support lvds, mini-lvds, and rsds standards. for more information, refer to the i/o features in stratix iv devices chapter. (3) row input buffers are true lvds buffers and support 100- differential on-chip termination. (4) row output buffers are true lvds buffers. lvds i/os row i/os with dedicated serdes circuitry (3), (4) lvds interface with 'use external pll' option disabled lvds interface with 'use external pll' option enabled column i/os (1), (2) chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?3 locations of the i/o banks ? march 2010 altera corporation stratix iv device handbook volume 1 the altlvds transmitter and receiver requires various clock and load enable signals from a left or right pll. the quartus ? ii software provides the following two choices when configuring the lvds serdes circuitry when using the pll: use external pll option enabled?you control the pll settings, such as dynamically reconfiguring the pll to support different data rates, dynamic phase shift, and so on. you must enable the use external pll option in the altlvds megafunction, using the altlvds megawizard ? , 8 use external pll option disabled?the quartus ii software configures the pll settings automatically. the software is also responsible for generating the various clock and load enable signals based on the input reference clock and data rate selected. 1 cc r c ffrc f rv w rfc use external pll option enabled. locations of the i/o banks stratix iv i/os are divided into 16 to 24 i/o banks. the dedicated circuitry that supports high-speed differential i/os is located in banks in the right and left side of the device. figure 8?2 shows a high-level chip overview of the stratix iv e device. figure 8?2. high-speed differential i/os with dpa locations in stratix iv e devices fpga fabric (logic elements, dsp, embedded memory, pll pll pll general purpose i/o and memory interface general purpose i/o and memory interface general purpose i/o and memory interface general purpose i/o and memory interface pll pll pll pll pll pll pll pll clock networks) pll general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr 8?4 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices lvds channels stratix iv device handbook volume 1 ? march 2010 altera corporation figure 8?3 shows a high-level chip overview of the stratix iv gt and gx devices. lvds channels the stratix iv device family supports lvds on both row and column i/o banks. row i/os support true lvds input with 100- , , , , , 1 ffr ffr r r c r w r fwr vr 1 1 r f rw c r r vc c r ffr r ffr c f w c c figure 8?3. high-speed differential i/os with dpa locations in stratix iv gt and gx devices pci express hard ip block fpga fabric (logic elements, dsp, embedded memory, pll pll pll general purpose i/o and memory interface general purpose i/o and memory interface general purpose i/o and memory interface general purpose i/o and memory interface transceiver block transceiver block transceiver block transceiver block pci express hard ip block pci express hard ip block pci express hard ip block pll pll pll pll pll pll pll pll clock networks) pll transceiver block transceiver block transceiver block transceiver block general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?5 lvds channels ? march 2010 altera corporation stratix iv device handbook volume 1 for example, there are a total of 112 lvds pairs on row i/os in the 780-pin ep4se230 device (refer to table 8?1 ). you can design up to a maximum of 56 true lvds input buffers and 56 true lvds output buffers, or up to a maximum of 112 emulated lvds output buffers. for the 780-pin ep4se230 device (refer to table 8?2 ), there are a total of 128 lvds pairs on column i/os. you can design up to a maximum of 64 true lvds input buffers and 64 emulated lvds output buffers, or up to a maximum of 128 emulated lvds output buffers. tab le 8 ?1 . lvds channels supported in stratix iv e device row i/o banks (note 1) , (2) , (3) device 780-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga 1760- pin fineline bga ep4se230 56 rx or etx + 56 tx or etx ??? ep4se360 56 rx or etx + 56 tx or etx (4) 88 rx or etx + 88 tx or etx ?? ep4se530 ? 88 rx or etx + 88 tx or etx (5) 112 rx or etx + 112 tx or etx (6) 112 rx or etx + 112 tx or etx ep4se820 ? 88 rx or etx + 88 tx or etx 112 rx or etx + 112 tx or etx 132 rx or etx + 132 tx or etx notes to ta bl e 8? 1 : (1) rx = true lvds input buffers with oct r d , tx = true lvds output buffers, etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channels are equally divided between the left and right sides of the device. (3) the lvds channel count does not include dedicated clock input pins. (4) ep4se360 devices are offered in the h780 package instead of the f780 package. (5) ep4se530 devices are offered in the h1152 package instead of the f1152 package. (6) ep4se530 devices are offered in the h1517 package instead of the f1517 package. tab le 8 ?2 . lvds channels supported in stratix iv e device column i/o banks (note 1) , (2) , (3) device 780-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga 1760-pin fineline bga ep4se230 64 rx or etx + 64 etx ? ? ? ep4se360 64 rx or etx + 64 etx (4) 96 rx or etx + 96 etx ? ? ep4se530 ? 96 rx or etx + 96 etx (5) 128 rx or etx + 128 etx (6) 128 rx or etx + 128 etx ep4se820 ? 96 rx or etx + 96 etx 128 rx or etx + 128 etx 144 rx or etx + 144 etx notes to ta bl e 8? 2 : (1) rx = true lvds input buffers without oct r d , etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channels are equally divided between the top and bottom sides of the device. (3) the lvds channel count does not include dedicated clock input pins. (4) ep4se360 devices are offered in the h780 package instead of the f780 package. (5) ep4se530 devices are offered in the h1152 package instead of the f1152 package. (6) ep4se530 devices are offered in the h1517 package instead of the f1517 package. 8?6 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices lvds channels stratix iv device handbook volume 1 ? march 2010 altera corporation table 8?3 and table 8?4 list the maximum number of row and column lvds i/os supported in stratix iv gt devices. table 8?5 and table 8?6 list the maximum number of row and column lvds i/os supported in stratix iv gx devices. tab le 8 ?3 . lvds channels supported in stratix iv gt device row i/o banks (note 1) , (2) device 1517-pin fineline bga 1932-pin fineline bga ep4s40g2 46 rx or etx + 73 tx or etx ? ep4s40g5 46 rx or etx + 73 tx or etx ? ep4s100g2 46 rx or etx + 73 tx or etx ? ep4s100g3 ? 47 rx or etx + 56 tx or etx ep4s100g4 ? 47 rx or etx + 56 tx or etx ep4s100g5 46 rx or etx + 73 tx or etx 47 rx or etx + 56 tx or etx notes to ta bl e 8? 3 : (1) rx = true lvds input buffers with oct r d , etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channel count does not include dedicated clock input pins. tab le 8 ?4 . lvds channels supported in stratix iv gt device column i/o banks (note 1) , (2) device 1517-pin fineline bga 1932-pin fineline bga ep4s40g2 96 rx or etx + 96 etx ? ep4s40g5 96 rx or etx + 96 etx ? ep4s100g2 96 rx or etx + 96 etx ? ep4s100g3 ? 128 rx or etx + 128 etx ep4s100g4 ? 128 rx or etx + 128 etx ep4s100g5 96 rx or etx + 96 etx 128 rx or etx + 128 etx notes to ta bl e 8? 4 : (1) rx = true lvds input buffers without oct r d , etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channel count does not include dedicated clock input pins. tab le 8 ?5 . lvds channels supported in stratix iv gx device row i/o banks (note 1) , (2) , (3) (part 1 of 2) device 780-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga (4) 1517-pin fineline bga 1760-pin fineline bga 1932-pin fineline bga ep4sgx70 28 rx or etx + 28 tx or etx ? 56 rx or etx + 56 tx or etx ??? ep4sgx110 28 rx or etx + 28 tx or etx 28 rx or etx + 28 tx or etx 56 rx or etx + 56 tx or etx ??? ep4sgx180 28 rx or etx + 28 tx or etx 44 rx or etx + 44 tx or etx 44 rx or etx + 44 tx or etx 88 rx or etx + 88 tx or etx ?? ep4sgx230 28 rx or etx + 28 tx or etx 44 rx or etx + 44 tx or etx 44 rx or etx + 44 tx or etx 88 rx or etx + 88 tx or etx ?? ep4sgx290 ? (5) 44 rx or etx + 44 tx or etx 44 rx or etx + 44 tx or etx 88 rx or etx + 88 tx or etx 88 rx or etx + 88 tx or etx 98 rx or etx + 98 tx or etx chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?7 lvds channels ? march 2010 altera corporation stratix iv device handbook volume 1 ep4sgx360 ? (5) 44 rx or etx + 44 tx or etx 44 rx or etx + 44 tx or etx 88 rx or etx + 88 tx or etx 88 rx or etx + 88 tx or etx 98 rx or etx + 98 tx or etx ep4sgx530 ? ? 44 rx or etx + 44 tx or etx (6) 88 rx or etx + 88 tx or etx (7) 88 rx or etx + 88 tx or etx 98 rx or etx + 98 tx or etx notes to ta bl e 8? 5 : (1) rx = true lvds input buffers with oct r d , tx = true lvds output buffers, etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channels are equally divided between the left and right sides of the device, except for the devices in th e 780-pin fineline bga. these devices have the lvds rx and tx located on the left side of the device. (3) the lvds channel count does not include dedicated clock input pins. (4) this package supports pma-only transceiver channels. (5) ep4sgx290 and ep4sgx360 devices are offered in the h780 package instead of the f780 package. (6) ep4sgx530 devices are offered in the h1152 package instead of the f1152 package. (7) ep4sgx530 devices are offered in the h1517 package instead of the f1517 package. tab le 8 ?5 . lvds channels supported in stratix iv gx device row i/o banks (note 1) , (2) , (3) (part 2 of 2) device 780-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga (4) 1517-pin fineline bga 1760-pin fineline bga 1932-pin fineline bga tab le 8 ?6 . lvds channels supported in stratix iv gx device column i/o banks (note 1) , (2) , (3) device 780-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga (4) 1517-pin fineline bga 1760-pin fineline bga 1932-pin fineline bga ep4sgx70 64 rx or etx + 64 etx ? 64 rx or etx + 64 etx ??? ep4sgx110 64 rx or etx + 64 etx 64 rx or etx + 64 etx 64 rx or etx + 64 etx ??? ep4sgx180 64 rx or etx + 64 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx ?? ep4sgx230 64 rx or etx + 64 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx ?? ep4sgx290 72 rx or etx + 72 etx (5) 96 rx or etx + 96 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx 128 rx or etx + 128 etx 128 rx or etx + 128 etx ( 8 ) ep4sgx360 72 rx or etx + 72 etx (5) 96 rx or etx + 96 etx 96 rx or etx + 96 etx 96 rx or etx + 96 etx 128 rx or etx + 128 etx 128 rx or etx + 128 etx ( 8 ) ep4sgx530 ? ? 96 rx or etx + 96 etx (6) 96 rx or etx + 96 etx (7) 128 rx or etx + 128 etx 128 rx or etx + 128 etx notes to ta bl e 8? 6 : (1) rx = true lvds input buffers without oct r d , etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r ). (2) the lvds rx and tx channels are equally divided between the left and right sides of the device. (3) the lvds channel count does not include dedicated clock input pins. (4) this package supports pma-only transceiver channels. (5) ep4sgx290 and ep4sgx360 devices are offered in the h780 package instead of the f780 package. (6) ep4sgx530 devices are offered in the h1152 package instead of the f1152 package. (7) ep4sgx530 devices are offered in the h1517 package instead of the f1517 package. (8) the quartus ii software version 9.0 does not support ep4sgx290 and ep4sgx360 devices in the 1932-pin fineline bga package. t hese devices will be supported in a future release of the quartus ii software. 8?8 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices lvds serdes stratix iv device handbook volume 1 ? march 2010 altera corporation lvds serdes figure 8?4 shows a transmitter and receiver block diagram for the lvds serdes circuitry in the left and right banks. this diagram shows the interface signals of the transmitter and receiver data path. for more information, refer to ?differential transmitter? on page 8?11 and ?differential receiver? on page 8?16 . figure 8?4. lvds serdes (note 1) , (2) , (3) notes to figure 8?4 : (1) this diagram shows a shared pll between the transmitter and receiver. if the transmitter and receiver are not sharing the sa me pll, the two left and right plls are required. (2) in sdr and ddr modes, the data width is 1 and 2 bits, respectively. (3) the tx_in and rx_out ports have a maximum data width of 10 bits. + - + - ioe tx_in 10 serializer 2 ioe ioe supports sdr, ddr, or non-registered datapath din dout lvds transmitter lvds receiver tx_coreclock tx_out rx_in dpa circuitry synchronizer din retimed data dpa clock din dout din dout din dout deserializer bit slip 2 3 (lvds_load_en, diffioclk, tx_coreclock) ioe supports sdr, ddr, or non-registered datapath fpga fabric 10 rx_out (load_en, diffioclk) 2 diffioclk clock mux rx_divfwdclk rx_outclock left/right pll rx_inclock/tx_inclock (lvds_load_en, lvds_diffioclk, rx_outclock 3 lvds_diffioclk dpa_diffioclk 3 (dpa_load_en, dpa_diffioclk, rx_divfwdclk) 8 serial lvds clock phases lvds clock domain dpa clock domain chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?9 altlvds port list ? march 2010 altera corporation stratix iv device handbook volume 1 altlvds port list table 8?7 lists the interface signals for an lvds transmitter and receiver. tab le 8 ?7 . port list of the lvds interface (altlvds) (note 1) , (2) (part 1 of 3) port name input / output description pll signals pll_areset input asynchronous reset to the lvds transmitter and receiver pll. the minimum pulse width requirement for this signal is 10 ns. lvds transmitter interface signals tx_in[ ] input the data bus width per channel is the same as the serialization factor (sf). input data must be synchronous to the tx_coreclock signal. tx_inclock input reference clock input for the transmitter pll. the altlvds megawizard plug-in manager sofware automatically selects the appropriate pll multiplication factor based on the data rate and reference clock frequency selection. for more information about the allowed frequency range for this reference clock, refer to the ?high-speed i/o specification? section in the dc and switching characteristics chapter. tx_enable (3) input this port is instantiated only when you select the use external pll option in the megawizard plug-in manager software. this input port must be driven by the pll instantiated though the altpll megawizard plug-in manager software. tx_out output lvds transmitter serial data output port. tx_out is clocked by a serial clock generated by the left and right pll. tx_outclock output the frequency of this clock is programmable to be the same as the data rate, half the data rate, or one-fourth the data rate. the phase offset of this clock, with respect to the serial data, is programmable in increments of 45. tx_coreclock (3) output fpga fabric-transmitter interface clock. the parallel transmitter data generated in the fpga fabric must be clocked with this clock. this port is not available when you select the use external pll option in the megawizard plug-in manager software. the fpga fabric-transmitter interface clock must be driven by the pll instantiated through the altpll megawizard plug-in manager software. tx_locked output when high, this signal indicates that the transmitter pll is locked to the input reference clock. 8?10 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices altlvds port list stratix iv device handbook volume 1 ? march 2010 altera corporation lvds receiver interface signals rx_in input lvds receiver serial data input port. rx_inclock input reference clock input for the receiver pll. the altlvds megawizard plug-in manager sofware automatically selects the appropriate pll multiplication factor based on the data rate and reference clock frequency selection. for more information about the allowed frequency range for this reference clock, refer to the ?high-speed i/o specification? section in the dc and switching characteristics chapter. rx_channel_data_align input edge-sensitive bit-slip control signal. each rising edge on this signal causes the data re-alignment circuitry to shift the word boundary by one bit. the minimum pulse width requirement is one parallel clock cycle. there is no maximum pulse width requirement. rx_dpll_hold input when low, the dpa tracks any dynamic phase variations between the clock and data. when high, the dpa holds the last locked phase and does not track any dynamic phase variations between the clock and data. this port is not available in non-dpa mode. rx_enable (3) input this port is instantiated only when you select the use external pll option in the megawizard plug-in manager software. this input port must be driven by the pll instantiated though the altpll megawizard plug-in manager software. rx_out[ ] output receiver parallel data output. the data bus width per channel is the same as the deserialization factor (df). the output data is synchronous to the rx_outclock signal in non-dpa and dpa modes. it is synchronous to the rx_divfwdclk signal in soft-cdr mode. rx_outclock output parallel output clock from the receiver pll. the parallel data output from the receiver is synchronous to this clock in non-dpa and dpa modes. this port is not available when you select the use external pll option in the megawizard plug-in manager software. the fpga fabric-receiver interface clock must be driven by the pll instantiated through the altpll megawizard plug-in manager software. rx_locked output when high, this signal indicates that the receiver pll is locked to rx_inclock . rx_dpa_locked output this signal only indicates an initial dpa lock condition to the optimum phase after power up or reset. this signal is not de-asserted if the dpa selects a new phase out of the eight clock phases to sample the received data. you must not use the rx_dpa_locked signal to determine a dpa loss-of-lock condition. rx_cda_max output data re-alignment (bit slip) roll-over signal. when high for one parallel clock cycle, this signal indicates that the user-programmed number of bits for the word boundary to roll-over have been slipped. rx_divfwdclk output parallel dpa clock to the fpga fabric logic array. the parallel receiver output data to the fpga fabric logic array is synchronous to this clock in soft-cdr mode. this signal is not available in non-dpa and dpa modes. dpa_pll_recal input enable pll calibration dynamically without resetting the dpa circuitry or the pll. tab le 8 ?7 . port list of the lvds interface (altlvds) (note 1) , (2) (part 2 of 3) port name input / output description chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?11 differential transmitter ? march 2010 altera corporation stratix iv device handbook volume 1 f for more information about the lvds transmitter and receiver settings using altlvds, refer to the altlvds megafunction user guide . differential transmitter the stratix iv transmitter has a dedicated circuitry to provide support for lvds signaling. the dedicated circuitry consists of a differential buffer, a serializer, and left and right plls that can be shared between the transmitter and receiver. the differential buffer can drive out lvds, mini-lvds, and rsds signaling levels. the serializer takes up to 10 bits wide parallel data from the fpga fabric, clocks it into the load registers, and serializes it using shift registers clocked by the left and right pll before sending the data to the differential buffer. the msb of the parallel data is transmitted first. 1 when using emulated lvds i/o standards at the differential transmitter, the serdes circuitry must be implemented in logic cells but not hard serdes. the load enable ( lvds_load_en ) signal and the diffioclk signal (the clock running at serial data rate) generated from the pll_lx (left pll) or pll_rx (right pll) clocks the load and shift registers. you can statically set the serialization factor to 4, 6, 7, 8, or 10 using the quartus ii software. the load enable signal is derived from the serialization factor setting. figure 8?5 shows a block diagram of the stratix iv transmitter. dpa_pll_cal_busy output busy signal that is asserted high when the pll calibration occurs. reset signals rx_reset input asynchronous reset to the dpa circuitry and fifo. the minimum pulse width requirement for this reset is one parallel clock cycle. this signal resets dpa and fifo blocks. rx_fifo_reset input asynchronous reset to the fifo between the dpa and the data realignment circuits. the synchronizer block must be reset after a dpa loses lock condition and the data checker shows corrupted received data. the minimum pulse width requirement for this reset is one parallel clock cycle. this signal resets the fifo block. rx_cda_reset input asynchronous reset to the data realignment circuitry. the minimum pulse width requirement for this reset is one parallel clock cycle. this signal resets the data realignment block. notes to ta bl e 8? 7 : (1) unless stated, signals are valid in all three modes (non-dpa, dpa, and soft-cdr) for a single channel. (2) all reset and control signals are active high. (3) for more information, refer to ?lvds interface with the use external pll option enabled? on page 8?25 . tab le 8 ?7 . port list of the lvds interface (altlvds) (note 1) , (2) (part 3 of 3) port name input / output description 8?12 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices differential transmitter stratix iv device handbook volume 1 ? march 2010 altera corporation you can configure any stratix iv transmitter data channel to generate a source-synchronous transmitter clock output. this flexibility allows the placement of the output clock near the data outputs to simplify board layout and reduce clock-to-data skew. different applications often require specific clock-to-data alignments or specific data-rate-to-clock-rate factors. the transmitter can output a clock signal at the same rate as the data with a maximum frequency of 800 mhz. the output clock can also be divided by a factor of 1, 2, 4, 6, 8, or 10, depending on the serialization factor. you can set the phase of the clock in relation to the data at 0 or 180 (edge or center aligned). the left and right plls ( pll_lx and pll_rx ) provide additional support for other phase shifts in 45 increments. these settings are made statically in the quartus ii megawizard plug-in manager software. figure 8?6 shows the stratix iv transmitter in clock output mode. in clock output mode, you can use an lvds channel as a clock output channel. figure 8?5. stratix iv transmitter (note 1) , (2) notes to figure 8?5 : (1) in sdr and ddr modes, the data width is 1 and 2 bits, respectively. (2) the tx_in port has a maximum data width of 10 bits. figure 8?6. stratix iv transmitter in clock output mode tx_coreclock fpga fabric tx_in 10 serializer 2 ioe lvds transmitter ioe supports sdr, ddr, or non-registered datapath left/right pll tx_inclock (lvds_load_en, diffioclk, tx_coreclock) 3 lvds clock domain din dout + - tx_out transmitter circuit diffioclk lvds_load_en txclkout? txclkout+ parallel series fpga fabric left/right pll chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?13 differential transmitter ? march 2010 altera corporation stratix iv device handbook volume 1 you can bypass the stratix iv serializer to support ddr (2) and sdr (1) operations to achieve a serialization factor of 2 and 1, respectively. the i/o element (ioe) contains two data output registers that can each operate in either ddr or sdr mode. figure 8?7 shows the serializer bypass path. programmable v od and programmable pre-emphasis stratix iv lvds transmitters support programmable pre-emphasis and programmable v od . pre-emphasis increases the amplitude of the high-frequency component of the output signal, and thus helps to compensate for the frequency-dependent attenuation along the transmission line. figure 8?8 shows the differential lvds output. figure 8?7. stratix iv serializer bypass (note 1) , (2) , (3) notes to figure 8?7 : (1) all disabled blocks and signals are grayed out. (2) in ddr mode, tx_inclock clocks the ioe register. in sdr mode, data is directly passed through the ioe. (3) in sdr and ddr modes, the data width to the ioe is 1 and 2 bits, respectively. + - tx_coreclock tx_coreclock fpga fabr ic tx_in 2 serializer serializer 2 ioe din din dout dout lvds transmitter ioe supports sdr, ddr, or non-registered datapath tx_out left/right pll left/right pll (lvds_load_en, diffioclk, tx_coreclock) (lvds_load_en, diffioclk, tx_coreclock) 3 figure 8?8. differential v od single-ended waveform positive channel (p) negative channel (n) ground differential waveform p - n = 0v v od v od v od v cm v od (diff peak - peak) = 2 x v od (single-ended) 8?14 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices differential transmitter stratix iv device handbook volume 1 ? march 2010 altera corporation figure 8?9 shows the lvds output with pre-emphasis. pre-emphasis is an important feature for high-speed transmission. without pre-emphasis, the output current is limited by the v od setting and the output impedance of the driver. at high frequency, the slew rate may not be fast enough to reach full v od before the next edge, producing pattern-dependent jitter. with pre-emphasis, the output current is boosted momentarily during switching to increase the output slew rate. the overshoot introduced by the extra current happens only during switching and does not ring, unlike the overshoot caused by signal reflection. the amount of pre-emphasis needed depends on the attenuation of the high-frequency component along the transmission line. the quartus ii software allows four settings for programmable pre-emphasis?zero ( 0 ), low (1 ), medium ( 2 ), and high ( 3 ). the default setting is low. the v od is also programmable with four settings: low ( 0 ), medium low ( 1 ), medium high ( 2 ), and high ( 3 ). the default setting is medium low. programmable v od you can statically assign the v od settings from the assignment editor. table 8?8 lists the assignment name for programmable v od and its possible values in the quartus ii software assignment editor. figure 8?9. programmable pre-emphasis (note 1) note to figure 8?9 : (1) v p ? voltage boost from pre-emphasis. v od ? differential output voltage (peak-peak). tab le 8 ?8 . quartus ii software assignment editor to tx_out assignment name programmable differential output voltage (v od ) allowed values 0, 1, 2, 3 out out v od v p v p chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?15 differential transmitter ? march 2010 altera corporation stratix iv device handbook volume 1 figure 8?10 shows the assignment of programmable v od for a transmit data output from the quartus ii software assignment editor. programmable pre-emphasis four different settings are allowed for pre-emphasis from the assignment editor for each lvds output channel. table 8?9 lists the assignment name and its possible values for programmable pre-emphasis in the quartus ii software assignment editor. figure 8?10. quartus ii software assignment editor?programmable v od tab le 8 ?9 . quartus ii software assignment editor to tx_out assignment name programmable pre-emphasis allowed values 0, 1, 2, 3 8?16 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices differential receiver stratix iv device handbook volume 1 ? march 2010 altera corporation figure 8?11 shows the assignment of programmable pre-emphasis for a transmit data output port from the quartus ii software assignment editor. differential receiver the stratix iv device family has a dedicated circuitry to receive high-speed differential signals in row i/os. figure 8?12 shows the hardware blocks of the stratix iv receiver. the receiver has a differential buffer and left and right plls that can be shared between the transmitter and receiver, a dpa block, a synchronizer, a data realignment block, and a deserializer. the differential buffer can receive lvds, mini-lvds, and rsds signal levels, which are statically set in the quartus ii software assignment editor. the left and right pll receives the external clock input and generates different phases of the same clock. the dpa block chooses one of the clocks from the left and right pll and aligns the incoming data on each channel. the synchronizer circuit is a 1 bit wide by 6 bit deep fifo buffer that compensates for any phase difference between the dpa clock and the data realignment block. if necessary, the user-controlled data realignment circuitry inserts a single bit of latency in the serial bit stream to align to the word boundary. the deserializer includes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logic. the stratix iv device family supports three different receiver modes: figure 8?11. quartus ii software assignment editor ? programmable pre-emphasis chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?17 differential receiver ? march 2010 altera corporation stratix iv device handbook volume 1 the physical medium connecting the transmitter and receiver lvds channels may introduce skew between the serial data and the source-synchronous clock. the instantaneous skew between each lvds channel and the clock also varies with the jitter on the data and clock signals as seen by the receiver. the three different modes? non-dpa, dpa, and soft-cdr?provide different options to overcome skew between the source synchronous clock (non-dpa, dpa) /reference clock (soft-cdr) and the serial data. 1 rr w w c c w rc cr cc rcv r c w crcr c c c fr w w rc cr cc rcv r f rv r fr cr cr c fr cc r rc rr c fr rc figure 8?12. receiver block diagram (note 1) , (2) notes to figure 8?12 : (1) in sdr and ddr modes, the data width from the ioe is 1 and 2 bits, respectively. (2) the rx_out port has a maximum data width of 10 bits. ioe 2 deserializer bit slip synchronizer dpa circuitry 2 clock mux 8 serial lvds clock phases left/right pll rx_inclock lvds clock domain dpa clock domain 10 dout din dout din dout din din retimed data dpa clock lvds_diffiioclk dpa_diffioclk 3 (dpa_load_en, dpa_diffioclk, rx_divfwdclk) (lvds_load_en, lvds_diffioclk, rx_outclk) 3 (load_en, diffioclk) diffioclk rx_out rx_divfwdclk rx_outclock rx_in + fpga fabric lvds receiver ioe supports sdr, ddr, or non-registered datapath 8?18 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices differential receiver stratix iv device handbook volume 1 ? march 2010 altera corporation differential i/o termination the stratix iv device family provides a 100- , clk[0,2,9,11] ). it is not supported for column i/o pins, dedicated clock input pins ( clk[1,3,8,10] ), or the corner pll clock inputs. figure 8?13 shows device on-chip termination. receiver hardware blocks the differential receiver has the following hardware blocks: dpa block the dpa block takes in high-speed serial data from the differential input buffer and selects one of the eight phases generated by the left and right pll to sample the data. the dpa chooses a phase closest to the phase of the serial data. the maximum phase offset between the received data and the selected phase is 1/8 ui, which is the maximum quantization error of the dpa. the eight phases of the clock are equally divided, offering a 45 resolution. figure 8?13. on-chip differential i/o termination lvds transmitter stratix iv differential receiver with on-chip 100 termination r d z 0 = 50 z 0 = 50 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?19 differential receiver ? march 2010 altera corporation stratix iv device handbook volume 1 figure 8?14 shows the possible phase relationships between the dpa clocks and the incoming serial data. the dpa block continuously monitors the phase of the incoming serial data and selects a new clock phase if needed. you can prevent the dpa from selecting a new clock phase by asserting the optional rx_dpll_hold port, which is available for each channel. dpa circuitry does not require a fixed training pattern to lock to the optimum phase out of the eight phases. after reset or power up, dpa circuitry requires transitions on the received data to lock to the optimum phase. an optional output port, rx_dpa_locked , is available to indicate an initial dpa lock condition to the optimum phase after power up or reset. this signal is not de-asserted if the dpa selects a new phase out of the eight clock phases to sample the received data. do not use the rx_dpa_locked signal to determine a dpa loss-of-lock condition. use data checkers such as a cyclic redundancy check (crc) or diagonal interleaved parity (dip-4) to validate the data. an independent reset port, rx_reset , is available to reset the dpa circuitry. dpa circuitry must be retrained after reset. 1 c synchronizer the synchronizer is a 1 bit wide and 6 bit deep fifo buffer that compensates for the phase difference between dpa_diffioclk , which is the optimal clock selected by the dpa block, and lvds_diffioclk , which is produced by the left and right pll. the synchronizer can only compensate for phase differences, not frequency differences between the data and the receiver?s input reference clock. figure 8?14. dpa clock phase to serial data timing relationship (note 1) note to figure 8?14 : (1) t vco is defined as the pll serial clock period. 45? 90? 135? 180? 225? 270? 315? 0.125t vco t vco 0? rx_in d0 d1 d2 d3 d4 dn 8?20 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices differential receiver stratix iv device handbook volume 1 ? march 2010 altera corporation an optional port, rx_fifo_reset , is available to the internal logic to reset the synchronizer. the synchronizer is automatically reset when the dpa first locks to the incoming data. altera recommends using rx_fifo_reset to reset the synchronizer when the dpa signals a loss-of-lock condition and the data checker indicates corrupted received data. 1 crr crc f data realignment block (bit slip) skew in the transmitted data along with skew added by the link causes channel-to-channel skew on the received serial data streams. if the dpa is enabled, the received data is captured with different clock phases on each channel. this may cause the received data to be misaligned from channel to channel. to compensate for this channel-to-channel skew and establish the correct received word boundary at each channel, each receiver channel has a dedicated data realignment circuit that realigns the data by inserting bit latencies into the serial stream. an optional rx_channel_data_align port controls the bit insertion of each receiver independently controlled from the internal logic. the data slips one bit on the rising edge of rx_channel_data_align . the requirements for the rx_channel_data_align signal include: rx_channel_data_align. figure 8?15 shows receiver output ( rx_out ) after one bit slip pulse with the deserialization factor set to 4. the data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. the programmable bit rollover point can be from 1 to 11 bit-times, independent of the deserialization factor. the programmable bit rollover point must be set equal to or greater than the deserialization factor, allowing enough depth in the word alignment circuit to slip through a full word. you can set the value of the bit rollover point using the megawizard plug-in manager software. an optional status port, rx_cda_max , is available to the fpga fabric from each channel to indicate when the preset rollover point is reached. figure 8?15. data realignment timing rx_in rx_outclock rx_channel_data_align rx_out rx_inclock 3 3210 321x xx21 0321 2 1 0 3 2 1 0 3 2 1 0 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?21 differential receiver ? march 2010 altera corporation stratix iv device handbook volume 1 figure 8?16 shows a preset value of four bit-times before rollover occurs. the rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has occurred. deserializer you can statically set the deserialization factor to 4, 6, 7, 8, or 10 by using the quartus ii software. you can bypass the stratix iv deserializer in the quartus ii megawizard plug-in manager software to support ddr (2) or sdr (1) operations, as shown figure 8?17 . the dpa and data realignment circuit cannot be used when the deserializer is bypassed. the ioe contains two data input registers that can operate in ddr or sdr mode. figure 8?16. receiver data re-alignment rollover rx_outclock rx_channel_data_align rx_cda_max rx_inclock figure 8?17. stratix iv deserializer bypass (note 1) , (2) , (3) notes to figure 8?17 : (1) all disabled blocks and signals are grayed out. (2) in ddr mode, rx_inclock clocks the ioe register. in sdr mode, data is directly passed through the ioe. (3) in sdr and ddr modes, the data width from the ioe is 1 and 2 bits, respectively. ioe 2 dese ri a liz e r deserializer b it slip synchronizer dpa circ uitr y 2 c lock m u x 8 s erial l vd s c lock phase s left/right pll left/right pll 2 dout din dout din do u t din din r etime d d at a dpa c lock l vd s_ diffiiocl k dpa _ di ff iocl k 3 ( dpa_l o ad_en , d pa_diffioclk , rx_divfwdclk ) (l vd s _l o ad_en, l vds_diffioclk , rx_outclk ) 3 ( load_e n, diffioclk ) di ff iocl k rx_out r x _ div f wdcl k rx_outc l oc k rx_in + fpga fabric lvds receiver ioe su pports sdr, ddr, or non-registered datapath 8?22 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices differential receiver stratix iv device handbook volume 1 ? march 2010 altera corporation receiver data path modes the stratix iv device family supports three receiver datapath modes?non-dpa mode, dpa mode, and soft-cdr mode. non-dpa mode figure 8?18 shows the non-dpa datapath block diagram. in non-dpa mode, the dpa and synchronizer blocks are disabled. input serial data is registered at the rising or falling edge of the serial lvds_diffioclk clock produced by the left and right pll. you can select the rising/falling edge option using the altldvs megawizard plug-in manager software. both data realignment and deserializer blocks are clocked by the lvds_diffioclk clock, which is generated by the left and right pll. figure 8?18. receiver data path in non-dpa mode (note 1) , (2) notes to figure 8?18 : (1) in sdr and ddr modes, the data width from the ioe is 1 and 2 bits, respectively. (2) the rx_out port has a maximum data width of 10 bits . 2 deserializer bit slip synchroni z er d p a circuitr p p y 2 clock mux 8 s e r ial l vds l l c loc k phases left/right pll rx_inclock lvds clock domain 10 dout din dout din do u t din n din r etimed d ata dp a cloc p p k l vds_diffiioclk l l d p a_diffioclk p p 3 (dp a_lo p p a d_en , dp a_diffioclk, p p rx_divfwdclk ) (lvds_load_en, lvds_diffioclk, rx_outclk) 3 (load_en, diffioclk) diffioclk rx_out r x _ div f wdclk rx_outclock rx_in + fpga fabric lvds receiver i o e s uppo r t s s dr, ddr, or non-registered datapat h i o e chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?23 differential receiver ? march 2010 altera corporation stratix iv device handbook volume 1 dpa mode figure 8?19 shows the dpa mode datapath, where all the hardware blocks mentioned in ?receiver hardware blocks? on page 8?18 are active. the dpa block chooses the best possible clock ( dpa_diffioclk ) from the eight fast clocks sent by the left and right pll. this serial dpa_diffioclk clock is used for writing the serial data into the synchronizer. a serial lvds_diffioclk clock is used for reading the serial data from the synchronizer. the same lvds_diffioclk clock is used in data realignment and deserializer blocks. figure 8?19. receiver datapath in dpa mode (note 1) , (2) , (3) notes to figure 8?19 : (1) all disabled blocks and signals are grayed out. (2) in sdr and ddr modes, the data width from the ioe is 1 and 2 bits, respectively. (3) the rx_out port has a maximum data width of 10 bits . 2 deserializer bit slip synchronizer dpa circuitry 2 clock mux 8 serial lvds clock phases left/right pll rx_inclock lvds clock domain dpa clock domain 10 dout din din retimed data dpa clock lvds_diffiioclk dpa_diffioclk 3 (dpa_load_en, dpa_diffioclk, rx_divfwdclk) (lvds_load_en, lvds_diffioclk, rx_outclk) 3 (load_en, diffioclk) diffioclk rx_out rx_divfwdcl k rx_outclock rx_in + fpga fabric lvds receiver i o e s u pp o r t s s dr, ddr, or non-re g istered datapat h io e dout din dout din 8?24 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices differential receiver stratix iv device handbook volume 1 ? march 2010 altera corporation soft-cdr mode the stratix iv lvds channel offers the soft-cdr mode to support the gigabit ethernet and sgmii protocols. a receiver pll uses the local clock source for reference. figure 8?20 shows the soft-cdr mode datapath. in soft-cdr mode, the synchronizer block is inactive. the dpa circuitry selects an optimal dpa clock phase to sample the data. use the selected dpa clock for bit-slip operation and deserialization. the dpa block also forwards the selected dpa clock, divided by the deserialization factor called rx_divfwdclk , to the fpga fabric, along with the deserialized data. this clock signal is put on the periphery clock (pclk) network. when using soft-cdr mode, the rx_reset port must not be asserted after the rx_dpa_lock is asserted because the dpa will continuously choose new phase taps from the pll to track parts per million (ppm) differences between the reference clock and incoming data. f r r fr wr rfr clock networks and plls in stratix iv devices chapter. figure 8?20. receiver datapath in soft-cdr mode (note 1) , (2) , (3) notes to figure 8?20 : (1) all disabled blocks and signals are grayed out. (2) in sdr and ddr modes, the data width from the ioe is 1 and 2 bits, respectively. (3) the rx_out port has a maximum data width of 10 bits . 2 deserializer bit slip synchronizer dpa circuitry 2 clock mux 8 serial lvds clock phases left/right pll rx_inclock lvds clock domain dpa clock domain 10 dout din dout din dout din din retimed data dpa clock lvds_diffiioclk dpa_diffioclk 3 (dpa_load_en, dpa_diffioclk, rx_divfwdclk) (lvds_load_en, lvds_diffioclk, rx_outclk) 3 (load_en, diffioclk) diffioclk rx_out rx_divfwdclk rx_outclock rx_in + fpga fabric lvds receiver i o e s u pp o r t s s dr, ddr, or non-re g istered datapat h io e chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?25 lvds interface with the use external pll option enabled ? march 2010 altera corporation stratix iv device handbook volume 1 you can use every lvds channel in soft-cdr mode and can drive the fpga fabric using the pclk network in the stratix iv device family. the rx_dpa_locked signal is not valid in soft-cdr mode because the dpa continuously changes its phase to track ppm differences between the upstream transmitter and the local receiver input reference clocks. the parallel clock rx_outclock , generated by the left and right pll, is also forwarded to the fpga fabric. lvds interface with the use external pll option enabled the altlvds megawizard plug-in manager software provides an option for implementing the lvds interface with the use external pll option. with this option enabled you can control the pll settings, such as dynamically reconfiguring the pll to support different data rates, dynamic phase shift, and other settings. you also must instantiate an altpll megafunction to generate the various clock and load enable signals. when you enable the use external pll option with the altlvds transmitter and receiver, the following signals are required from the altpll megafunction: rx_syncclock port and receiver fpga fabric logic 1 1 cr r cc r cc r r c c1 c rcv w c f c c c f cc r r rfc cc f f ffr cc rr r r fr rfr altlvds megafunction user guide . 8?26 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices lvds interface with the use external pll option enabled stratix iv device handbook volume 1 ? march 2010 altera corporation table 8?10 lists the signal interface between the output ports of the altpll megafunction and input ports of the altlvds transmitter and receiver. 1 rx_syncclock port is automatically enabled in an lvds receiver in external pll mode. the quartus ii compiler errors out if this port is not connected as shown in figure 8?21 . when generating the altpll megafunction, the left/right pll option is configured to set up the pll in lvds mode. figure 8?21 shows the connection between the altpll and altlvds megafunctions. table 8?10. signal interface between altpll and altlvds megafunctions from the altpll megafunction to the altlvds transmitter to the altlvds receiver serial clock output (c0) tx_inclock (serial clock input to the transmitter) rx_inclock (serial clock input) load enable output (c1) tx_enable (load enable to the transmitter) rx_enable (load enable for the deserializer) parallel clock output (c2) parallel clock used inside the transmitter core logic in the fpga fabric rx_syncclock (parallel clock input) and parallel clock used inside the receiver core logic in the fpga fabric ~(locked) ? pll_areset (asynchronous pll reset port) (1) note to tab l e 8 ?1 0 : (1) the pll_areset signal is automatically enabled for the lvds receiver in external pll mode. this signal does not exist for lvds transmitter instantiation when the external pll option is enabled. figure 8?21. lvds interface with the altpll megafunction (note 1) note to figure 8?21 : (1) instantiation of pll_areset is optional for the altpll instantiation. transmitter core logic tx_coreclk rx_coreclk receiver core logic tx_in tx_inclock tx_enable altpll lvds receiver (altlvds) lvds transmitter (altlvds) fpga fabric c0 inclk0 c1 c2 rx_out rx_inclock rx_enable rx_syncclock pll_areset locked pll_areset chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?27 lvds interface with the use external pll option enabled ? march 2010 altera corporation stratix iv device handbook volume 1 example 8?1 shows how to generate three output clocks using an altpll megafunction. example 8?1. generating three output clocks using an altpll megafunction lvds data rate = 1 gbps; serialization factor = 10; input reference clock = 100 mhz the following settings are used when generating the three output clocks using an altpll megafunction. the serial clock must be 1000 mhz and the parallel clock must be 100 mhz (serial clock divided by the serialization factor): 1000 mhz (multiplication factor = 10 and division factor = 1) ?180 with respect to the voltage-controlled oscillator (vco) clock 50% 100 mhz (multiplication factor = 1 and division factor = 1) 288 [(deserialization factor - 2)/deserialization factor] 360 10% (100 divided by the serialization factor) 100 mhz (multiplication factor = 1 and division factor = 1) ?18 (c0 phase shift divided by the serialization factor) 50% 8?28 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices left and right plls (pll_lx and pll_rx) stratix iv device handbook volume 1 ? march 2010 altera corporation the equation 8?1 calculations for phase shift assume that the input clock and serial data are edge aligned. introducing a phase shift of ?180 to sampling clock (c0) ensures that the input data is center-aligned with respect to the c0, as shown in figure 8?22 . left and right plls (pll_lx and pll_rx) the stratix iv device family contains up to eight left and right plls with up to four plls located on the left side and four on the right side of the device. the left plls can support high-speed differential i/o banks on the left side; the right plls can support high-speed differential i/o banks on the right side of the device. the high-speed differential i/o receiver and transmitter channels use these left and right plls to generate the parallel clocks ( rx_outclock and tx_outclock ) and high-speed clocks ( diffioclk). figure 8?2 on page 8?3 and figure 8?3 on page 8?4 show the locations of the left and right plls for stratix iv e, gt, and gx devices, respectively. the pll vco operates at the clock frequency of the data rate. clock switchover and dynamic reconfiguration are allowed using the left and right pll in high-speed differential i/o support mode. f r r fr rfr clock network and plls in stratix iv devices chapter. figure 8?22. phase relationship for external pll interface signals d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 inclk0 vco clk (internal pll clk) c0 (-180 phase shift) c1 (288 phase shift) c2 (-18 phase shift) serial data chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?29 stratix iv clocking ? march 2010 altera corporation stratix iv device handbook volume 1 stratix iv clocking the left and right plls feed into the differential transmitter and receive channels through the lvds and dpa clock network. the center left and right plls can clock the transmitter and receive channels above and below them. the corner left and right plls can drive i/os in the banks adjacent to them. figure 8?23 shows center pll clocking in the stratix iv device family. for more information about pll clocking restrictions, refer to ?differential pin placement guidelines? on page 8?37 . figure 8?24 shows center and corner pll clocking in the stratix iv device family. for more information about pll clocking restrictions, refer to ?differential pin placement guidelines? on page 8?37 . figure 8?23. lvds/dpa clocks in the stratix iv device family with center plls 4 2 2 2 2 4 4 4 4 4 4 4 quadrant quadrant quadrant quadrant lv d s clock center pll_l2 center pll_l3 dpa clock lv d s clock dpa clock lv d s clock center pll_r2 center pll_r3 dpa clock lv d s clock dpa clock figure 8?24. lvds/dpa clocks in the stratix iv device family with center and corner plls 4 2 2 2 2 4 quadrant quadrant quadrant quadrant lv d s clock center pll_l2 center pll_l3 lv d s clock dpa clock 2 4 2 4 4 4 2 4 2 4 lv d s clock center pll_r2 center pll_r3 dpa clock lv d s clock dpa clock corner pll_l1 corner pll_l4 dpa clock corner pll_r1 corner pll_r4 8?30 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices source-synchronous timing budget stratix iv device handbook volume 1 ? march 2010 altera corporation source-synchronous timing budget this section describes the timing budget, waveforms, and specifications for source-synchronous signaling in the stratix iv device family. lvds i/o standards enable high-speed data transmission. this high data transmission rate results in better overall system performance. to take advantage of fast system performance, it is important to understand how to analyze timing for these high-speed signals. timing analysis for the differential block is different from traditional synchronous timing analysis techniques. instead of focusing on clock-to-output and setup times, source synchronous timing analysis is based on the skew between the data and the clock signals. high-speed differential data transmission requires the use of timing parameters provided by ic vendors and is strongly influenced by board skew, cable skew, and clock jitter. this section defines the source-synchronous differential data orientation timing parameters, the timing budget definitions for the stratix iv device family, and how to use these timing parameters to determine a design?s maximum performance. differential data orientation there is a set relationship between an external clock and the incoming data. for operations at 1 gbps and a serialization factor of 10, the external clock is multiplied by 10. you can set phase-alignment in the pll to coincide with the sampling window of each data bit. the data is sampled on the falling edge of the multiplied clock. figure 8?25 shows the data bit orientation of the 10 mode. differential i/o bit position data synchronization is necessary for successful data transmission at high frequencies. figure 8?26 shows the data bit orientation for a channel operation. this figure is based on the following: figure 8?25. bit orientation in the quartus ii software 9 8 7 6 5 4 3 2 1 0 10 lvds bits msb lsb inclock/o u tclock data in chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?31 source-synchronous timing budget ? march 2010 altera corporation stratix iv device handbook volume 1 table 8?11 lists the conventions for differential bit naming for 18 differential channels. the msb and lsb positions increase with the number of channels used in a system. figure 8?26. bit-order and word boundary for one differential channel (note 1) note to figure 8?26 : (1) these are only functional waveforms and are not intended to convey timing information. previous cycle 76543210 msb lsb tx_outclock tx_out xxxxxxxx xxx xxxxx current cycle next cycle transmitter channel operation (x8 mode) x xxxxxxxx rx_inclock rx_in 76543210 xxx xxxxxxx xxxx x receiver channel operation (x8 mode) rx_outclock rx_out [7..0] x x x x x x x x x x x x x x x x x x x x 7 6 5 4 3 2 1 0 x x x x table 8?11. differential bit naming receiver channel data number internal 8-bit parallel data msb position lsb position 170 21 58 32 31 6 43 12 4 53 93 2 64 74 0 75 54 8 86 35 6 97 16 4 10 79 72 11 87 80 12 95 88 13 103 96 14 111 104 15 119 112 16 127 120 17 135 128 18 143 136 8?32 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices source-synchronous timing budget stratix iv device handbook volume 1 ? march 2010 altera corporation transmitter channel-to-channel skew transmitter channel-to-channel skew (tccs) is an important parameter based on the stratix iv transmitter in a source synchronous differential interface. this parameter is used in receiver skew margin calculation. for more information, refer to ?receiver skew margin for non-dpa mode? on page 8?32 . tccs is the difference between the fastest and slowest data output transitions, including the tco variation and clock skew. for lvds transmitters, the timequest timing analyzer provides a tccs report, which shows tccs values for serial output ports. f c v fr rr report_tccs ) in the quartus ii compilation report under the timequest timing analyzer, or from the dc and switching characteristics chapter. receiver skew margin for non-dpa mode changes in system environment, such as temperature, media (cable, connector, or pcb), and loading effect the receiver ?s setup and hold times; internal skew affects the sampling ability of the receiver. different modes of lvds receivers use different specifications that can help in deciding the ability to sample the received serial data correctly. in dpa mode, you must use dpa jitter tolerance instead of receiver input skew margin (rskm). in non-dpa mode, use tccs, rskm, and sampling window (sw) specifications for high-speed source-synchronous differential signals in the receiver data path. the relationship between rskm, tccs, and sw is expressed by the rskm equation shown in equation 8?1 . conventions used for the equation: equation 8?1. rskm rskm tui sw ? tccs ? 2 ----------------------------------------- = chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?33 source-synchronous timing budget ? march 2010 altera corporation stratix iv device handbook volume 1 figure 8?27 shows the relationship between the rskm, tccs, and the receiver?s sw. you must calculate the rskm value to decide whether or not data can be sampled properly by the lvds receiver with the given data rate and device. a positive rskm value indicates that the lvds receiver can sample the data properly, whereas a negative rskm indicates that it cannot. figure 8?27. differential high-speed timing diagram and timing budget for non-dpa mode tui time unit inter v al (tui) tccs internal clock falling edge tccs tccs 2 receiv er input data transmitter output data internal clock synchronization external clock receiv er input data internal clock external inpu t clock timing budge t timing diag ram clock placement sw tccs rskm rskm sw rskm rskm 8?34 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices source-synchronous timing budget stratix iv device handbook volume 1 ? march 2010 altera corporation for lvds receivers, the quartus ii software provides an rskm report showing the sw, tui, and rskm values for non-dpa mode. you can generate the rskm report by executing the report_rskm command in the timequest timing analyzer. you can find the rskm report in the quartus ii compilation report under the timequest timing analyzer section. 1 rr v rr rcvr r r cr r fw 1 r r fr cr r w vr c r r c set input delay option. figure 8?28. selection of constraint menu in timequest timing analyzer chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?35 source-synchronous timing budget ? march 2010 altera corporation stratix iv device handbook volume 1 2. figure 8?29 shows the setting parameters for the set input delay option. the clock name must reference the source synchronous clock that feeds the lvds receiver. select the desired clock using the pull-down menu. 3. figure 8?30 shows the targets option. you can view a list of all available ports using the list option in the name finder window. figure 8?29. input time delay assignment through timequest timing analyzer figure 8?30. name finder window in set input delay option 8?36 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices source-synchronous timing budget stratix iv device handbook volume 1 ? march 2010 altera corporation 4. select the lvds receiver serial input ports (from the list) according to the input delay you set. click ok . 5. in the set input delay window, set the appropriate values in the input delay options section and delay value. 6. click run to incorporate these values in the timequest timing analyzer. 7. assign the appropriate delay for all the lvds receiver input ports following these steps. if you have already assigned input delay and you need to add more delay to that input port, use the add delay option in the set input delay window. 1 f r rcvr cc w f r c rc cr f .sdc) using the set_input_delay command. f r r fr .sdc commands and the timequest timing analyzer, refer to the quartus ii timequest timing analyzer chapter in volume 3 of the quartus ii development software handbook . example 8?2 shows the rskm calculation. 1 c cc cr fr ffr example 8?2. rskm data rate: 1 gbps, board channel-to-channel skew = 200 ps for stratix iv devices: tccs = 100 ps (pending characterization) sw = 300 ps (pending characterization) tui = 1000 ps total rccs = tccs + board channel-to-channel skew= 100 ps + 200 ps = 300 ps rskm = tui - sw - rccs = 1000 ps - 300 ps - 300 ps = 400 ps > 0 because the rskm > 0 ps, receiver non-dpa mode must work correctly. chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?37 differential pin placement guidelines ? march 2010 altera corporation stratix iv device handbook volume 1 differential pin placement guidelines to ensure proper high-speed operation, differential pin placement guidelines have been established. the quartus ii compiler automatically checks that these guidelines are followed and issues an error message if they are not met. this section is divided into pin placement guidelines with and without dpa usage because dpa usage adds some constraints on the placement of high-speed differential channels. 1 ffr c rfr r f c rfr guidelines for dpa-enabled differential channels the stratix iv device family has differential receivers and transmitters in i/o banks on the left and right sides of the device. each receiver has a dedicated dpa circuit to align the phase of the clock to the data phase of its associated channel. when you use dpa-enabled channels in differential banks, you must adhere to the guidelines listed in the following sections. dpa-enabled channels and single-ended i/os when you enable a dpa channel in a bank, both single-ended i/os and differential i/o standards are allowed in the bank. dpa-enabled channel driving distance if the number of dpa channels driven by each left and right pll exceeds 25 lab rows, altera recommends implementing data realignment (bit slip) circuitry for all the dpa channels. 8?38 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices differential pin placement guidelines stratix iv device handbook volume 1 ? march 2010 altera corporation using corner and center left and right plls if a differential bank is being driven by two left and right plls, where the corner left and right pll is driving one group and the center left and right pll is driving another group, there must be at least one row of separation between the two groups of dpa-enabled channels (refer to figure 8?31 ). the two groups can operate at independent frequencies. you do not need a separation if a single left and right pll is driving the dpa-enabled channels as well as dpa-disabled channels. figure 8?31. corner and center left and right plls driving dpa-enabled differential i/os in the same bank center left/right pll corner left / right pll diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa -enabled diff i/o dpa- enabled diff i/o channels driven by corner left/right pll channels driven by center left/right pll one unused channel for buffer dpa -enabled diff i/o dpa - enabled diff i/o dpa - enabled diff i/o dpa - enabled diff i/o dpa - enabled diff i/o reference reference clk clk chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?39 differential pin placement guidelines ? march 2010 altera corporation stratix iv device handbook volume 1 using both center left and right plls you can use both center left and right plls to drive dpa-enabled channels simultaneously, as long as they drive these channels in their adjacent banks only, as shown in figure 8?32 . if one of the center left and right plls drives the top and bottom banks, you cannot use the other center left and right pll to drive differential channels, as shown in figure 8?32 . if the top pll_l2 and pll_r2 drives dpa-enabled channels in the lower differential bank, the pll_l3 and pll_r3 cannot drive dpa-enabled channels in the upper differential banks and vice versa. in other words, the center left and right plls cannot drive cross-banks simultaneously, as shown in figure 8?33 . figure 8?32. center left and right plls driving dpa-enabled differential i/os reference clk dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o center left/right pll (pll_l2/pll_r2) center left/right pll (pll_l2/pll_r2) center left/right pll (pll_l3/pll_r3) center left/right pll (pll_l3/pll_r3) unused pll reference clk reference clk reference clk dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o 8?40 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices differential pin placement guidelines stratix iv device handbook volume 1 ? march 2010 altera corporation guidelines for dpa-disabled differential channels when you use dpa-disabled channels in the left and right banks of a stratix iv device, you must adhere to the guidelines in the following sections. dpa-disabled channels and single-ended i/os the placement rules for dpa-disabled channels and single-ended i/os are the same as those for dpa-enabled channels and single-ended i/os. for more information, refer to ?dpa-enabled channels and single-ended i/os? on page 8?37 . figure 8?33. invalid placement of dpa-enabled differential i/os driven by both center left and right plls dpa-enabled diff i/o center left /right pll dpa-enabled diff i/o dpa-enabled diff i/o reference clk reference clk dpa-enabled diff i/o dpa-enabled diff i/o dpa-enabled diff i/o center left /right pll dpa-enabled diff i/o dpa-enabled diff i/o chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?41 differential pin placement guidelines ? march 2010 altera corporation stratix iv device handbook volume 1 dpa-disabled channel driving distance each left and right pll can drive all the dpa-disabled channels in the entire bank. using corner and center left and right plls you can use a corner left and right pll to drive all transmitter channels and a center left and right pll to drive all dpa-disabled receiver channels within the same differential bank. in other words, a transmitter channel and a receiver channel in the same lab row can be driven by two different plls, as shown in figure 8?34 . a corner left and right pll and a center left and right pll can drive duplex channels in the same differential bank, as long as the channels driven by each pll are not interleaved. separation is not necessary between the group of channels driven by the corner and center left and right plls, as shown in figure 8?34 and figure 8?35 . figure 8?34. corner and center left and right plls driving dpa-disabled differential i/os in the same bank diff rx corner left/right pll diff tx diff rx diff rx diff tx diff tx diff tx diff tx diff tx diff tx diff rx diff rx diff tx diff rx diff rx diff tx diff rx diff rx diff rx diff tx corner left / right pll dpa -disabled diff i /o channels driven by corner left/right pll channels driven by center left/right pll no separation buffer needed reference clk reference clk reference clk reference clk dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o center left/right pll center left/right pll 8?42 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices differential pin placement guidelines stratix iv device handbook volume 1 ? march 2010 altera corporation figure 8?35. invalid placement of dpa-disabled differential i/os due to interleaving of channels driven by the corner and center left and right plls dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o corner left/right pll reference clk dpa-disabled diff i/o dpa-disabled diff i/o reference clk center left/right pll chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices 8?43 differential pin placement guidelines ? march 2010 altera corporation stratix iv device handbook volume 1 using both center left and right plls you can use both center left and right plls simultaneously to drive dpa-disabled channels on upper and lower differential banks. unlike dpa-enabled channels, the center left and right plls can drive cross-banks. for example, the upper-center left and right pll can drive the lower differential bank at the same time the lower center left and right pll is driving the upper differential bank, and vice versa, as shown in figure 8?36 . figure 8?36. both center left and right plls driving cross-bank dpa-disabled channels simultaneously dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o dpa-disabled diff i/o reference clk reference clk center left/right pll center left/right pll 8?44 chapter 8: high-speed differential i/o interfaces and dpa in stratix iv devices chapter revision history stratix iv device handbook volume 1 ? march 2010 altera corporation chapter revision history table 8?12 lists the revision history for this chapter. table 8?12. chapter revision history date and document version changes made changes made march 2010 v3.1 removed note 7 from tab le 8 ?1 and table 8?2 . updated figure 8?5 . updated the ?lvds channels? section. updated table 8?7 . added a note to the ?lvds interface with the use external pll option enabled? and ?a ltlv ds po rt l ist ? sections. minor text edits. ? november 2009 v3.0 changed ?dedicated lvds? to ?true lvds?. removed ep4se110, ep4se290, and ep4se680 devices. added ep4se820 and stratix iv gt devices. updated ?lvds channels?, ?differential transmitter?, ?soft-cdr mode?, and ?dpa-enabled channels and single-ended i/os? sections. updated table 8?1, table 8?2, table 8?5, and table 8?6. added table 8?3 and table 8?4. updated example 8?1. updated figure 8?22. minor text edits. ? june 2009 v2.3 added an introductory paragraph to increase search ability. minor text edits. ? april 2009 v2.2 updated ?introduction?. updated figure 8?3. removed table 8-5 and table 8-6. ? march 2009 v2.1 updated ?introduction?, ?stratix iv lvds channels?, ?stratix iv differential transmitter?, ?differential i/o termination?, and ?dynamic phase alignment (dpa) block? sections. updated table 8?1, table 8?2, table 8?3, table 8?4, and table 8?7. added table 8?5 and table 8?6. updated figure 8?2. removed ?referenced documents? section. ? november 2008 v2.0 updated figure 8?2, figure 8?3, figure 8?21, figure 8?34. removed figure 8?31. updated table 8?1, table 8?10. updated ?differential pin placement guidelines? section. ? may 2008 v1.0 initial release. ? ? march 2010 altera corporation stratix iv device handbook volume 1 section iii. system integration this section includes the following chapters: revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook. iii?2 section iii: system integration revision history stratix iv device handbook volume 1 ? march 2010 altera corporation ? march 2010 altera corporation stratix iv device handbook volume 1 9. hot socketing and power-on reset in stratix iv devices this chapter describes information about hot-socketing specifications, power-on reset (por) requirements, and their implementation in stratix ? iv devices. stratix iv devices offer hot socketing, also known as hot plug-in or hot swap, and power sequencing support without the use of external devices. you can insert or remove a stratix iv device or a board in a system during system operation without causing undesirable effects to the running system bus or board that is inserted into the system. the hot-socketing feature also removes some of the difficulty when you use stratix iv devices on pcbs that contain a mixture of 3.0-, 2.5-, 1.8-, 1.5-, and 1.2-v devices. the stratix iv hot-socketing feature provides: stratix iv hot-socketing specifications stratix iv devices are hot-socketing compliant without the need for external components or special design requirements. hot-socketing support in stratix iv devices has the following advantages: siv51009-3.1 9?2 chapter 9: hot socketing and power-on reset in stratix iv devices hot-socketing feature implementation in stratix iv devices stratix iv device handbook volume 1 ? march 2010 altera corporation stratix iv devices can be driven before power up you can drive signals into i/o pins, dedicated input pins, and dedicated clock pins of stratix iv devices before or during power up or power down without damaging the device. i/o pins remain tri-stated during power up a device that does not support hot socketing can interrupt system operation or cause contention by driving out before or during power up. in a hot-socketing situation, the stratix iv device?s output buffers are turned off during system power up or power down. also, the stratix iv device does not drive out until the device is configured and working within the recommended operating conditions. insertion or removal of a stratix iv device from a powered-up system devices that do not support hot socketing can short power supplies when powered up through the device signal pins. this irregular power up can damage both the driving and driven devices and can disrupt card power up. you can insert a stratix iv device into or remove it from a powered-up system board without damaging the system board or interfering with its operation. you can power up or power down the v ccio , v cc , v ccpgm , and v ccp d supplies in any sequence which are monitored by the hotsocket circuit. in addition, all other power supplies for the device can be powered up or down in any sequence. individual power supply ramp-up and ramp-down rates range from 50 s to 100 ms. during hot socketing, the i/o pin capacitance is less than 15 pf and the clock pin capacitance is less than 20 pf. 1 ccf wr rc vc f wr fr r ccr rr c fr c r vc r c w c c c ccr w crc r c cv r c c cc rv cv fr wr c rv crr vc wr r c c c c wc fr wr r w vc r vc rw r f crr c crc hot-socketing feature implementation in stratix iv devices the hot-socketing feature turns off the output buffer during power up and power down of the v cc , v ccaux , v ccio , v ccpgm , or v ccpd power supplies. the hot-socketing circuitry generates an internal hotsckt signal when the v cc , v ccaux , v ccio , v ccpgm , or v ccpd power supplies are below the threshold voltage. hot-socketing circuitry is designed to prevent excess i/o leakage during power up. when the voltage ramps up very slowly, it is still relatively low, even after the por signal is released and the configuration is completed. the conf_done, nceo , and nstatus pins fail to chapter 9: hot socketing and power-on reset in stratix iv devices 9?3 hot-socketing feature implementation in stratix iv devices ? march 2010 altera corporation stratix iv device handbook volume 1 respond, as the output buffer cannot flip from the state set by the hot-socketing circuit at this low voltage. therefore, the hot-socketing circuitry has been removed from these configuration pins to make sure that they are able to operate during configuration. thus, it is expected behavior for these pins to drive out during power-up and power-down sequences. figure 9?1 shows the stratix iv device?s i/o pin circuitry. the por circuit monitors the voltage level of the power supplies (v cc , v ccaux , v ccpt , v ccpgm , and v ccpd ) and keeps the i/o pins tri-stated until the device is in user mode. the weak pull-up resistor (r) in the stratix iv input/output element (ioe) keeps the i/o pins from floating. the 3.0-v tolerance control circuit permits the i/o pins to be driven by 3.0 v before the v cc , v ccaux , v ccpt , v ccpgm , or v ccpd supplies are powered. it also prevents the i/o pins from driving out when the device is not in user mode. to successfully power-up and exit por on production devices, fully power v cc before v ccaux begins to ramp. 1 r rfrc fr c r ffr r rr r cc w r fr cc wr rv r r fr vr wr r r c r r c rw c fcfc v r crr c w r vc figure 9?1. hot-socketing circuitry for stratix iv devices v ccio pa d r voltage tolerance control output enable hot socket output pre-driver power on reset monitor weak pull-up resistor input buffer to logic array 9?4 chapter 9: hot socketing and power-on reset in stratix iv devices power-on reset circuitry stratix iv device handbook volume 1 ? march 2010 altera corporation power-on reset circuitry when power is applied to a stratix iv device, a por event occurs if the power supply reaches the recommended operating range within the maximum power supply ramp time (t ramp ). if t ramp is not met, the device i/o pins and programming registers remain tri-stated, during which device configuration could fail. the maximum t ramp for stratix iv devices is 100 ms; the minimum t ramp is 50 s. when the porsel pin is high, the maximum t ramp for stratix iv devices is 4 ms. stratix iv devices provide a dedicated input pin ( porsel ) to select a por delay time during power up. when the porsel pin is connected to gnd, the por delay time is 100 to 300 ms. when the porsel pin is set to high, the por delay time is 4 to 12 ms. the por block consists of a regulator por, satellite por, and main por to check the power supply levels for proper device configuration. the satellite por monitors the following: 1 r rc wr fr w fr rr r r f vc cfr c r r cfr r r vc cfr cc rr c c fr f r r w f r f c 1 cfrr c fc wr figure 9?2. simplified por diagram for stratix iv devices regulator por satellite por por pulse setting porsel por main por v ccpgm v ccpd v cc v ccpt v ccaux chapter 9: hot socketing and power-on reset in stratix iv devices 9?5 power-on reset specifications ? march 2010 altera corporation stratix iv device handbook volume 1 power-on reset specifications the por circuit monitors the power supplies listed in table 9?1 . 1 r rc wr fr crc r wr 1 r r v ffc vc cfr cfc r crc r vc r cr w r wr w rr porsel input pin. when the porsel pin is connected to gnd, the por delay time is 100 to 300 ms. when the porsel pin is set to high, the por delay time is 4 to 12 ms. f r r fr cfc rfr dc and switching characteristics chapter. tab le 9 ?1 . power supplies monitored by the por circuitry power supply description setting (v) v cc core and periphery power supply 0.9 v ccpt programmable power technology power supply 1.5 v ccpd i/o pre-driver power supply 2.5, 3.0 v ccpgm configuration pins power supply 1.8, 2.5, 3.0 v ccaux auxiliary supply for the programmable power technology 2.5 tab le 9 ?2 . power supplies not monitored by the por circuitry (note 1) power supply description setting (v) v ccio i/o power supply 1.2, 1.5, 1.8, 2.5, 3.0 v cca_pll pll analog global power supply 2.5 v ccd_pll pll digital power supply 0.9 v c c_c lki n pll differential clock input power supply (top and bottom i/o banks only) 2.5 v ccbat battery back-up power supply for design security volatile key storage 3.0 note to tab l e 9 ?2 : (1) the transceiver supplies are not monitored by por. 9?6 chapter 9: hot socketing and power-on reset in stratix iv devices document revision history stratix iv device handbook volume 1 ? march 2010 altera corporation document revision history table 9?3 shows the revision history for this chapter. tab le 9 ?3 . document revision history date and document version changes made summary of changes march 2010 v3.1 updated the introduction and the ?stratix iv hot-socketing specifications? , ?insertion or removal of a stratix iv device from a powered-up system? , ?hot-socketing feature implementation in stratix iv devices? , ?power-on reset circuitry? , and ?power-on reset specifications? sections. updated table 9?1 and tab le 9 ?2 . updated figure 9?2 . minor text edits. ? november 2009 v3.0 updated graphics. minor text edits. ? june 2009 v2.2 updated table 9?2. added introductory sentences to improve search ability. removed the conclusion section. minor text edits. ? march 2009 v2.1 changed all ?stratix iv e? to ?stratix iv?. updated ?stratix iv hot-socketing specifications? and ?hot-socketing feature implementation in stratix iv devices? sections. updated figure 9?2. removed ?referenced documents? section. ? november 2008 v2.0 updated ?hot-socketing feature implementation in stratix iv devices? on page 9?2. updated ?power-on reset circuitry? on page 9?4. updated table 9?1. made minor editorial changes. ? july 2008 v1.1 revised ?introduction?. ? may 2008 v1.0 initial release. ? ? march 2010 altera corporation stratix iv device handbook volume 1 10. configuration, design security, and remote system upgrades in stratix iv devices this chapter describes the configuration, design security, and remote system upgrades in stratix ? iv devices. stratix iv devices provide configuration data decompression to save configuration memory space and time. they also provide a built-in design security feature that protects your designs against ip theft and tampering of your configuration files. stratix iv devices also offer remote system upgrade capability so that you can upgrade your system in real-time through any network. this helps to deliver feature enhancements and bug fixes and provides error detection, recovery, and status information to ensure reliable reconfiguration. overview this chapter contains information about stratix iv?supported configuration schemes, instructions about how to execute the required configuration schemes, and the necessary pin settings. stratix iv devices use sram cells to store configuration data. as sram is volatile, you must download configuration data to the stratix iv device each time the device powers up. you can configure stratix iv devices using one of four configuration schemes: siv51010-3.1 10?2 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices configu r ation s c heme s stratix iv device handbook volume 1 ? march 2010 altera corporation ?dedicated remote system upgrade circuitry? on page 10?55 ?quartus ii software support? on page 10?61 ?design security? on page 10?62 configuration devices altera ? serial configuration devices support a single-device and multi-device configuration solution for stratix iv devices and are used in the fast as configuration scheme. serial configuration devices offer a low-cost, low pin-count configuration solution. f for information about serial configuration devices, refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet in volume 2 of the configuration handbook . 1 all minimum timing information in this chapter covers the entire stratix iv family. some devices may work at less than the minimum timing stated in this handbook due to process variation. configuration schemes select the configuration scheme by driving the stratix iv device msel pins either high or low, as shown in table 10?1 . the msel input buffers are powered by the v cc power supply. altera recommends you hardwire the msel[] pins to v ccpgm and gnd. the msel[2..0] pins have 5-k internal pull-down resistors that are always active. during power-on reset (por) and during reconfiguration, the msel pins must be at v il and v ih levels of v ccp gm voltage to be considered logic low and logic high. 1 to avoid problems with detecting an incorrect configuration scheme, hardwire the msel[] pins to v ccp gm and gnd without pull-up or pull-down resistors. do not drive the msel[] pins by a microprocessor or another device. table 10?1. stratix iv configuration schemes configuration scheme msel2 msel1 msel0 fast passive parallel 0 0 0 passive serial 0 1 0 fast as (40 mhz) (1) 011 remote system upgrade fast as (40 mhz) (1) 011 fpp with design security feature and/or decompression enabled (2) 001 jtag-based configuration (4) (3) (3) (3) notes to ta bl e 10 ?1 : (1) stratix iv devices only support fast as configuration. you must use either e pcs64 or epcs128 devices to configure a stratix iv device in fast as mode. (2) these modes are only supported when using a max ii device or a microprocessor with flash memory for configuration. in these modes, the host system must output a dclk that is 4 the data rate. (3) do not leave the msel pins floating, connect them to v ccpgm or gnd. these pins support the non-jtag configuration scheme used in production. if you only use the jtag configuration, connect the msel pins to gnd. (4) the jtag-based configuration takes precedence over other configuration schemes, which means the msel pin settings are ignored. the jtag-based configuration does not support the design security or decompression features. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?3 configu r ation s c heme s ? march 2010 altera corporation stratix iv device handbook volume 1 table 10?2 lists the uncompressed raw binary file ( .rbf ) configuration file sizes for stratix iv devices. use the data in table 10?2 to estimate the file size before design compilation. different configuration file formats; for example, a hexidecimal ( .hex ) or tabular text file ( .ttf ) format, have different file sizes. refer to the quartus ? ii software for the different types of configuration file and file sizes. however, for any specific version of the quartus ii software, any design targeted for the same device has the same uncompressed configuration file size. if you are using compression, the file size can vary after each compilation because the compression ratio is dependent on the design. f for more information about setting device configuration options or creating configuration files, refer to the device configuration options and configuration file formats chapters in volume 2 of the configuration handbook . table 10?2. stratix iv uncompressed raw binary file ( .rbf ) sizes device data size (bits) ep4se230 94,557,465 ep4se360 128,395,577 ep4se530 171,722,057 ep4se820 241,700,000 (1) ep4sgx70 47,833,345 ep4sgx110 47,833,345 ep4sgx180 94,557,465 ep4sgx230 94,557,465 ep4sgx290 128,395,577 171,722,057 (2) ep4sgx360 128,395,577 171,722,057 (2) ep4sgx530 171,722,057 ep4s40g2 94,557,465 ep4s40g5 171,722,057 ep4s100g2 94,557,465 ep4s100g3 171,722,057 ep4s100g4 171,722,057 ep4s100g5 171,722,057 note to tab l e 1 0? 2 : (1) this value is preliminary. (2) this only applies to the f45 package. 10?4 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices configu r ation featu r e s stratix iv device handbook volume 1 ? march 2010 altera corporation configuration features stratix iv devices offer design security, decompression, and remote system upgrade features. design security using configuration bitstream encryption is available in stratix iv devices, which protects your designs. stratix iv devices can receive a compressed configuration bitstream and decompress this data in real-time, reducing storage requirements and configuration time. you can make real-time system upgrades from remote locations of your stratix iv designs with the remote system upgrade feature. table 10?3 summarizes which configuration features you can use in each configuration scheme. you can also refer to the following: for more information about the configuration data decompression feature, refer to ?configuration data decompression? on page 10?47 . for more information about the remote system upgrade feature, refer to ?remote system upgrades? on page 10?49 . for more information about the design security feature, refer to ?design security? on page 10?62 . if your system already contains a common flash interface (cfi) flash memory, you can use it for stratix iv device configuration storage as well. the max ii parallel flash loader (pfl) feature in max ii devices provides an efficient method to program cfi flash memory devices through the jtag interface and provides the logic to control configuration from the flash memory device to the stratix iv device. both ps and fpp configuration modes are supported using this pfl feature. f for more information about pfl, refer to an 386: using the parallel flash loader with the quartus ii software . for more information about programming altera serial configuration devices, refer to ?programming serial configuration devices? on page 10?22 . table 10?3. stratix iv configuration features configuration scheme configuration method decompression design security remote system upgrade fpp max ii device or a microprocessor with flash memory v (1) v (1) ? fast as serial configuration device vvv ps max ii device or a microprocessor with flash memory vv ? download cable vv ? jtag max ii device or a microprocessor with flash memory ? ? ? download cable ? ? ? note to tab l e 1 0? 3 : (1) in these modes, the host system must send a dclk that is 4 the data rate. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?5 configu r ation featu r e s ? march 2010 altera corporation stratix iv device handbook volume 1 power-on reset circuit the por circuit keeps the entire system in reset until the power supply voltage levels have stabilized on power-up. after power-up, the device does not release nstatus until v cc , v ccaux , v ccp t , v ccpgm , and v ccpd are above the device?s por trip point. on power down, brown-out occurs if the v cc , v ccaux , v ccpt , v ccpgm , or v ccpd drops below the threshold voltage. in stratix iv devices, a pin-selectable option ( porsel ) is provided that allows you to select between the standard por time or fast por time. when porsel is driven low, the standard por time is 100 ms < t por < 300 ms, which has a lower power-ramp rate. when porsel is driven high, the fast por time is 4 ms < t por < 12 ms. v ccpgm pins stratix iv devices have a power supply, v ccp gm , for all the dedicated configuration pins and dual function pins. the supported configuration voltage is 1.8, 2.5, and 3.0 v. stratix iv devices do not support 1.5 v configuration. use the v ccp gm pin to power all dedicated configuration inputs, dedicated configuration outputs, dedicated configuration bidirectional pins, and some of the dual functional pins that you use for configuration. with v ccpgm , the configuration input buffers do not have to share power lines with the regular i/o buffer in stratix iv devices. the operating voltage for the configuration input pin is independent of the i/o banks power supply v ccio during configuration. therefore, stratix iv devices do not need configuration voltage constraints on v ccio . v ccpd pins stratix iv devices have a dedicated programming power supply, v ccpd , which must be connected to 3.0 v/2.5 v to power the i/o pre-drivers and jtag i/o pins ( tck, tms, tdi, tdo , and trst ). 1 v ccpgm and v ccpd must ramp up from 0 v to the desired voltage level within 100 ms when porsel is low or 4 ms when porsel is high. if these supplies are not ramped up within this specified time, your stratix iv device will not configure successfully. if your system cannot ramp up the power supplies within 100 ms or 4 ms, you must hold nconfig low until all the power supplies are stable. 1 v ccpd must be greater than or equal to v ccio of the same bank. if v ccio of the bank is set to 3.0 v, v ccpd must be powered up to 3.0 v. if the v ccio of the bank is powered to 2.5 v or lower, v ccpd must be powered up to 2.5 v. for more information about configuration pins power supply, refer to ?device configuration pins? on page 10?39 . 10?6 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fa s t pa ss ive pa r allel configu r ation stratix iv device handbook volume 1 ? march 2010 altera corporation fast passive parallel configuration fast passive parallel configuration in stratix iv devices is designed to meet the continuously increasing demand for faster configuration times. stratix iv devices are designed with the capability of receiving byte-wide configuration data per clock cycle. you can perform fpp configuration of stratix iv devices using an intelligent host, such as a max ii device or a microprocessor. fpp configuration using a max ii device as an external host fpp configuration using compression and an external host provides the fastest method to configure stratix iv devices. in this configuration scheme, you can use a max ii device as an intelligent host that controls the transfer of configuration data from a storage device, such as flash memory, to the target stratix iv device. you can store configuration data in .rbf , .hex, or .ttf format. when using the max ii device as an intelligent host, a design that controls the configuration process, such as fetching the data from flash memory and sending it to the device, must be stored in the max ii device. 1 if you are using the stratix iv decompression and/or design security features, the external host must be able to send a dclk frequency that is 4 the data rate. the 4 dclk signal does not require an additional pin and is sent on the dclk pin. the maximum dclk frequency is 125 mhz, which results in a maximum data rate of 250 mbps. if you are not using the stratix iv decompression or design security features, the data rate is 8 the dclk frequency. figure 10?1 shows the configuration interface connections between the stratix iv device and a max ii device for single device configuration. figure 10?1. single device fpp configuration using an external host note to figure 10?1 : (1) connect the resistor to a supply that provides an acceptable input signal for the stratix iv device. v ccpgm must be high enough to meet the v ih specification of the i/o on the device and the external host. altera recommends that you power up all configuration system i/os with v ccpgm. external host (max ii device or microprocessor) conf_done nstatus nce data[7..0] nconfig stratix iv device memory addr data[7..0] gnd msel[2..0] v ccpgm (1) v ccpgm (1) gnd dclk nceo n.c. 10 k 10 k chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?7 fa s t pa ss ive par allel configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 after power-up, the stratix iv device goes through a por. the por delay depends on the porsel pin setting. when porsel is driven low, the standard por time is 100 ms < t por < 300 ms. when porsel is driven high, the fast por time is 4ms chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?9 fa s t pa ss ive par allel configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. the low signal on the nstatus pin also alerts the max ii device that there is an error. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the device and pin options dialog box) is turned on, the device releases nstatus after a reset time-out period (a maximum of 500 s). after nstatus is released and pulled high by a pull-up resistor, the max ii device can try to reconfigure the target device without needing to pulse nconfig low. if this option is turned off, the max ii device must generate a low-to-high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. the max ii device can also monitor the conf_done and init_done pins to ensure successful configuration. the max ii device must monitor the conf_done pin to detect errors and determine when programming completes. if all the configuration data is sent, but the conf_done or init_done signals have not gone high, the max ii device reconfigures the target device. 1 if you use the optional clkusr pin and nconfig is pulled low to restart the configuration during device initialization, ensure that clkusr continues toggling during the time nstatus is low (a maximum of 500 s). when the device is in user mode, initiating reconfiguration is done by transitioning the nconfig pin low-to-high. the nconfig pin must be low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. after nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. figure 10?2 shows how to configure multiple stratix iv devices using a max ii device. this circuit is similar to the fpp configuration circuit for a single device, except the devices are cascaded for multi-device configuration. figure 10?2. multi-device fpp configuration using an external host note to figure 10?2 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for all stratix iv devices in the chain. v ccpgm must be high enough to meet the v ih specification of the i/o standard on the device and the external host. altera recommends you power up all configuration system i/os with v ccpgm. conf_done nstatus nce data[7..0] nconfig stratix iv device 1 stratix iv device 2 memory addr data[7..0] gnd v ccpgm (1) v ccpgm (1) dclk nceo conf_done nstatus nce data[7..0] nconfig dclk nceo n.c. 10 k 10 k external host (max ii device or microprocessor) msel[2..0] gnd msel[2..0] gnd 10?10 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fa s t pa ss ive pa r allel configu r ation stratix iv device handbook volume 1 ? march 2010 altera corporation in a multi-device fpp configuration, the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the first device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. the second device in the chain begins configuration within one clock cycle; therefore, the transfer of data destinations is transparent to the max ii device. all other configuration pins ( nconfig, nstatus, dclk, data[7..0] , and conf_done ) are connected to every device in the chain. the configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. all nstatus and conf_done pins are tied together; if any device detects an error, configuration stops for the entire chain and you must reconfigure the entire chain. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this behavior is similar to a single device detecting an error. if the auto-restart configuration after error option is turned on, the devices release their nstatus pins after a reset time-out period (a maximum of 500 s). after all nstatus pins are released and pulled high, the max ii device tries to reconfigure the chain without pulsing nconfig low. if this option is turned off, the max ii device must generate a low-to-high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. in a multi-device fpp configuration chain, all stratix iv devices in the chain must either enable or disable the decompression and/or design security features. you cannot selectively enable the decompression and/or design security features for each device in the chain because of the data and dclk relationship. if the chain contains devices that do not support design security, use a serial configuration scheme. if a system has multiple devices that contain the same configuration data, tie all device nce inputs to gnd and leave the nceo pins floating. all other configuration pins ( nconfig, nstatus , dclk, data[7..0] , and conf_done ) are connected to every device in the chain. configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices start and complete configuration at the same time. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?11 fa s t pa ss ive par allel configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 figure 10?3 shows a multi-device fpp configuration when both stratix iv devices are receiving the same configuration data. you can use a single configuration chain to configure stratix iv devices with other altera devices that support fpp configuration, such as other types of stratix devices. to ensure that all devices in the chain complete configuration at the same time, or that an error flagged by one device initiates reconfiguration in all devices, tie all of the device conf_done and nstatus pins together. f for more information about configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains in volume 2 of the configuration handbook. figure 10?3. multiple-device fpp configuration using an external host when both devices receive the same data notes to figure 10?3 : (1) connect the resistor to a supply that provides an acceptable input signal for all stratix iv devices in the chain. v ccpgm must be high enough to meet the v ih specification of the i/o on the device and the external host. altera recommends you power up all configuration system i/os wit h v ccpgm. (2) the nceo pins of both stratix iv devices are left unconnected when configuring the same configuration data into multiple devices. conf_done nstatus nce data[7..0] nconfig stratix iv device stratix iv device memory addr data[7..0] v ccpgm (1) v ccpgm (1) dclk nceo n.c. (2) conf_done nstatus nce data[7..0] nconfig gnd dclk nceo n.c. (2 ) 10 k 10 k external host (max ii device or microprocessor) gnd msel[2..0] msel[2..0] gnd gnd 10?12 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fa s t pa ss ive pa r allel configu r ation stratix iv device handbook volume 1 ? march 2010 altera corporation fpp configuration timing figure 10?4 shows the timing waveform for fpp configuration when using a max ii device as an external host. this waveform shows the timing when you have not enabled the decompression and design security features. table 10?4 lists the timing parameters for stratix iv devices for fpp configuration when you have not enabled the decompression and design security features. figure 10?4. fpp configuration timing waveform (note 1) , (2) notes to figure 10?4 : (1) use this timing waveform when you have not enabled the decompression and design security features. (2) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus, and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (3) after power-up, the stratix iv device holds nstatus low for the time of the por delay. (4) after power-up, before and during configuration, conf_done is low. (5) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (6) data[7..0] are available as user i/o pins after configuration except for some exceptions on stratix iv gt. the state of these pins depends o n the dual-purpose pin settings. nconfig nstatus (3) conf_done (4) dclk data[7..0] user i/o init_done byte 0 byte 1 byte 2 byte 3 byte n-2 byte n-1 byte n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mode (6) (5) user mode table 10?4. fpp timing parameters for stratix iv devices (part 1 of 2) (note 1) , (2) symbol parameter minimum maximum units stratix iv (6) stratix iv (7) stratix iv (6) stratix iv (7) t cf2cd nconfig low to conf_done low ? 800 ns t cf2st0 nconfig low to nstatus low ? 800 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 10 500 (3) s t cf2st1 nconfig high to nstatus high ? 500 (3) s t cf2ck nconfig high to first rising edge on dclk 500 ? s t st2ck nstatus high to first rising edge of dclk 2? s t dsu data setup time before rising edge on dclk 4?ns t dh data hold time after rising edge on dclk 1?ns t r input rise time ? 40 ns chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?13 fa s t pa ss ive par allel configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 t input fall time ? 40 ns t cd2um conf_done high to user mode (4) 55 150 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period ?? t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (8532 clkusr period) ?? t ch dclk high time (5) 3.6 4.5 ? ns t cl dclk low time (5) 3.6 4.5 ? ns t clk dclk period (5) 810 ? ns f max dclk frequency ? 125 100 mhz notes to ta bl e 10 ?4 : (1) this information is preliminary. (2) use these timing parameters when you have not enabled the decompression and design security features. (3) you can obtain this value if you do not delay the configuration by extending the nconfig or nstatus low pulse width. (4) the minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for starting the device. (5) adding up t ch and t cl equals to t clk . when ep4se230 t ch is 3.6 ns (min), t cl must be 4.4 ns and vice versa. (6) applicable to ep4se230, ep4se360, ep4sgx70, ep4sgx110, ep 4sgx180, ep4sgx230, ep4sgx290 ( except f45 package), ep4sgx360 (except f45 package), ep4s40g2, ep4s100g2 devices. (7) applicable to ep4se530, ep4se820, ep4sgx290 (only for f45 p ackage), ep4sgx360 (only for f 45 package), ep4s gx530, ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5 devices. table 10?4. fpp timing parameters for stratix iv devices (part 2 of 2) (note 1) , (2) symbol parameter minimum maximum units stratix iv (6) stratix iv (7) stratix iv (6) stratix iv (7) 10?14 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fa s t pa ss ive pa r allel configu r ation stratix iv device handbook volume 1 ? march 2010 altera corporation figure 10?5 shows the timing waveform for fpp configuration when using a max ii device as an external host. this waveform shows the timing when you have enabled the decompression and/or design security features. table 10?5 lists the timing parameters for stratix iv devices for fpp configuration when you enable the decompression and/or the design security features. figure 10?5. fpp configuration timing waveform with decompression or design security feature enabled (note 1) , (2) notes to figure 10?5 : (1) use this timing waveform when you have enabled the decompression and/or design security features. (2) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (3) after power-up, the stratix iv device holds nstatus low for the time of the por delay. (4) after power-up, before and during configuration, conf_done is low. (5) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (6) data[7..0] are available as user i/o pins after configuration except for some exceptions on stratix iv gt. the state of these pins depends on the dual-purpose pin settings. (7) if needed, you can pause dclk by holding it low. when dclk restarts, the external host must provide data on the data[7..0] pins prior to sending the first dclk rising edge. nconfig nstatus (3) conf_done (4) dclk data[7..0] user i/o init_done t cd2um t cf2st1 t cf2cd t cfg t cf2ck t t cf2st0 t st2ck high-z user mode 12341234 1 byte 0 byte 1 byte 2 byte (n-1) byte n 43 t dsu t dh status t dh t ch t cl t clk (7) (5) (6) user mode table 10?5. fpp timing parameters for stratix iv devices with the decompression and/or design security features enabled (note 1) , (2) (part 1 of 2) symbol parameter minimum maximum units stratix iv (6) stratix iv (7) stratix iv (6) stratix iv (7) t cf2cd nconfig low to conf_done low ? 800 ns t cf2st0 nconfig low to nstatus low ? 800 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 10 500 (3) s t cf2st1 nconfig high to nstatus high ? 500 (3) s t cf2ck nconfig high to first rising edge on dclk 500 ? s t st2ck nstatus high to first rising edge of dclk 2? s t dsu data setup time before rising edge on dclk 4?ns t dh data hold time after rising edge on dclk 3/( dclk frequency) + 1 ? ns chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?15 fa s t a c tive se r ial configu r ation (se r ial configu r ation devi c e s ) ? march 2010 altera corporation stratix iv device handbook volume 1 f for more information about device configuration options and how to create configuration files, refer to the device configuration options and configuration file formats chapters in volume 2 of the configuration handbook . fpp configuration using a microprocessor in this configuration scheme, a microprocessor can control the transfer of configuration data from a storage device, such as flash memory, to the target stratix iv device. all information in ?fpp configuration using a max ii device as an external host? on page 10?6 is also applicable when using a microprocessor as an external host. refer to this section for all configuration and timing information. fast active serial configuration (serial configuration devices) in the fast as configuration scheme, stratix iv devices are configured using a serial configuration device. these configuration devices are low-cost devices with non-volatile memory that feature a simple four-pin interface and a small form factor. t data data rate ? 250 mbps t r input rise time ? 40 ns t input fall time ? 40 ns t cd2um conf_done high to user mode (4) 55 150 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period ?? t cd2umc conf_done high to user mode with clkusr option on (4) t cd2cu + (8532 clkusr period) ?? t ch dclk high time (5) 3.6 4.5 ? ns t cl dclk low time (5) 3.6 4.5 ? ns t clk dclk period (5) 810 ? ns f max dclk frequency ? 125 100 mhz notes to ta bl e 10 ?5 : (1) this information is preliminary. (2) use these timing parameters when you use the decompression and/or design security features. (3) you can obtain this value if you do not delay the configuration by extending the nconfig or nstatus low pulse width. (4) the minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for starting the device. (5) adding up t ch and t cl equals to t clk . when ep4se230 t ch is 3.6 ns (min), t cl must be 4.4 ns and vice versa. (6) applicable for ep4se230, ep4se360, ep4sgx70, ep4sgx110, ep4s gx180, ep4sgx230, ep4sgx290 (excep t f45 package), ep4sgx360 (except f45 package), ep4s40g2, ep4s100g2 devices. (7) applicable for ep4se530, ep4se820, ep4sgx290 (only for f45 p ackage), ep 4sgx360 (only for f45 packa ge), ep4sgx530, ep4s40g5, ep4s100g3, ep4s100g4, ep4s100g5 devices. table 10?5. fpp timing parameters for stratix iv devices with the decompression and/or design security features enabled (note 1) , (2) (part 2 of 2) symbol parameter minimum maximum units stratix iv (6) stratix iv (7) stratix iv (6) stratix iv (7) 10?16 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fa s t a c tive se r ial configu r ation (se r ial configu r ation devi c e s ) stratix iv device handbook volume 1 ? march 2010 altera corporation the largest serial configuration device currently supports 128 mbits of configuration bitstream. use the stratix iv decompression features or select an fpp or ps configuration scheme for ep4se360, ep4sgx290, ep4s40g5, ep4s100g3 and larger devices. f for more information about serial configuration devices, refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet chapter in volume 2 of the configuration handbook . serial configuration devices provide a serial interface to access configuration data. during device configuration, stratix iv devices read configuration data using the serial interface, decompress data if necessary, and configure their sram cells. this scheme is referred to as the as configuration scheme because the stratix iv device controls the configuration interface. this scheme contrasts with the ps configuration scheme where the configuration device controls the interface. 1 the stratix iv decompression and design security features are fully available when configuring your stratix iv device using fast as mode. serial configuration devices have a four-pin interface: serial clock input ( dclk ), serial data output ( data ), as data input ( asdi ), and an active-low chip select ( ncs ). this four-pin interface connects to stratix iv device pins, as shown in figure 10?6 . you can power the epcs serial configuration device with 3.0 v when you configure the stratix iv fpga using active serial (as) configuration mode. this is feasible because the power supply to the epcs device ranges between 2.7 v and 3.6 v. you do not need a dedicated 3.3 v power supply to power the epcs device. the epcs device and the vccpgm pins on the stratix iv device may share the same 3.0 v power supply. figure 10?6. single device fast as configuration notes to figure 10?6 : (1) connect the pull-up resistors to v ccpgm at a 3.0-v supply. (2) stratix iv devices use the asdo -to- asdi path to control the configuration device. data dclk ncs asdi data0 dclk ncso asdo serial configuration device stratix iv device 10 k 10 k 10 k v ccpgm (1) gnd nceo nce nstatus nconfig conf_done (2) msel1 msel0 n .c. msel2 gnd v ccpgm v ccpgm (1) v ccpgm (1) chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?17 fa s t a c tive se r ial configu r ation (se r ial configu r ation devi c e s ) ? march 2010 altera corporation stratix iv device handbook volume 1 upon power-up, the stratix iv devices go through a por. the por delay depends on the porsel pin setting. when porsel is driven low, the standard por time is 100 ms < t por < 300 ms. when porsel is driven high, the fast por time is 4ms chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?19 fa s t a c tive se r ial configu r ation (se r ial configu r ation devi c e s ) ? march 2010 altera corporation stratix iv device handbook volume 1 figure 10?7 shows the pin connections for the multi-device fast as configuration. as shown in figure 10?7 , the nstatus and conf_done pins on all target devices are connected together with external pull-up resistors. these pins are open-drain bidirectional pins on the devices. when the first device asserts nceo (after receiving all of its configuration data), it releases its conf_done pin. but the subsequent devices in the chain keep this shared conf_done line low until they have received their configuration data. when all target devices in the chain have received their configuration data and have released conf_done , the pull-up resistor drives a high level on this line and all devices simultaneously enter initialization mode. if an error occurs at any point during configuration, the nstatus line is driven low by the failing device. if you enable the auto-restart configuration after error option, reconfiguration of the entire chain begins after a reset time-out period (a maximum of 500 s). if you did not enable the auto-restart configuration after error option, the external system must monitor nstatus for errors and then pulse nconfig low to restart configuration. the external system can pulse nconfig if it is under system control rather than tied to v ccgpm . 1 while you can cascade stratix iv devices, you cannot cascade or chain together serial configuration devices. figure 10?7. multi-device fast as configuration notes to figure 10?7 : (1) connect the pull-up resistors to v ccpgm at a 3.0-v supply. (2) connect the repeater buffers between the stratix iv master and slave device(s) for data[0] and dclk . this is to prevent potential signal integrity and clock skew problems. data dclk ncs asdi data0 dclk ncso asdo serial configuration device stratix iv device master stratix iv device slave 10 k 10 k gnd nceo nce nstatus conf_done data0 dclk nceo nce nstatus conf_done 10 k nconfig nconfig n .c. msel1 msel0 gnd msel2 v ccpgm msel1 msel0 msel2 gnd v ccpgm v ccpgm (1) v ccpgm (1) v ccpgm (1) bu ffers (2) 10?20 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fa s t a c tive se r ial configu r ation (se r ial configu r ation devi c e s ) stratix iv device handbook volume 1 ? march 2010 altera corporation if the configuration bitstream size exceeds the capacity of a serial configuration device, you must select a larger configuration device and/or enable the compression feature. when configuring multiple devices, the size of the bitstream is the sum of the individual device configuration bitstreams. a system may have multiple devices that contain the same configuration data. in active serial chains, you can implement this by storing one copy of the .sof in the serial configuration device. the same copy of the .sof configures the master stratix iv device and all remaining slave devices concurrently. all stratix iv devices must be the same density and package. to configure four identical stratix iv devices with the same .sof , you can set up the chain as shown in figure 10?8 . the first device is the master device and its msel pins must be set to select as configuration. the other three slave devices are set up for concurrent configuration and their msel pins must be set to select ps configuration. the nce input pins from the master and slave are connected to gnd, and the data and dclk pins connect in parallel to all four devices. during the configuration cycle, the master device reads its configuration data from the serial configuration device and transmits the configuration data to all three slave devices, configuring all of them simultaneously. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?21 fa s t a c tive se r ial configu r ation (se r ial configu r ation devi c e s ) ? march 2010 altera corporation stratix iv device handbook volume 1 figure 10?8 shows the multi-device fast as configuration when the devices receive the same data using a single .sof . estimating active serial configuration time active serial configuration time is dominated by the time it takes to transfer data from the serial configuration device to the stratix iv device. this serial interface is clocked by the stratix iv dclk output (generated from an internal oscillator) and must be set to 40 mhz (25 ns) .therefore, the minimum configuration time estimate for an ep4se230 device (94, 600, 000 bits of uncompressed data) is: rbf size (minimum dclk period / 1 bit per dclk cycle) = estimated minimum configuration time 94, 600, 000 bits (25 ns / 1 bit) = 2365 ms 1 the calculation above is based on a preliminary uncompressed .rbf size. the final .rbf size will be available after the quartus ii software is able to generate the .rbf . figure 10?8. multi-device fast as configuration when the devices receive the same data using a single .sof notes to figure 10?8 : (1) connect the pull-up resistors to v ccpgm at a 3.0-v supply. (2) connect the repeater buffers between the stratix iv master and slave device(s) for data[0] and dclk . this is to prevent potential signal integrity and clock skew problems. data dclk ncs asdi data0 dclk ncso asdo serial configuration device stratix iv device master 10 k 10 k gnd nceo nce nstatus conf_done data0 dclk nceo nce nstatus conf_done 10 k nconfig nconfig n .c. msel1 msel0 msel2 msel1 msel0 gnd msel2 v ccpgm data0 dclk stratix iv device slave stratix iv device slave stratix iv device slave nceo nce nstatus conf_done nconfig n .c. msel1 msel0 gnd msel2 v ccpgm data0 dclk nceo nce nstatus conf_done nconfig n .c. msel1 msel0 gnd msel2 v ccpgm gnd v ccpgm v ccpgm (1) v ccpgm (1) v ccpgm (1) bu ffers (2) gnd n .c. 10?22 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices fa s t a c tive se r ial configu r ation (se r ial configu r ation devi c e s ) stratix iv device handbook volume 1 ? march 2010 altera corporation enabling compression reduces the amount of configuration data that is transmitted to the stratix iv device, which also reduces configuration time. on average, compression reduces configuration time, depending on the design. programming serial configuration devices serial configuration devices are non-volatile, flash-memory-based devices. you can program these devices in-system using the usb-blaster?, ethernetblaster?, or byteblaster? ii download cable. alternatively, you can program them using the altera programming unit (apu), supported third-party programmers, or a microprocessor with the srunner software driver. you can perform in-system programming of serial configuration devices using the conventional as programming interface or the jtag interface solution. because serial configuration devices do not support the jtag interface, the conventional method to program them is using the as programming interface. the configuration data used to program serial configuration devices is downloaded using programming hardware. during in-system programming, the download cable disables device access to the as interface by driving the nce pin high. stratix iv devices are also held in reset by a low level on nconfig . after programming is complete, the download cable releases nce and nconfig , allowing the pull-down and pull-up resistors to drive gnd and v ccpgm , respectively. figure 10?9 shows the download cable connections for the serial configuration device. altera has developed serial flashloader (sfl), an in-system programming solution for serial configuration devices using the jtag interface. this solution requires the stratix iv device to be a bridge between the jtag interface and the serial configuration device. f for more information about sfl, refer to an 370: using the serial flashloader with quartus ii software . f for more information about the usb-blaster download cable, refer to the usb-blaster download cable user guide . for more information about the byteblaster ii cable, refer to the byteblaster ii download cable user guide . for more information about the ethernetblaster download cable, refer to the ethernetblaster communications cable user guide. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?23 fa s t a c tive se r ial configu r ation (se r ial configu r ation devi c e s ) ? march 2010 altera corporation stratix iv device handbook volume 1 you can program serial configuration devices with the quartus ii software using the altera programming hardware and the appropriate configuration device programming adapter. in production environments, you can program serial configuration devices using multiple methods. you can use altera programming hardware or other third-party programming hardware to program blank serial configuration devices before they are mounted on pcbs. alternatively, you can use an on-board microprocessor to program the serial configuration device in-system using c-based software drivers provided by altera. you can program a serial configuration device in-system by an external microprocessor using srunner. srunner is a software driver developed for embedded serial configuration device programming, which can be easily customized to fit in different embedded systems. srunner is able to read raw programming data (. rpd ) and write to serial configuration devices. the serial configuration device programming time using srunner is comparable to the programming time with the quartus ii software. f for more information about srunner, refer to an 418: srunner: an embedded solution for serial configuration device programming and the source code on the altera website at www.altera.com . figure 10?9. in-system programming of serial configuration devices notes to figure 10?9 : (1) connect these pull-up resistors to v ccpgm at a 3.0-v supply. (2) power up the usb-byteblaster, byteblaster ii, or ethernetblaster cable?s v cc(trgt) with v ccpgm . data dclk ncs asdi data0 dclk ncso nce nconfig nstatus nceo conf_done asdo v ccpgm 10 k 10 k 10 k 10 k stratix iv device serial configuration device pin 1 usb blaster or byteblaser ii (as mode) 10-pin male header n .c. (2) msel1 msel0 gnd msel2 v ccpgm v ccpgm (1) v ccpgm (1) v ccpgm (1) 10?24 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices pa ss ive ser ial configu r ation stratix iv device handbook volume 1 ? march 2010 altera corporation f for more information about programming serial configuration devices, refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet chapter in volume 2 of the configuration handbook . guidelines for connecting serial configuration devices on an as interface for single- and multi-device as configurations, the board trace length and loading between the supported serial configuration device and the stratix iv device family must follow the recommendations listed in table 10?6 . passive serial configuration you can program ps configuration for stratix iv devices using an intelligent host, such as a max ii device or microprocessor with flash memory, or a download cable. in the ps scheme, an external host (a max ii device, embedded processor, or host pc) controls configuration. configuration data is clocked into the target stratix iv device using the data0 pin at each rising edge of dclk. 1 the stratix iv decompression and design security features are fully available when configuring your stratix iv device using ps mode. ps configuration using a max ii device as an external host in this configuration scheme, you can use a max ii device as an intelligent host that controls the transfer of configuration data from a storage device, such as flash memory, to the target stratix iv device. you can store configuration data in .rbf , .hex , or .ttf format. table 10?6. maximum trace length and loading for the as configuration stratix iv device as pins maximum board trace length from the stratix iv device to the serial configuration device (inches) maximum board load (pf) dclk 10 15 data[0] 10 30 ncso 10 30 asdo 10 30 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?25 pa ss ive ser ial configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 figure 10?10 shows the configuration interface connections between a stratix iv device and a max ii device for single device configuration. after power-up, stratix iv devices go through a por. the por delay depends on the porsel pin setting. when porsel is driven low, the standard por time is 100 ms < t por < 300 ms. when porsel is driven high, the fast por time is 4ms chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?27 pa ss ive ser ial configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. the low signal on the nstatus pin also alerts the max ii device that there is an error. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the device and pin options dialog box) is turned on, the stratix iv device releases nstatus after a reset time-out period (a maximum of 500 s). after nstatus is released and pulled high by a pull-up resistor, the max ii device can try to reconfigure the target device without needing to pulse nconfig low. if this option is turned off, the max ii device must generate a low-to-high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. the max ii device can also monitor the conf_done and init_done pins to ensure successful configuration. the conf_done pin must be monitored by the max ii device to detect errors and determine when programming completes. if all configuration data is sent, but conf_done or init_done have not gone high, the max ii device must reconfigure the target device. 1 if you use the optional clkusr pin and nconfig is pulled low to restart configuration during device initialization, you must ensure that clkusr continues toggling during the time nstatus is low (a maximum of 500 s). when the device is in user-mode, you can initiate a reconfiguration by transitioning the nconfig pin low-to-high. the nconfig pin must be low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. figure 10?11 shows how to configure multiple devices using a max ii device. this circuit is similar to the ps configuration circuit for a single device, except the stratix iv devices are cascaded for multi-device configuration. figure 10?11. multi-device ps configuration using an external host note to figure 10?11 : (1) connect the resistor to a supply that provides an acceptable input signal for all stratix iv devices in the chain. v ccpgm must be high enough to meet the v ih specification of the i/o on the device and the external host. altera recommends you power up all configuration system i/os wit h v ccpgm . conf_done nstatus nce data 0 nconfig stratix iv device 1 stratix iv device 2 memory addr data0 gnd 10 k 10 k dclk conf_done nstatus nce data0 nconfig dclk nceo nceo n.c. external host (max ii device or microprocessor) msel1 msel0 gnd msel2 v ccpgm msel1 msel0 gnd msel2 v ccpgm v ccpgm (1) v ccpgm (1) 10?28 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices pa ss ive ser ial configu r ation stratix iv device handbook volume 1 ? march 2010 altera corporation in multi-device ps configuration, the first device?s nce pin is connected to gnd, while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the first device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. the second device in the chain begins configuration within one clock cycle. therefore, the transfer of data destinations is transparent to the max ii device. all other configuration pins ( nconfig, nstatus, dclk, data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. because all nstatus and conf_done pins are tied together, if any device detects an error, configuration stops for the entire chain and you must reconfigure the entire chain. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this behavior is similar to a single device detecting an error. if the auto-restart configuration after error option is turned on, the devices release their nstatus pins after a reset time-out period (a maximum of 500 s). after all nstatus pins are released and pulled high, the max ii device can try to reconfigure the chain without needing to pulse nconfig low. if this option is turned off, the max ii device must generate a low-to-high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. in your system, you can have multiple devices that contain the same configuration data. to support this configuration scheme, all device nce inputs are tied to gnd, while the nceo pins are left floating. all other configuration pins ( nconfig, nstatus, dclk, data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices start and complete configuration at the same time. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?29 pa ss ive ser ial configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 figure 10?12 shows multi-device ps configuration when both stratix iv devices are receiving the same configuration data. you can use a single configuration chain to configure stratix iv devices with other altera devices. to ensure that all devices in the chain complete configuration at the same time, or that an error flagged by one device initiates reconfiguration in all devices, all of the device conf_done and nstatus pins must be tied together. f for more information about configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in volume 2 of the configuration handbook . figure 10?12. multiple-device ps configuration when both devices receive the same data notes to figure 10?12 : (1) connect the resistor to a supply that provides an acceptable input signal for all stratix iv devices in the chain. v ccpgm must be high enough to meet the v ih specification of the i/o on the device and the external host. altera recommends you power up all configuration system i/os wit h v ccpgm . (2) the nceo pins of both devices are left unconnected when configuring the same configuration data into multiple devices. conf_done nstatus nce data 0 nconfig stratix iv device stratix iv device memory addr data0 gnd 10 k 10 k dclk conf_done nstatus nce data0 nconfig dclk nceo nceo n.c. external host (max ii device or microprocessor) msel1 msel0 gnd msel2 v ccpgm msel1 msel0 gnd msel2 v ccpgm n.c. gnd (2) (2) v ccpgm (1) v ccpgm (1) 10?30 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices pa ss ive ser ial configu r ation stratix iv device handbook volume 1 ? march 2010 altera corporation ps configuration timing figure 10?13 shows the timing waveform for ps configuration when using a max ii device as an external host. table 10?7 lists the timing parameters for stratix iv devices for ps configuration. figure 10?13. ps configuration timing waveform (note 1) notes to figure 10?13 : (1) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus, and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) after power-up, the stratix iv device holds nstatus low for the time of the por delay. (3) after power-up, before and during configuration, conf_done is low. (4) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (5) data[0] is available as a user i/o pin after configuration. the st ate of this pin depends on the dual-purpose pin settings. nconfig nstatus (2) conf_done (3) dclk data user i/o init_done bit 0 bit 1 bit 2 bit 3 bit n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mode (5) (4) table 10?7. ps timing parameters for stratix iv devices (part 1 of 2) (note 1) symbol parameter minimum maximum units t cf2cd nconfig low to conf_done low ? 800 ns t cf2st0 nconfig low to nstatus low ? 800 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 10 500 (2) s t cf2st1 nconfig high to nstatus high ? 500 (2) s t cf2ck nconfig high to first rising edge on dclk 500 ? s t st2ck nstatus high to first rising edge of dclk 2? s t dsu data setup time before rising edge on dclk 4?ns t dh data hold time after rising edge on dclk 0?ns t ch dclk high time (4) 3.2 ? ns t cl dclk low time (4) 3.2 ? ns t clk dclk period (4) 8?ns f max dclk frequency ? 125 mhz t r input rise time ? 40 ns chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?31 pa ss ive ser ial configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 f device configuration options and how to create configuration files are described in the device configuration options and configuration file formats chapters in volume 2 of the configuration handbook . ps configuration using a microprocessor in this ps configuration scheme, a microprocessor controls the transfer of configuration data from a storage device, such as flash memory, to the target stratix iv device. for more information about configuration and timing information, refer to ?ps configuration using a max ii device as an external host? on page 10?24 . this section is also applicable when using a microprocessor as an external host. ps configuration using a download cable 1 in this section, the generic term ?download cable? includes the altera usb-blaster universal serial bus (usb) port download cable, masterblaster serial/usb communications cable, byteblaster ii parallel port download cable, byteblastermv parallel port download cable, and ethernetblaster download cable. in a ps configuration with a download cable, an intelligent host (such as a pc) transfers data from a storage device to the device using the usb blaster, masterblaster, byteblaster ii, ethernetblaster, or byteblastermv cable. after power-up, stratix iv devices go through a por. the por delay depends on the porsel pin setting. when porsel is driven low, the standard por time is 100 ms < t por < 300 ms. when porsel is driven high, the fast por time is 4ms chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?33 pa ss ive ser ial configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 you can use a download cable to configure multiple stratix iv devices by connecting each device?s nceo pin to the subsequent device?s nce pin. the first device?s nce pin is connected to gnd, while its nceo pin is connected to the nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. all other configuration pins ( nconfig, nstatus, dclk, data0 , and conf_done ) are connected to every device in the chain. because all conf_done pins are tied together, all devices in the chain initialize and enter user mode at the same time. in addition, because the nstatus pins are tied together, the entire chain halts configuration if any device detects an error. the auto-restart configuration after error option does not affect the configuration cycle because you must manually restart the configuration in the quartus ii software when an error occurs. figure 10?15 shows how to configure multiple stratix iv devices with a download cable. figure 10?15. multi-device ps configuration using a usb blaster, ethernetblaster, masterblaster, byteblaster ii, or byteblastermv cable notes to figure 10?15 : (1) connect the pull-up resistor to the same supply voltage (v ccpgm ) as the usb blaster, masterblaster ( vio pin), byteblaster ii, byteblastermv, or ethernetblaster cable. (2) you only need the pull-up resistors on data0 and dclk if the download cable is the only configuration scheme used on your board. this is to ensure that data0 and dclk are not left floating after configuration. for example, if y ou are also using a configuration device, you do not need the pull-up resistors on data0 and dclk . (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io must match the device?s v ccpgm . for more information about this value, refer to the masterblaster serial/usb communications cable user guide . in the usb-blaster, byteblaster ii, and byteblastermv cables, this pin is a no connect. stratix iv device 1 stratix iv device 2 nce nconfig conf_done dclk nce nconfig conf_done dclk nceo gnd (ps mode) v ccpgm (1) nstatus nstatus data0 data0 gnd 10 k 10 k 10 k 10 k 10 k pin 1 download cable 10-pin male header nceo n.c. gnd v io (3 ) (2) (2) msel1 msel0 gnd msel2 msel1 msel0 gnd msel2 v ccpgm (1) v ccpgm (1) v ccpgm (1) v ccpgm (1) v ccpgm (1) v ccpgm (1 ) v ccpgm (1) 10?34 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices jtag configu r ation stratix iv device handbook volume 1 ? march 2010 altera corporation f for more information about how to use the usb blaster, masterblaster, byteblaster ii, or byteblastermv cables, refer to the following user guides: usb-blaster download cable user guide masterblaster serial/usb communications cable user guide byteblaster ii download cable user guide byteblastermv download cable user guide ethernetblaster communications cable user guide jtag configuration jtag has developed a specification for boundary-scan testing. this boundary-scan test (bst) architecture offers the capability to efficiently test components on pcbs with tight lead spacing. the bst architecture can test pin connections without using physical test probes and capture functional data while a device is operating normally. you can also use jtag circuitry to shift configuration data into the device. the quartus ii software automatically generates .sof s that you can use for jtag configuration with a download cable in the quartus ii software programmer. f for more information about jtag boundary-scan testing and commands available using stratix iv devices, refer to the following documents: jtag boundary scan testing chapter programming support for jam stapl language stratix iv devices are designed such that jtag instructions have precedence over any device configuration modes. therefore, jtag configuration can take place without waiting for other configuration modes to complete. for example, if you attempt jtag configuration of stratix iv devices during ps configuration, ps configuration is terminated and jtag configuration begins. 1 you cannot use the stratix iv decompression or design security features if you are configuring your stratix iv device when using jtag-based configuration. 1 a device operating in jtag mode uses four required pins, tdi, tdo, tms , and tck, and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi, tms , and trst pins have weak internal pull-up resistors (typically 25 k ). the jtag output pin tdo and all jtag input pins are powered by 2.5-v/3.0-v v ccpd . all the jtag pins only support the lvttl i/o standard. all user i/o pins are tri-stated during jtag configuration. f all the jtag pins are powered by the v ccpd power supply of i/o bank 1a. for more information about how to connect a jtag chain with multiple voltages across the devices in the chain, refer to the jtag boundary scan testing chapter . chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?35 jtag configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 during jtag configuration, you can download data to the device on the pcb through the usb blaster, masterblaster, byteblaster ii, ethernetblaster, or byteblastermv download cable. configuring devices through a cable is similar to programming devices in-system, except you must connect the trst pin to v ccpd . this ensures that the tap controller is not reset. figure 10?16 shows jtag configuration of a single stratix iv device when using a download cable. to configure a single device in a jtag chain, the programming software places all other devices in bypass mode. in bypass mode, devices pass programming data from the tdi pin to the tdo pin through a single bypass register without being affected internally. this scheme enables the programming software to program or verify the target device. configuration data driven into the device appears on the tdo pin one clock cycle later. figure 10?16. jtag configuration of a single device using a download cable notes to figure 10?16 : (1) connect the pull-up resistor to the same supply voltage as the usb blaster, masterblaster ( vio pin), byteblaster ii, byteblastermv, or ethernetblaster cable. the voltage supply can be connected to the v ccpd of the device. (2) connect the nconfig and msel[2..0] pins to support a non-jtag configuration scheme. if you only use the jtag configuration, connect nconfig to v ccpgm and msel[2..0] to gnd. pull dclk either high or low, whichever is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io must match the device?s v ccpd . for more information about this value, refer to the masterblaster serial/usb communications cable user guide . in the usb-blaster, byteblaster ii, and byteblastermv cable, this pin is a no connect. (4) you must connect nce to gnd or driven low for successful jtag configuration. (5) the pull-up resistor value can vary from 1 k to 10 k . nce (4) msel[2..0] nconfig conf_done v ccpd (1) gnd gnd (2) (2) v ccpd (1) 10 k 10 k nstatus pin 1 download cable 10-pin male header (jtag mode) (top view) gnd tck tdo tms tdi 1 k gnd v io (3) stratix i v de vice nce0 n .c. trst dclk (2) v ccpgm v ccpgm v ccpd (1) v ccpd (1) (5) (5) 10?36 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices jtag configu r ation stratix iv device handbook volume 1 ? march 2010 altera corporation the quartus ii software verifies successful jtag configuration upon completion. at the end of configuration, the software checks the state of conf_done through the jtag port. when the quartus ii software generates a jam file (. jam) for a multi-device chain, it contains instructions so that all the devices in the chain are initialized at the same time. if conf_done is not high, the quartus ii software indicates that configuration has failed. if conf_done is high, the software indicates that configuration was successful. after the configuration bitstream is transmitted serially using the jtag tdi port, the tck port is clocked an additional 1,094 cycles to perform device initialization. stratix iv devices have dedicated jtag pins that always function as jtag pins. not only can you perform jtag testing on stratix iv devices before and after, but also during configuration. while other device families do not support jtag testing during configuration, stratix iv devices support the bypass, id code, and sample instructions during configuration without interrupting configuration. all other jtag instructions may only be issued by first interrupting configuration and reprogramming the i/o pins using the config_io instruction. the config_io instruction allows i/o buffers to be configured using the jtag port and when issued, interrupts configuration. this instruction allows you to perform board-level testing prior to configuring the stratix iv device or waiting for a configuration device to complete configuration. after configuration has been interrupted and jtag testing is complete, you must reconfigure the part using jtag ( pulse_config instruction) or by pulsing nconfig low. the chip-wide reset ( dev_clrn ) and chip-wide output enable ( dev_oe ) pins on stratix iv devices do not affect jtag boundary-scan or programming operations. toggling these pins does not affect jtag operations (other than the usual boundary-scan operation). when designing a board for jtag configuration for stratix iv devices, consider the dedicated configuration pins. table 10?8 lists how these pins are connected during jtag configuration. table 10?8. dedicated configuration pin connections during jtag configuration (part 1 of 2) signal description nce on all stratix iv devices in the chain, nce must be driven low by connecting it to ground, pulling it low using a resistor, or driving it by some control circuitry. for devices that are also in multi-device fpp, as, or ps configuration chains, the nce pins must be connected to gnd during jtag configuration or jtag must be configured in the same order as the configuration chain. nceo on all stratix iv devices in the chain, you can leave nceo floating or connected to the nce of the next device. msel do not leave these pins floating. these pins support whichever non-jtag configuration is used in production. if you only use jtag configuration, tie these pins to gnd. nconfig driven high by connecting to v ccpgm , pulling up using a resistor, or driven high by some control circuitry. nstatus pull to v ccpgm using a 10-k resistor. when configuring multiple devices in the same jtag chain, each nstatus pin must be pulled up to v ccpgm individually. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?37 jtag configu r ation ? march 2010 altera corporation stratix iv device handbook volume 1 when programming a jtag device chain, one jtag-compatible header is connected to several devices. the number of devices in the jtag chain is limited only by the drive capability of the download cable. when four or more devices are connected in a jtag chain, altera recommends buffering the tck, tdi , and tms pins with an on-board buffer. jtag-chain device programming is ideal when the system contains multiple devices, or when testing your system using jtag bst circuitry. figure 10?17 shows a multi-device jtag configuration when using a download cable. conf_done pull to v ccpgm using a 10-k resistor. when configuring multiple devices in the same jtag chain, each conf_done pin must be pulled up to v ccpgm individually. conf_done going high at the end of jtag configuration indicates successful configuration. dclk do not leave dclk floating. drive low or high, whichever is more convenient on your board. table 10?8. dedicated configuration pin connections during jtag configuration (part 2 of 2) signal description figure 10?17. jtag configuration of multiple devices using a download cable notes to figure 10?17 : (1) connect the pull-up resistor to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii, byteblastermv, or ethernetblaster cable. connect the voltage supply to v ccpd of the device. (2) connect the nconfig and msel[2..0] pins to support a non-jtag configuration scheme. if you only use jtag configuration, connect nconfig to v ccpgm and msel[2..0] to gnd. pull dclk either high or low, whichever is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io must match the device?s v ccpd . for more information about this value, refer to the masterblaster serial/usb communications cable user guide . in the usb-blaster, byteblaster ii, and byteblastermv cables, this pin is a no connect. (4) you must connect nce to gnd or drive it low for successful jtag configuration. (5) the pull-up resistor value can vary from 1 k to 10 k . tms tck download cable 10-pin male header (jtag mode) tdi tdo v ccpd v ccpd (1) pin 1 nstatus nconfig msel[2..0] nce (4) v ccpgm conf_done tms tck tdi tdo nstatus nconfig msel[2..0] nce (4) conf_done tms tck tdi tdo nstatus nconfig msel[2..0] nce (4) conf_done (1) (2) (2) (2) (2) (2) (2) v io (3) stratix i v de vice stratix i v de vice stratix ii or stratix ii gx de vice trst trst trst 10 k 10 k 10 k 10 k 10 k 1 k 10 k dclk dclk dclk (2) (2) (2) stratix i v de vice v ccpd (1) v ccpd (1) v ccpd (1) v ccpd (1) v ccpgm v ccpgm v ccpgm v ccpgm v ccpgm (5) (5) 10?38 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices jtag configu r ation stratix iv device handbook volume 1 ? march 2010 altera corporation you must connect the nce pin to gnd or drive it low during jtag configuration. in multi-device fpp, as, and ps configuration chains, the first device?s nce pin is connected to gnd, while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. in addition, the conf_done and nstatus signals are all shared in multi-device fpp, as, or ps configuration chains so the devices can enter user mode at the same time after configuration is complete. when the conf_done and nstatus signals are shared among all the devices, you must configure every device when jtag configuration is performed. if you only use jtag configuration, altera recommends that you connect the circuitry as shown in figure 10?17 , where each of the conf_done and nstatus signals are isolated, so that each device can enter user mode individually. after the first device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. therefore, if these devices are also in a jtag chain, ensure the nce pins are connected to gnd during jtag configuration or that the devices are jtag configured in the same order as the configuration chain. as long as the devices are jtag configured in the same order as the multi-device configuration chain, the nceo of the previous device drives the nce of the next device low when it has successfully been jtag configured. you can place other altera devices that have jtag support in the same jtag chain for device programming and configuration. 1 jtag configuration support is enhanced and allows more than 17 stratix iv devices to be cascaded in a jtag chain. f for more information about configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in volume 2 of the configuration handbook . you can configure stratix iv devices using multiple configuration schemes on the same board. combining jtag configuration with as configuration on your board is useful in the prototyping environment because it allows multiple methods to configure your fpga. f for more information about combining jtag configuration with other configuration schemes, refer to the combining different configuration schemes chapter in volume 2 of the configuration handbook . chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?39 devi c e configu r ation pin s ? march 2010 altera corporation stratix iv device handbook volume 1 figure 10?18 shows jtag configuration of a stratix iv device using a microprocessor. jam stapl jam ? stapl, jedec standard jesd-71, is a standard file format for in-system programmability (isp) purposes. jam stapl supports programming or configuration of programmable devices and testing of electronic systems, using the ieee 1149.1 jtag interface. jam stapl is a freely licensed open standard. the jam player provides an interface for manipulating the ieee std. 1149.1 jtag tap state machine. f for more information about jtag and jam stapl in embedded environments, refer to using jam stapl for isp via an embedded processor . to download the jam player, visit the altera website at www.altera.com . device configuration pins the following tables list the connections and functionality of all the configuration- related pins on stratix iv devices. table 10?9 lists the stratix iv configuration pins and their power supply. figure 10?18. jtag configuration of a single device using a microprocessor notes to figure 10?18 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for all stratix iv devices in the chain. v ccpgm must be high enough to meet the v ih specification of the i/o on the device. (2) connect the nconfig and msel[2..0] pins to support a non-jtag configuration scheme. if you use only the jtag configuration, connect nconfig to v ccgpm and msel[2..0] to gnd. pull dclk either high or low, whichever is convenient on your board. (3) connect nce to gnd or drive it low for successful jtag configuration. (4) the microprocessor must use the same i/o standard as v ccpd to drive the jtag pins. trst tdi (4) tck (4) tms (4) tdo (4) microprocessor memory addr data stratix iv device nstatus conf_done v ccpgm (1) 10 k 10 k (3) nce nconfig n.c. gnd (2) (2) v ccpd nceo msel[2..0] dclk (2) v ccpgm (1) table 10?9. stratix iv configuration pin summary (part 1 of 2) (note 1) description input/output dedicated powered by configuration mode tdi input yes v ccpd jtag tms input yes v ccpd jtag tck input yes v ccpd jtag trst input yes v ccpd jtag tdo output yes v ccpd jtag crc_error output ? pull-up optional, all modes 10?40 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices devi c e configu r ation pin s stratix iv device handbook volume 1 ? march 2010 altera corporation data0 input ? v ccpgm /v ccio (3) all modes except jtag data[7..1] input ? v ccpgm/ v ccio (3) fpp init_done output ? pull-up optional, all modes clkusr input ? v ccpgm /v ccio (3) optional nstatus bidirectional yes v ccpgm /pull-up all modes nce input yes v ccpgm all modes conf_done bidirectional yes v ccpgm /pull-up all modes nconfig input yes v ccpgm all modes porsel input yes v cc (2) all modes asdo output yes v ccpgm as ncso output yes v ccpgm as dclk input yes v ccpgm ps, fpp output yes v ccpgm as nio_pullup input yes v cc (2) all modes nceo output yes v ccpgm all modes msel[2..0] input yes v cc (2) all modes notes to ta bl e 10 ?9 : (1) the total number of pins is 29. the total number of dedicated pins is 18. (2) although msel[2..0] , porsel , and nio_pullup are powered up by v cc , altera recommends you connect these pins to v ccpgm or gnd directly without using a pull-up or pull-down resistor. (3) these pins are powered up by v ccpgm during configuration. these pins are powered up by v ccio if they are used as regular i/o in user mode. table 10?9. stratix iv configuration pin summary (part 2 of 2) (note 1) description input/output dedicated powered by configuration mode chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?41 devi c e configu r ation pin s ? march 2010 altera corporation stratix iv device handbook volume 1 table 10?10 lists the dedicated configuration pins. you must connect these pins properly on your board for successful configuration. some of these pins may not be required for your configuration schemes. table 10?10. dedicated configuration pins on the stratix iv device (part 1 of 4) pin name user mode configuration scheme pin type description vccpgm n/a all power dedicated power pin. use this pin to power all dedicated configuration inputs, dedicated configuration outputs, dedicated configuration bidirectional pins, and some of the dual functional pins that are used for configuration. you must connect this pin to 1.8, 2.5, or 3.0 v. v ccpgm must ramp-up from 0 v to v ccpgm within 100 ms when porsel is low or 4 ms when porsel is high. if v ccpgm is not ramped up within this specified time, your stratix iv device will not configure successfully. if your system does not allow a v ccpgm ramp-up within 100 ms or 4 ms, you must hold nconfig low until all power supplies are stable. vccpd n/a all power dedicated power pin. use this pin to power the i/o pre-drivers, jtag input and output pins, and design security circuitry. you must connect this pin to 2.5 v or 3.0 v, depending on the i/o standards selected. for the 3.0-v i/o standard, v ccpd = 3.0 v. for the 2.5 v or below i/o standards, v ccpd = 2.5 v. v ccpd must ramp-up from 0 v to 2.5 v / 3.0 v within 100 ms when porsel is low or 4 ms when porsel is high. if v ccpd is not ramped up within this specified time, your stratix iv device will not configure successfully. if your system does not allow a v ccpd to ramp-up time within 100 ms or 4 ms, you must hold nconfig low until all power supplies are stable. porsel n/a all input dedicated input that selects between a standard por time or a fast por time. a logic low selects a standard por time setting of 100 ms < t por < 300 ms and a logic high selects a fast por time setting of 4 ms < t por < 12 ms. the porsel input buffer is powered by v cc and has an internal 5-k pull-down resistor that is always active. tie the porsel pin directly to v ccpgm or gnd. nio_pullup n/a all input dedicated input that chooses whether the internal pull-up resistors on the user i/o pins and dual-purpose i/o pins ( ncso , nasdo , data[7..0] , clkusr , and init_done ) are on or off before and during configuration. a logic high turns off the weak internal pull-up resistors; a logic low turns them on. the nio-pullup input buffer is powered by v cc and has an internal 5-k pull-down resistor that is always active. the nio-pullup can be tied directly to v ccpgm , using a 1-k pull-up resistor or tied directly to gnd, depending on your device requirements. 10?42 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices devi c e configu r ation pin s stratix iv device handbook volume 1 ? march 2010 altera corporation msel[2..0] n/a all input three-bit configuration input that sets the stratix iv device configuration scheme. for the appropriate connections, refer to table 10?1 on page 10?2 . you must hardwire these pins to v ccpgm or gnd. the msel[2..0] pins have internal 5-k pull-down resistors that are always active. nconfig n/a all input configuration control input. pulling this pin low during user-mode causes the device to lose its configuration data, enter a reset state, and tri-state all i/o pins. returning this pin to a logic high level initiates a reconfiguration. configuration is possible only if this pin is high, except in jtag programming mode, when nconfig is ignored. nstatus n/a all bidirectional open-drain the device drives nstatus low immediately after power-up and releases it after the por time. during user mode and regular configuration, this pin is pulled high by an external 10-k resistor. this pin, when driven low by the stratix iv device, indicates that the device has encountered an error during configuration. status output?if an error occurs during configuration, nstatus is pulled low by the target device. status input?if an external source drives the nstatus pin low during configuration or initialization, the target device enters an error state. driving nstatus low after configuration and initialization does not affect the configured device. if you use a configuration device, driving nstatus low causes the configuration device to attempt to configure the device, but because the device ignores transitions on nstatus in user mode, the device does not reconfigure. to initiate a reconfiguration, nconfig must be pulled low. nstatus (continued) ?? ? if v ccpgm is not fully powered up, the following could occur: v ccpgm is powered high enough for the nstatus buffer to function properly and nstatus is driven low. when v ccpgm is ramped up, por trips and nstatus is released after por expires. v ccpgm is not powered high enough for the nstatus buffer to function properly. in this situation, nstatus might appear logic high, triggering a configuration attempt that would fail because por did not yet trip. when v ccpd is powered up, nstatus is pulled low because por did not yet trip. when por trips after v ccpgm is powered up, nstatus is released and pulled high. at that point, reconfiguration is triggered and the device is configured. table 10?10. dedicated configuration pins on the stratix iv device (part 2 of 4) pin name user mode configuration scheme pin type description chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?43 devi c e configu r ation pin s ? march 2010 altera corporation stratix iv device handbook volume 1 conf_done n/a all bidirectional open-drain status output. the target device drives the conf_done pin low before and during configuration. after all the configuration data is received without error and the initialization cycle starts, the target device releases conf_done . status input. after all the data is received and conf_done goes high, the target device initializes and enters user mode. the conf_done pin must have an external 10-k pull-up resistor for the device to initialize. driving conf_done low after configuration and initialization does not affect the configured device. nce n/a all input active-low chip enable. the nce pin activates the device with a low signal to allow configuration. the nce pin must be held low during configuration, initialization, and user mode. in single device configuration, it must be tied low. in multi-device configuration, nce of the first device is tied low, while its nceo pin is connected to nce of the next device in the chain. the nce pin must also be held low for successful jtag programming of the device. nceo n/a all output output that drives low when device configuration is complete. in single device configuration, this pin is left floating. in multi-device configuration, this pin feeds the next device?s nce pin. the nceo of the last device in the chain is left floating. the nceo pin is powered by v ccpgm . asdo n/a as output control signal from the stratix iv device to the serial configuration device in as mode used to read out configuration data. in as mode, asdo has an internal pull-up resistor that is always active. ncso n/a as output output control signal from the stratix iv device to the serial configuration device in as mode that enables the configuration device. in as mode, ncso has an internal pull-up resistor that is always active. table 10?10. dedicated configuration pins on the stratix iv device (part 3 of 4) pin name user mode configuration scheme pin type description 10?44 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices devi c e configu r ation pin s stratix iv device handbook volume 1 ? march 2010 altera corporation dclk n/a synchronous configuration schemes (ps, fpp, as) input (ps, fpp) output (as) in ps and fpp configuration, dclk is the clock input used to clock data from an external source into the target device. data is latched into the device on the rising edge of dclk . in as mode, dclk is an output from the stratix iv device that provides timing for the configuration interface. in as mode, dclk has an internal pull-up resistor (typically 25 k ) that is always active. in as configuration schemes, this pin is driven into an inactive state after configuration completes. you can use this pin as a user i/o during user mode. in ps or fpp schemes that use a control host, you must drive dclk either high or low, whichever is more convenient. in passive schemes, you cannot use dclk as a user i/o during user mode. toggling this pin after configuration does not affect the configured device. data0 n/a in as mode. i/o in ps or fpp mode. ps, fpp, as input data input. in serial configuration modes, bit-wide configuration data is presented to the target device on the data0 pin. in as mode, data0 has an internal pull-up resistor that is always active. after ps or fpp configuration, data0 is available as a user i/o pin. the state of this pin depends on the dual-purpose pin settings. data[7..1] i/o parallel configuration schemes (fpp) inputs data inputs. byte-wide configuration data is presented to the target device on data[7..0] . in serial configuration schemes, they function as user i/o pins during configuration, which means they are tri-stated. after fpp configuration, data[7..1] are available as user i/o pins. the state of these pins depends on the dual-purpose pin settings. table 10?10. dedicated configuration pins on the stratix iv device (part 4 of 4) pin name user mode configuration scheme pin type description chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?45 devi c e configu r ation pin s ? march 2010 altera corporation stratix iv device handbook volume 1 table 10?11 lists the optional configuration pins. if these optional configuration pins are not enabled in the quartus ii software, they are available as general-purpose user i/o pins. therefore, during configuration, these pins function as user i/o pins and are tri-stated with weak pull-up resistors. table 10?11. optional configuration pins pin name user mode pin type description clkusr n/a if option is on. i/o if option is off. input optional user-supplied clock input synchronizes the initialization of one or more devices. enable this pin by turning on the enable user-supplied start-up clock ( clkusr ) option in the quartus ii software. init_done n/a if option is on. i/o if option is off. output open-drain use as a status pin to indicate when the device has initialized and is in user mode. when nconfig is low and during the beginning of configuration, the init_done pin is tri-stated and pulled high due to an external 10-k pull-up resistor. after the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled high and the device enters user mode. thus, the monitoring circuitry must be able to detect a low-to-high transition. enable this pin by turning on the enable init_done output option in the quartus ii software. dev_oe n/a if option is on. i/o if option is off. input optional pin that allows you to override all tri-states on the device. when this pin is driven low, all i/o pins are tri-stated. when this pin is driven high, all i/o pins behave as programmed. enable this pin by turning on the enable device-wide output enable ( dev_oe ) option in the quartus ii software. dev_clrn n/a if option is on. i/o if option is off. input optional pin that allows you to override all clears on all device registers. when this pin is driven low, all registers are cleared. when this pin is driven high, all registers behave as programmed. enable this pin by turning on the enable device-wide reset ( dev_clrn ) option in the quartus ii software. 10?46 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices devi c e configu r ation pin s stratix iv device handbook volume 1 ? march 2010 altera corporation table 10?12 lists the dedicated jtag pins. jtag pins must be kept stable before and during configuration to prevent accidental loading of jtag instructions. the tdi, tms , and trst pins have weak internal pull-up resistors, while tck has a weak internal pull-down resistor (typically 25 k ). if you plan to use the signaltap ? embedded logic array analyzer, you must connect the jtag pins of the stratix iv device to a jtag header on your board. f for more information about the pin connection recommendations, refer to the stratix iv gx device family pin connection guidelines . table 10?12. dedicated jtag pins pin name user mode pin type description tdi n/a te st d ata input serial input pin for instructions as well as test and programming data. data is shifted on the rising edge of tck . the tdi pin is powered by the 2.5-v/3.0-v v ccpd supply. if the jtag interface is not required on your board, you can disable the jtag circuitry by connecting this pin to logic high using a 1-k resistor. tdo n/a te st d ata output serial data output pin for instructions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. the tdo pin is powered by v ccpd . for recommendations about connecting a jtag chain with multiple voltages across the devices in the chain, refer to the jtag boundary scan testing chapter. if the jtag interface is not required on your board, you can disable the jtag circuitry by leaving this pin unconnected. tms n/a te st mo de select input pin that provides the control signal to determine the transitions of the tap controller state machine. tms is evaluated on the rising edge of tck . therefore, you must set up tms before the rising edge of tck . transitions within the state machine occur on the falling edge of tck after the signal is applied to tms . the tms pin is powered by 2.5-v/3.0-v v ccpd . if the jtag interface is not required on your board, you can disable the jtag circuitry by connecting this pin to logic high using a 1-k resistor. tck n/a test clock input clock input to the bst circuitry. some operations occur at the rising edge, while others occur at the falling edge. the tck pin is powered by the 2.5-v/3.0-v v ccpd supply. it is expected that the clock input waveform have a nominal 50% duty cycle. if the jtag interface is not required on your board, you can disable the jtag circuitry by connecting tck to gnd. trst n/a test reset input (optional) active-low input to asynchronously reset the boundary-scan circuit. the trst pin is optional according to ieee std. 1149.1. the trst pin is powered by the 2.5-v/3.0-v v ccpd supply. hold tms at 1 or keep tck static while trst is changed from 0 to 1. if the jtag interface is not required on your board, you can disable the jtag circuitry by connecting the trst pin to gnd. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?47 configu r ation data de c omp r e ss ion ? march 2010 altera corporation stratix iv device handbook volume 1 configuration data decompression stratix iv devices support configuration data decompression, which saves configuration memory space and time. this feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compressed bitstream to stratix iv devices. during configuration, the stratix iv device decompresses the bitstream in real time and programs its sram cells. 1 preliminary data indicates that compression typically reduces the configuration bitstream size by 35 to 55% based on the designs used. stratix iv devices support decompression in the fpp (when using a max ii device or microprocessor + flash), fast as, and ps configuration schemes. the stratix iv decompression feature is not available in the jtag configuration scheme. in ps mode, use the stratix iv decompression feature because sending compressed configuration data reduces configuration time. when you enable compression, the quartus ii software generates configuration files with compressed configuration data. this compressed file reduces the storage requirements in the configuration device or flash memory, and decreases the time needed to transmit the bitstream to the stratix iv device. the time required by a stratix iv device to decompress a configuration file is less than the time needed to transmit the configuration data to the device. there are two ways to enable compression for stratix iv bitstreams: before design compilation (in the compiler settings menu) and after design compilation (in the convert programming files window). to enable compression in the project?s compiler settings menu, perform the following steps: 1. on the assignments menu, click device to bring up the settings dialog box. 2. after selecting your stratix iv device, open the device and pin options window. 3. in the configuration settings tab, turn on generate compressed bitstreams (as shown in figure 10?19 ). 10?48 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices configu r ation data de c omp r e ss ion stratix iv device handbook volume 1 ? march 2010 altera corporation you can also enable compression when creating programming files from the convert programming files window. to do this, perform the following steps: 1. on the file menu, click convert programming files . 2. select the programming file type ( .pof , .sram , .hex, .rbf , or .ttf ). 3. for .pof output files, select a configuration device. 4. in the input files to convert box, select sof data . 5. select add file and add a stratix iv device .sof file. 6. select the name of the file you added to the sof data area and click properties . 7. check the compression check box. when multiple stratix iv devices are cascaded, you can selectively enable the compression feature for each device in the chain if you are using a serial configuration scheme. figure 10?20 shows a chain of two stratix iv devices. the first stratix iv device has compression enabled; therefore, receives a compressed bitstream from the configuration device. the second stratix iv device has the compression feature disabled and receives uncompressed data. in a multi-device fpp configuration chain (with a max ii device or microprocessor + flash), all stratix iv devices in the chain must either enable or disable the decompression feature. you cannot selectively enable the compression feature for each device in the chain because of the data and dclk relationship. figure 10?19. enabling compression for stratix iv bitstreams in compiler settings chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?49 remote sy s tem upg r ade s ? march 2010 altera corporation stratix iv device handbook volume 1 you can generate programming files for this setup by clicking convert programming files on the file menu in the quartus ii software. remote system upgrades this section describes the functionality and implementation of the dedicated remote system upgrade circuitry. it also defines several concepts related to remote system upgrade, including factory configuration, application configuration, remote update mode, and user watchdog timer. additionally, this section provides design guidelines for implementing remote system upgrades with the supported configuration schemes. system designers sometimes face challenges such as shortened design cycles, evolving standards, and system deployments in remote locations. stratix iv devices help overcome these challenges with their inherent reprogrammability and dedicated circuitry to perform remote system upgrades. remote system upgrades help deliver feature enhancements and bug fixes without costly recalls, reduce time-to-market, extend product life, and avoid system downtime. stratix iv devices feature dedicated remote system upgrade circuitry. soft logic (either the nios ? ii embedded processor or user logic) implemented in a stratix iv device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. the dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. remote system upgrade is supported in fast as stratix iv configuration schemes. you can also implement remote system upgrade in conjunction with advanced stratix iv features such as real-time decompression of configuration data and design security using the advanced encryption standard (aes) for secure and efficient field upgrades. the largest serial configuration device currently supports 128 mbits of configuration bitstream. figure 10?20. compressed and uncompressed configuration data in the same configuration file nce gnd nceo decompression controller stratix i v de vice nce nceo n .c. serial configuration data compressed uncompressed configuration data configuration data serial config u ration de vice stratix i v de vice 10?50 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices remote sy s tem upg r ade s stratix iv device handbook volume 1 ? march 2010 altera corporation 1 stratix iv devices only support remote system upgrade in the single device fast as configuration scheme. because the largest serial configuration device currently supports 128 mbits of configuration bitstream, the remote system upgrade feature is not supported in ep4sgx290, ep4se360, and larger devices. 1 the remote system upgrade feature is not supported in a multi-device chain. functional description the dedicated remote system upgrade circuitry in stratix iv devices manages remote configuration and provides error detection, recovery, and status information. user logic or a nios ii processor implemented in the stratix iv device logic array provides access to the remote configuration data source and an interface to the system?s configuration memory. stratix iv devices have remote system upgrade processes that involve the following steps: 1. a nios ii processor (or user logic) implemented in the stratix iv device logic array receives new configuration data from a remote location. the connection to the remote source uses a communication protocol such as the transmission control protocol/internet protocol (tcp/ip), peri pheral component interconnect (pci), user datagram protocol (udp), universal asynchronous receiver/transmitter (uart), or a proprietary interface. 2. the nios ii processor (or user logic) stores this new configuration data in non-volatile configuration memory. 3. the nios ii processor (or user logic) initiates a reconfiguration cycle with the new or updated configuration data. 4. the dedicated remote system upgrade circuitry detects and recovers from any error(s) that might occur during or after the reconfiguration cycle and provides error status information to the user design. figure 10?21 shows the steps required for performing remote configuration updates. (the numbers in figure 10?21 coincide with the steps just mentioned.) figure 10?21. functional diagram of stratix iv remote system upgrade de v elopment location memory stratix i v configu ration stratix i v de vice control module data data data configu ration 1 2 3 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?51 remote sy s tem upg r ade s ? march 2010 altera corporation stratix iv device handbook volume 1 figure 10?22 shows a block diagram for implementing a remote system upgrade with the stratix iv fast as configuration scheme. you must set the mode select pins ( msel[2..0] ) to fast as mode to use remote system upgrade in your system. table 10?13 lists the msel pin settings for stratix iv devices in standard configuration mode and remote system upgrade mode. the following sections describe remote update of the remote system upgrade mode. for more information about standard configuration schemes supported in stratix iv devices, refer to ?configuration schemes? on page 10?2 . 1 when using fast as mode, you must select remote update mode in the quartus ii software and insert the altremote_update megafunction to access the circuitry. for more information, refer to ?altremote_update megafunction? on page 10?61 . enabling remote update you can enable remote update for stratix iv devices in the quartus ii software before design compilation (in the compiler settings menu). in remote update mode, the auto-restart configuration after error option is always enabled. to enable remote update in the project?s compiler settings, perform the following steps in the quartus ii software: 1. on the assignment menu, click device . the settings dialog box appears. 2. click device and pin options . the device and pin options dialog box appears. 3. click the configuration tab. 4. from the configuration scheme list, select active serial (you can also use configuration device ) ( figure 10?23 ). figure 10?22. remote system upgrade block diagram for stratix iv fast as configuration scheme table 10?13. stratix iv remote system upgrade modes configuration scheme msel[2..0] remote system upgrade mode fast as (40 mhz) 011 standard 011 remote update (1) note to table 10?13 : (1) all epcs densities are able to support dclk up to 40 mhz, but batches of epcs1 and epcs4 manufactured on 0.18- m process geometry can only support dclk up to 20 mhz. for more information, refer to the serial configuration devices (e pcs1, epcs4, epcs16, epcs64, and epcs12 8 ) data sheet chapter in volume 2 of the configuration handbook . stratix i v de vice serial configu ration de vice nios ii processor or user logic 10?52 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices remote sy s tem upg r ade s stratix iv device handbook volume 1 ? march 2010 altera corporation 5. from the configuration mode list, select remote ( figure 10?23 ). 6. click ok . 7. in the settings dialog box, click ok . configuration image types when performing a remote system upgrade, stratix iv device configuration bitstreams are classified as factory configuration images or application configuration images. an image, also referred to as a configuration, is a design loaded into the stratix iv device that performs certain user-defined functions. each stratix iv device in your system requires one factory image or the addition of one or more application images. the factory image is a user-defined fall-back, or safe configuration, and is responsible for administering remote updates in conjunction with the dedicated circuitry. application images implement user-defined functionality in the target stratix iv device. you may include the default application image functionality in the factory image. a remote system upgrade involves storing a new application configuration image or updating an existing one using the remote communication interface. after an application configuration image is stored or updated remotely, the user design in the stratix iv device initiates a reconfiguration cycle with the new image. any errors during or after this cycle are detected by the dedicated remote system upgrade figure 10?23. enabling remote update for stratix iv devices in the compiler settings menu chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?53 remote sy s tem upg r ade mode ? march 2010 altera corporation stratix iv device handbook volume 1 circuitry and cause the device to automatically revert to the factory image. the factory image then performs error processing and recovery. the factory configuration is written to the serial configuration device only once by the system manufacturer and must not be remotely updated. on the other hand, application configurations may be remotely updated in the system. both images can initiate system reconfiguration. remote system upgrade mode remote system upgrade has one mode of operation?remote update mode. remote update mode allows you to determine the functionality of your system upon power-up and offers several features. remote update mode in remote update mode, stratix iv devices load the factory configuration image after power up. the user-defined factory configuration determines which application configuration is to be loaded and triggers a reconfiguration cycle. the factory configuration may also contain application logic. when used with serial configuration devices, remote update mode allows an application configuration to start at any flash sector boundary. for example, this translates to a maximum of 128 sectors in the epcs64 device and 32 sectors in the epcs16 device, where the minimum size of each page is 512 kbits. altera recommends not using the same page in the serial configuration devices for two images. additionally, remote update mode features a user watchdog timer that determines the validity of an application configuration. when a stratix iv device is first powered up in remote update mode, it loads the factory configuration located at page zero (page registers pgm[23:0] = 24'b0 ). always store the factory configuration image for your system at page address zero. this corresponds to the start address location 0000000 in the serial configuration device. the factory image is user-designed and contains soft logic to: process any errors based on status information from the dedicated remote system upgrade circuitry communicate with the remote host and receive new application configurations and store this new configuration data in the local non-volatile memory device determine which application configuration is to be loaded into the stratix iv device enable or disable the user watchdog timer and load its time-out value (optional) instruct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle 10?54 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices remote sy s tem upg r ade mode stratix iv device handbook volume 1 ? march 2010 altera corporation figure 10?24 shows the transitions between the factory and application configurations in remote update mode. after power up or a configuration error, the factory configuration logic is loaded automatically. the factory configuration also must specify whether to enable the user watchdog timer for the application configuration and if enabled, to include the timer setting information. the user watchdog timer ensures that the application configuration is valid and functional. the timer must be continually reset within a specific amount of time during user mode operation of an application configuration. only valid application configurations contain the logic to reset the timer in user mode. this timer reset logic must be part of a user-designed hardware and/or software health monitoring signal that indicates error-free system operation. if the timer is not reset in a specific amount of time; for example, the user application configuration detects a functional problem or if the system hangs, the dedicated circuitry updates the remote system upgrade status register, triggering the loading of the factory configuration. 1 the user watchdog timer is automatically disabled for factory configurations. for more information about the user watchdog timer, refer to ?user watchdog timer? on page 10?60 . figure 10?24. transitions between configurations in remote update mode set control register and reconfigure set control register and reconfigure reload a different application application n configuration application 1 configuration factory configuration (page 0) configuration error configuration error power up configuration error reload a different application chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?55 dedi c ated remote sy s tem upg r ade ci rc uit r y ? march 2010 altera corporation stratix iv device handbook volume 1 if there is an error while loading the application configuration, the cause of the reconfiguration is written by the dedicated circuitry to the remote system upgrade status register. actions that cause the remote system upgrade status register to be written are: nstatus driven low externally internal crc error user watchdog timer time-out a configuration reset (logic array nconfig signal or external nconfig pin assertion to low) stratix iv devices automatically load the factory configuration located at page address zero. this user-designed factory configuration can read the remote system upgrade status register to determine the reason for the reconfiguration. the factory configuration then takes appropriate error recovery steps and writes to the remote system upgrade control register to determine the next application configuration to be loaded. when stratix iv devices successfully load the application configuration, they enter into user mode. in user mode, the soft logic (nios ii processor or state machine and the remote communication interface) assists the stratix iv device in determining when a remote system update is arriving. when a remote system update arrives, the soft logic receives the incoming data, writes it to the configuration memory device, and triggers the device to load the factory configuration. the factory configuration reads the remote system upgrade status register and control register, determines the valid application configuration to load, writes the remote system upgrade control register accordingly, and initiates system reconfiguration. dedicated remote system upgrade circuitry this section describes the implementation of the stratix iv remote system upgrade dedicated circuitry. the remote system upgrade circuitry is implemented in hard logic. this dedicated circuitry interfaces to the user-defined factory and application configurations implemented in the stratix iv device logic array to provide the complete remote configuration solution. the remote system upgrade circuitry contains the remote system upgrade registers, a watchdog timer, and a state machine that controls those components. 10?56 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices dedi c ated remote sy s tem upg r ade ci rc uit r y stratix iv device handbook volume 1 ? march 2010 altera corporation figure 10?25 shows the data path for the remote system upgrade block. remote system upgrade registers the remote system upgrade block contains a series of registers that store the page addresses, watchdog timer settings, and status information. table 10?14 lists these registers. figure 10?25. remote system upgrade circuit data path (note 1) note to figure 10?25 : (1) the ru_dout, ru_shiftnld, ru_captnupdt, ru_clk, ru_din, ru_nconfig, and ru_nrstimer signals are internally controlled by the altremote_update megafunction. logic array shift register status register (sr) [4..0] control register [37..0] din capture dout bit [4..0] logic array clko ut ru_shiftnld ru_captnupdt ru_clk ru_di n ru_nco n fig ru_nrstimer user w atchdog timer ru_dout capture clkin update logic array capture din bit [37..0] dout update update register [37..0] time-out rsu state machine internal oscillator table 10?14. remote system upgrade registers (part 1 of 2) register description shift register this register is accessible by the logic array and allows the update, status, and control registers to be written and sampled by user logic. control register this register contains the current page address, user watchdog timer settings, and one bit specifying whether the current configuration is a factory configuration or an application configuration. during a read operation in an application configuration, this register is read into the shift register. when a reconfiguration cycle is initiated, the contents of the update register are written into the control register. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?57 dedi c ated remote sy s tem upg r ade ci rc uit r y ? march 2010 altera corporation stratix iv device handbook volume 1 the remote system upgrade control and status registers are clocked by the 10-mhz internal oscillator (the same oscillator that controls the user watchdog timer). however, the remote system upgrade shift and update registers are clocked by the user clock input ( ru_clk). remote system upgrade control register the remote system upgrade control register stores the application configuration page address and user watchdog timer settings. the control register functionality depends on the remote system upgrade mode selection. in remote update mode, the control register page address bits are set to all zeros ( 24'b0 = 0000000 ) at power up to load the factory configuration. a factory configuration in remote update mode has write access to this register. figure 10?26 and table 10?15 specify the control register bit positions. in the figure, the numbers show the bit position of a setting within a register. for example, bit number 25 is the enable bit for the watchdog timer. the application-not-factory ( anf ) bit indicates whether the current configuration loaded in the stratix iv device is the factory configuration or an application configuration. this bit is set low by the remote system upgrade circuitry when an error condition causes a fall-back to the factory configuration. when the anf bit is high, the control register access is limited to read operations. when the anf bit is low, the register allows write operations and disables the watchdog timer. in remote update mode, the factory configuration design sets this bit high (1'b1) when updating the contents of the update register with the application page address and watchdog timer settings. update register this register contains data similar to that in the control register. however, it can only be updated by the factory configuration by shifting data into the shift register and issuing an update operation. when a reconfiguration cycle is triggered by the factory configuration, the control register is updated with the contents of the update register. during a capture in a factory configuration, this register is read into the shift register. status register this register is written to by the remote system upgrade circuitry on every reconfiguration to record the cause of the reconfiguration. this information is used by the factory configuration to determine the appropriate action following a reconfiguration. during a capture cycle, this register is read into the shift register. table 10?14. remote system upgrade registers (part 2 of 2) register description figure 10?26. remote system upgrade control register wd_timer[11..0] wd_en pgm[23..0] anf 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 .. 3 2 1 0 10?58 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices dedi c ated remote sy s tem upg r ade ci rc uit r y stratix iv device handbook volume 1 ? march 2010 altera corporation table 10?15 lists the remote system upgrade control register contents. remote system upgrade status register the remote system upgrade status register specifies the reconfiguration trigger condition. the various trigger and error conditions include: cyclic redundancy check (crc) error during application configuration nstatus assertion by an external device due to an error stratix iv device logic array triggered a reconfiguration cycle, possibly after downloading a new application configuration image external configuration reset ( nconfig ) assertion user watchdog timer time-out figure 10?27 and table 10?16 specify the contents of the status register. the numbers in the figure show the bit positions within a 5-bit register. table 10?15. remote system upgrade control register contents control register bit remote system upgrade mode value (2) definition anf (1) remote update 1'b0 application not factory pgm[23..0] remote update 24'b0000000 as configuration start address ( stadd[23..0] ) wd_en remote update 1'b0 user watchdog timer enable bit wd_timer[11..0] remote update 12'b000000000000 user watchdog time-out value (most significant 12 bits of 29-bit count value: {wd_timer[11..0], 17'b0} ) notes to table 10?15 : (1) in remote update mode, the remote configuration block does not update the anf bit automatically (you can update it manually). (2) this is the default value of the control register bit. figure 10?27. remote system upgrade status register wd 4 crc 0 nconfig 3 nstatus 1 core_nconfig 2 table 10?16. remote system upgrade status register contents (part 1 of 2) status register bit definition por reset value crc (from the configuration) crc error caused reconfiguration 1 bit '0' nstatus nstatus caused reconfiguration 1 bit '0' core_nconfig (1) device logic array caused reconfiguration 1 bit '0' nconfig nconfig caused reconfiguration 1 bit '0' chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?59 dedi c ated remote sy s tem upg r ade ci rc uit r y ? march 2010 altera corporation stratix iv device handbook volume 1 remote system upgrade state machine the remote system upgrade control and update registers have identical bit definitions, but serve different roles (refer to table 10?14 on page 10?56 ). while both registers can only be updated when the device is loaded with a factory configuration image, the update register writes are controlled by the user logic; the control register writes are controlled by the remote system upgrade state machine. in factory configurations, the user logic sends the anf bit (set high), the page address, and the watchdog timer settings for the next application configuration bit to the update register. when the logic array configuration reset ( ru_nconfig ) goes low, the remote system upgrade state machine updates the control register with the contents of the update register and initiates system reconfiguration from the new application page. 1 to ensure successful reconfiguration between the pages, assert the ru_nconfig signal for a minimum of 250 ns. this is equivalent to strobing the reconfiguration input of the altremote_update megafunction high for a minimum of 250 ns. in the event of an error or reconfiguration trigger condition, the remote system upgrade state machine directs the system to load a factory or application configuration (page zero or page one, based on the mode and error condition) by setting the control register accordingly. table 10?17 lists the contents of the control register after such an event occurs for all possible error or trigger conditions. the remote system upgrade status register is updated by the dedicated error monitoring circuitry after an error condition but before the factory configuration is loaded. capture operations during factory configuration access the contents of the update register. this feature is used by the user logic to verify that the page address and watchdog timer settings were written correctly. read operations in application configurations access the contents of the control register. this information is used by the user logic in the application configuration. wd watchdog timer caused reconfiguration 1 bit '0' note to table 10?16 : (1) logic array reconfiguration forces the system to load the application configuration data into the stratix iv device. this oc curs after the factory configuration specifies the appropriate application configuration page address by updating the update register. table 10?16. remote system upgrade status register contents (part 2 of 2) status register bit definition por reset value table 10?17. control register contents after an error or reconfiguration trigger condition reconfiguration error/trigger control register setting remote update nconfig reset all bits are 0 nstatus error all bits are 0 core triggered reconfiguration update register crc error all bits are 0 wd time out all bits are 0 10?60 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices dedi c ated remote sy s tem upg r ade ci rc uit r y stratix iv device handbook volume 1 ? march 2010 altera corporation user watchdog timer the user watchdog timer prevents a faulty application configuration from stalling the device indefinitely. the system uses the timer to detect functional errors after an application configuration is successfully loaded into the stratix iv device. the user watchdog timer is a counter that counts down from the initial value loaded into the remote system upgrade control register by the factory configuration. the counter is 29 bits wide and has a maximum count value of 2 29 . when specifying the user watchdog timer value, specify only the most significant 12 bits. the granularity of the timer setting is 2 15 cycles. the cycle time is based on the frequency of the 10-mhz internal oscillator. table 10?18 lists the operating range of the 10-mhz internal oscillator. the user watchdog timer begins counting once the application configuration enters device user mode. this timer must be periodically reloaded or reset by the application configuration before the timer expires by asserting ru_nrstimer . if the application configuration does not reload the user watchdog timer before the count expires, a time-out signal is generated by the remote system upgrade dedicated circuitry. the time-out signal tells the remote system upgrade circuitry to set the user watchdog timer status bit ( wd ) in the remote system upgrade status register and reconfigures the device by loading the factory configuration. 1 to allow remote system upgrade dedicated circuitry to reset the watchdog timer, you must assert the ru_nrstimer signal active for a minimum of 250 ns. this is equivalent to strobing the reset_timer input of the altremote_update megafunction high for a minimum of 250 ns. the user watchdog timer is not enabled during the configuration cycle of the device. errors during configuration are detected by the crc engine. also, the timer is disabled for factory configurations. functional errors should not exist in the factory configuration because it is stored and validated during production and is never updated remotely. 1 the user watchdog timer is disabled in factory configurations and during the configuration cycle of the application configuration. it is enabled after the application configuration enters user mode. table 10?18. 10-mhz internal oscillator specifications (note 1) minimum typical maximum units 4.3 5.3 10 mhz note to table 10?18 : (1) these values are preliminary. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?61 qua r tu s ii softwa r e suppo r t ? march 2010 altera corporation stratix iv device handbook volume 1 quartus ii software support the quartus ii software provides the flexibility to include the remote system upgrade interface between the stratix iv device logic array and the dedicated circuitry, generate configuration files for production, and allows remote programming of the system configuration memory. the altremote_update megafunction is the implementation option in the quartus ii software that you use for the interface between the remote system upgrade circuitry and the device logic array interface. using the megafunction block instead of creating your own logic saves design time and offers more efficient logic synthesis and device implementation. altremote_update megafunction the altremote_update megafunction provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the stratix iv device logic. this implementation is suitable for designs that implement the factory configuration functions using a nios ii processor or user logic in the device. figure 10?28 shows the interface signals between the altremote_update megafunction and nios ii processor or user logic. f for more information about the altremote_update megafunction and the description of ports listed in figure 10?28 , refer to the remote update circuitry (altremote_update) megafunction user guide . figure 10?28. interface signals between the altremote_update megafunction and the nios ii processor nios ii processor or user logic read_param write_param param[2..0] data_in[23..0] reconfig reset_timer clock reset busy data_out[23..0] altremote_update 10?62 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices de s ign se c u r ity stratix iv device handbook volume 1 ? march 2010 altera corporation design security this section provides an overview of the design security feature and its implementation on stratix iv devices using the advanced encryption standard (aes). it also covers the new security modes available in stratix iv devices. as stratix iv devices continue play a role in larger and more critical designs in competitive commercial and military environments, it is increasingly important to protect the designs from copying, reverse engineering, and tampering. stratix iv devices address these concerns with both volatile and non-volatile security feature support. stratix iv devices have the ability to decrypt configuration bitstreams using the aes algorithm, an industry-standard encryption algorithm that is fips-197 certified. stratix iv devices have a design security feature that utilizes a 256-bit security key. stratix iv devices store configuration data in sram configuration cells during device operation. because sram is volatile, the sram cells must be loaded with configuration data each time the device powers up. it is possible to intercept configuration data when it is being transmitted from the memory source (flash memory or a configuration device) to the device. the intercepted configuration data could then be used to configure another device. when using the stratix iv design security feature, the security key is stored in the stratix iv device. depending on the security mode, you can configure the stratix iv device using a configuration file that is encrypted with the same key, or for board testing, configured with a normal configuration file. the design security feature is available when configuring stratix iv devices using fpp configuration mode with an external host (such as a max ii device or microprocessor), or when using fast as or ps configuration schemes. the design security feature is also available in remote update with fast as configuration mode. the design security feature is not available when you are configuring your stratix iv device using jtag-based configuration. for more information, refer to ?supported configuration schemes? on page 10?66 . 1 when using a serial configuration scheme such as ps or fast as, configuration time is the same whether or not you enable the design security feature. if the fpp scheme is used with the design security or decompression feature, a 4 dclk is required. this results in a slower configuration time when compared with the configuration time of a stratix iv device that has neither the design security nor the decompression feature enabled. stratix iv security protection stratix iv device designs are protected from copying, reverse engineering, and tampering using configuration bitstream encryption. security against copying the security key is securely stored in the stratix iv device and cannot be read out through any interfaces. in addition, as configuration file read-back is not supported in stratix iv devices, the design information cannot be copied. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?63 de s ign se c u r ity ? march 2010 altera corporation stratix iv device handbook volume 1 security against reverse engineering reverse engineering from an encrypted configuration file is very difficult and time consuming because the stratix iv configuration file formats are proprietary and the file contains millions of bits which require specific decryption. reverse engineering the stratix iv device is just as difficult because the device is manufactured on the most advanced 40-nm process technology. security against tampering the non-volatile keys are one-time programmable. after the tamper protection bit is set in the key programming file generated by the quartus ii software, the stratix iv device can only be configured with configuration files encrypted with the same key. aes decryption block the main purpose of the aes decryption block is to decrypt the configuration bitstream prior to entering data decompression or configuration. prior to receiving encrypted data, you must enter and store the 256-bit security key in the device. you can choose between a non-volatile security key and a volatile security key with battery backup. the security key is scrambled prior to storing it in the key storage to make it more difficult for anyone to retrieve the stored key using de-capsulation of the device. flexible security key storage stratix iv devices support two types of security key programming?volatile and non-volatile keys. table 10?19 lists the differences between volatile keys and non-volatile keys. you can program the non-volatile key to the stratix iv device without an external battery. also, there are no additional requirements to any of the stratix iv power supply inputs. v ccbat is a dedicated power supply for volatile key storage and not shared with other on-chip power supplies, such as v ccio or v cc . v ccbat continuously supplies power to the volatile register regardless of the on-chip supply condition. table 10?19. security key options options volatile key non-volatile key key programmability reprogrammable and erasable one-time programmable external battery required not required key programming method (1) on-board on and off board design protection secure against copying and reverse engineering secure against copying and reverse engineering. tamper resistant if tamper protection bit is set. note to table 10?19 : (1) key programming is carried out using the jtag interface. 10?64 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices de s ign se c u r ity stratix iv device handbook volume 1 ? march 2010 altera corporation 1 after power-up, you must wait 300 ms ( porsel = 0) or 12 ms ( porsel = 1) before beginning key programming to ensure that v ccbat is at full rail. 1 for more information about how to calculate the key retention time of the battery used for volatile key storage, refer to the stratix iv powerplay early power estimator . f for more information about battery specifications, refer to the dc and switching characteristics chapter. f for more information about the v ccbat pin connection recommendations, refer to the stratix iv gx device family pin connection guidelines . stratix iv design security solution stratix iv devices are sram-based devices. to provide design security, stratix iv devices require a 256-bit security key for configuration bitstream encryption. you can carry out secure configuration in the following steps, as shown in figure 10?29 : 1. program the security key into the stratix iv device. 2. program the user-defined 256-bit aes keys to the stratix iv device through the jtag interface. 3. encrypt the configuration file and store it in the external memory. 4. encrypt the configuration file with the same 256-bit keys used to program the stratix iv device. encryption of the configuration file is done using the quartus ii software. the encrypted configuration file is then loaded into the external memory, such as a configuration or flash device. 5. configure the stratix iv device. at system power-up, the external memory device sends the encrypted configuration file to the stratix iv device. chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?65 de s ign se c u r ity ? march 2010 altera corporation stratix iv device handbook volume 1 security modes available the following security modes are available on the stratix iv device: volatile key secure operation with volatile key programmed and required external battery: this mode accepts both encrypted and unencrypted configuration bitstreams. use the unencrypted configuration bitstream support for board-level testing only. non-volatile key secure operation with one time programmable (otp) security key programmed: this mode accepts both encrypted and unencrypted configuration bitstreams. use the unencrypted configuration bitstream support for board level testing only. non-volatile key with tamper protection bit set secure operation in tamper resistant mode with otp security key programmed: only encrypted configuration bitstreams are allowed to configure the device. tamper protection disables jtag configuration with unencrypted configuration bitstream. 1 enabling the tamper protection bit disables test mode in stratix iv devices. this process is irreversible and prevents altera from conducting carry-out failure analysis if test mode is disabled. contact altera technical support to enable the tamper protection bit. figure 10?29. design security (note 1) note to figure 10?29 : (1) step 1, step 2, and step 3 correspond to the procedure described in ?design security? on page 10?62 . user-defined aes key key storage encrypted configuration file memory or configuration device stratix iv device aes decryption step 1 step 2 step 3 10?66 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices de s ign se c u r ity stratix iv device handbook volume 1 ? march 2010 altera corporation no key operation only unencrypted configuration bitstreams are allowed to configure the device. table 10?20 lists the different security modes and configuration bitstream supported for each mode. supported configuration schemes the stratix iv device supports only selected configuration schemes, depending on the security mode you select when you encrypt the stratix iv device. figure 10?30 shows the restrictions of each security mode when encrypting stratix iv devices. table 10?21 lists the configuration modes allowed in each of the security modes. table 10?20. security modes supported mode (1) function configuration file volatile key secure encrypted board-level testing unencrypted non-volatile key secure encrypted board-level testing unencrypted non-volatile key with tamper protection bit set secure (tamper resistant) (2) encrypted notes to table 10?20 : (1) in no key operation, only the unencrypt ed configuration file is supported. (2) the tamper protection bit setting does not prevent the device from being reconfigured. figure 10?30. stratix iv security modes?sequence and restrictions volatile key unencrypted or encrypted configuration file no key unencrypted configuration file non-volatile key unencrypted or encrypted configuration file non-volatile key with tamper-protection bit set encrypted configuration file chapter 10: configuration, design security, and remote system upgrades in stratix iv devices 10?67 do c ument revi s ion hi s to r y ? march 2010 altera corporation stratix iv device handbook volume 1 you can use the design security feature with other configuration features, such as compression and remote system upgrade features. when you use compression with the design security feature, the configuration file is first compressed and then encrypted using the quartus ii software. during configuration, the stratix iv device first decrypts and then decompresses the configuration file. document revision history table 10?22 shows the revision history for this chapter. table 10?21. allowed configuration modes for various security modes (note 1) security mode configuration file allowed configuration modes no key unencrypted all configuration modes that do not engage the design security feature. secure with volatile key encrypted passive serial with aes (and/or with decompression) fast passive parallel with aes (and/or with decompression) remote update fast as with aes (and/or with decompression) fast as (and/or with decompression) board-level testing with volatile key unencrypted all configuration modes that do not engage the design security feature. secure with non-volatile key encrypted passive serial with aes (and/or with decompression) fast passive parallel with aes (and/or with decompression) remote update fast as with aes (and/or with decompression) fast as (and/or with decompression) board-level testing with non-volatile key unencrypted all configuration modes that do not engage the design security feature. secure in tamper resistant mode using non-volatile key with tamper protection set encrypted passive serial with aes (and/or with decompression) fast passive parallel with aes (and/or with decompression) remote update fast as with aes (and/or with decompression) fast as (and/or with decompression) note to table 10?21 : (1) there is no impact to the configuration time required when compared with unencrypted configuration modes except fpp with aes (and/or decompression), which requires a dclk that is 4 the data rate. 10?68 chapter 10: configuration, design security, and remote system upgrades in stratix iv devices do c ument revi s ion hi s to r y stratix iv device handbook volume 1 ? march 2010 altera corporation table 10?22. document revision history date and document version changes made summary of changes march 2010 v3.1 added the ?guidelines for connecting serial configuration devices on an as interface? section. updated the ?power-on reset circuit? and ?fast active serial configuration (serial configuration devices)? sections. updated table 10?2 , tab le 1 0? 4 , tab le 1 0? 5 , table 10?10 , and table 10?13 . updated figure 10?16 and figure 10?17 with note 5. updated figure 10?4 , figure 10?5 , and figure 10?13 . updated the reference in the ?configuration schemes? section. ? november 2009 v3.0 updated table 10?1 and table 10?2. updated the ?fpp configuration using a max ii device as an external host?,?fast active serial configuration (serial configuration devices)?, ?device configuration pins?, ?remote system upgrades?, ?remote system upgrade mode?, ?estimating active serial configuration time?, ?remote system upgrade state machine?, and ?user watchdog timer? sections. removed table 10-4, table 10-7, table 10-8, and table 10-25. minor text edits. ? june 2009 v2.3 updated the ?vccpd pins?, ?fpp configuration using a max ii device as an external host?, ?estimating active serial configuration time?, ?fast active serial configuration (serial configuration devices)?, ?remote system upgrades?, ?ps configuration using a max ii device as an external host?, and ?ps configuration using a download cable? sections. updated table 10?3, table 10?13 and table 10?2. added introductory sentences to improve search ability. removed the conclusion section. minor text edits. ? april 2009 v2.2 updated table 10?2. ? march 2009 v2.1 updated table 10?1, table 10?2, and table 10?9. removed ?referenced documents? section. ? november 2008 v2.0 updated ?fast active serial configuration (serial configuration devices)? and ?jtag configuration? sections. updated figure 10?4, figure 10?5, figure 10?6, and figure 10?13. updated table 10?2 and table 10?13. medium update. may 2008 v1.0 initial release. ? ? march 2010 altera corporation stratix iv device handbook volume 1 11. seu mitigation in stratix iv devices this chapter describes how to use the error detection cyclical redundancy check (crc) feature when a stratix ? iv device is in user mode and recovers from crc errors. the purpose of the error detection crc feature in the stratix iv device is to detect a flip in any of the configuration random access memory (cram) bits in stratix iv devices due to a soft error. with the error detection circuitry, you can continuously verify the integrity of the configuration cram bits. in critical applications such as avionics, telecommunications, system control, and military applications, it is important to be able to do the following: confirm that the configuration data stored in a stratix iv device is correct alert the system to the occurrence of a configuration error 1 the error detection feature is enhanced in the stratix iv device family. similar to stratix iii devices, the error detection and recovery time for single-event upset (seu) in stratix iv devices is reduced when compared with stratix ii devices. f for more information about test methodology for enhanced error detection in stratix iv devices, refer to an 539: test methodology of error detection and recovery using crc in altera fpga devices . dedicated circuitry is built into stratix iv devices and consists of a crc error detection feature that optionally checks for seus continuously and automatically. 1 for stratix iv devices, the error detection crc feature is provided in the quartus ? ii software version 8.0 and onwards. using error detection crc for the stratix iv device family has no impact on fitting or performance of your device. this chapter contains the following sections: ?error detection fundamentals? on page 11?2 ?configuration error detection? on page 11?2 ?user mode error detection? on page 11?2 ?error detection pin description? on page 11?5 ?error detection block? on page 11?6 ?error detection timing? on page 11?8 ?recovering from crc errors? on page 11?11 siv51011-3.1 11?2 chapter 11: seu mitigation in stratix iv devices error detection fundamentals stratix iv device handbook volume 1 ? march 2010 altera corporation error detection fundamentals error detection determines whether the data received is corrupted during transmission. to accomplish this, the transmitter uses a function to calculate a checksum value for the data and appends the checksum to the original data frame. the receiver uses the same calculation methodology to generate a checksum for the received data frame and compares the received checksum to the transmitted checksum. if the two checksum values are equal, the received data frame is correct and no data corruption occurred during transmission or storage. the error detection crc feature uses the same concept. when stratix iv devices are configured successfully and are in user mode, the error detection crc feature ensures the integrity of the configuration data. 1 there are two crc error checks. one crc error check always runs during configuration and a second optional crc error check runs in the background in user mode. both crc error checks use the same crc polynomial but different error detection implementations. for more information, refer to ?configuration error detection? and ?user mode error detection? . configuration error detection in configuration mode, a frame-based crc is stored within the configuration data and contains the crc value for each data frame. during configuration, the stratix iv device calculates the crc value based on the frame of data that is received and compares it against the frame crc value in the data stream. configuration continues until either the device detects an error or configuration is completed. in stratix iv devices, the crc value is calculated during the configuration stage. a parallel crc engine generates 16 crc check bits per frame and then stores them in cram. the cram chain used for storing the crc check bits is 16 bits wide and its length is equal to the number of frames in the device. user mode error detection stratix iv devices have built-in error detection circuitry to detect data corruption by soft errors in the cram cells. this feature allows all cram contents to be read and verified to match a configuration-computed crc value. soft errors are changes in a cram bit state due to an ionizing particle. the error detection capability continuously computes the crc of the configured cram bits and compares it with the pre-calculated crc. if the crcs match, there is no error in the current configuration cram bits. the process of error detection continues until the device is reset (by setting nconfig low). if you enable the crc error detection option in the quartus ii software, after the device transitions into user mode, the error detection process is enabled. the internal 100 mhz configuration oscillator is divided down by a factor of two to 256 (at powers of two) to be used as the clock source during the error detection process. you must set the clock divide factor in the quartus ii software. chapter 11: seu mitigation in stratix iv devices 11?3 user mode error detection ? march 2010 altera corporation stratix iv device handbook volume 1 a single 16-bit crc calculation is done on a per-frame basis. after it has finished the crc calculation for a frame, the resulting 16-bit signature is hex 0000 if there are no cram bit errors detected in a frame by the error detection circuitry and the output signal crc_error is 0 . if a cram bit error is detected by the circuitry within a frame in the device, the resulting signature is non-zero. this causes the crc engine to start searching for the error bit location. error detection in stratix iv devices calculates crc check bits for each frame and pulls the crc_error pin high when it detects bit errors in the chip. within a frame, it can detect all single-bit, double-bit, and three-bit errors. the probability of more than three cram bits being flipped by an seu event is very low. in general, for all error patterns the probability of detection is 99.998%. the crc engine reports the bit location and determines the type of error for all single-bit errors and over 99.641% of double -adjacent errors. the probability of other error patterns is very low and report of the location of bit flips is not guaranteed by the crc engine. you can also read-out the error bit location through the jtag and the core interface. shift these bits out through either the shift_ederror_reg jtag instruction or the core interface before the crc detects the next error in another frame. if the next frame also has an error, you must shift these bits out within the amount of time of one frame crc verification. you can choose to extend this time interval by slowing down the error detection clock frequency, but this slows down the error recovery time for the seu event. for the minimum update interval for stratix iv devices, refer to table 11?6 on page 11?9 . if these bits are not shifted out before the next error location is found, the previous error location and error message is overwritten by the new information. the crc circuit continues to run, and if an error is detected, you must decide whether to complete a reconfiguration or to ignore the crc error. the error detection logic continues to calculate the crc_error and 16-bit signatures for the next frame of data regardless if any error has occurred in the current frame or not. you need to monitor these signals and take the appropriate actions if a soft error occurs. the error detection circuitry in stratix iv devices uses a 16-bit crc-ansi standard (16-bit polynomial) as the crc generator. the computed 16-bit crc signature for each frame is stored in the registers within the core. the total storage register size is 16 (the number of bits per frame) the number of frames. the stratix iv device error detection feature does not check memory blocks and i/o buffers. thus, the crc_error signal might stay solid high or low depending on the error status of the previously checked cram frame. the i/o buffers are not verified during error detection because these bits use flipflops as storage elements that are more resistant to soft errors when compared with cram cells. the support parity bits of mlab, m9k, and m144k are used to check the contents of the memory blocks for any errors. the m144k trimatrix memory block has a built-in error correction code block that checks and corrects the errors in the block. f for more information, refer to the trimatrix embedded memory blocks in stratix iv devices chapter . 11?4 chapter 11: seu mitigation in stratix iv devices user mode error detection stratix iv device handbook volume 1 ? march 2010 altera corporation a jtag instruction, ederror_inject , is provided to test the capability of the error detection block. this instruction is able to change the content of the 21-bit jtag fault injection register that is used for error injection in stratix iv devices, enabling the testing of the error detection block. 1 you can only execute the ederror_inject jtag instruction when the device is in user mode. table 11?1 lists the description of the ederror_inject jtag instruction. you can create a jam? file ( .jam ) to automate the testing and verification process. this allows you to verify the crc functionality in-system, on-the-fly, without having to reconfigure the device. you can then switch to the crc circuit to check for real errors induced by an seu. you can introduce a single-error or double-errors adjacent to each other to the configuration memory. this provides an extra way to facilitate design verification and system fault tolerance characterization. use the jtag fault injection register with the ederror_inject instruction to flip the readback bits. the stratix iv device is then forced into error test mode. the content of the jtag fault injection register is not loaded into the fault injection register during the processing of the last and first frame. it is only loaded at the end of this period. 1 you can only introduce error injection in the first data frame, but you can monitor the error information at any time. for more information about the jtag fault injection register and fault injection register, refer to ?error detection registers? on page 11?6 . table 11?2 lists how the fault injection register is implemented and describes error injection. table 11?1. ederror_inject jtag instruction jtag instruction instruction code description ederror_inject 00 0001 0101 this instruction controls the 21-bit jtag fault injection register, which is used for error injection. table 11?2. fault injection register bit bit[20..19] bit[18..8] bit[7..0] description error type byte location of the injected error error byte value content error type (1) error injection type depicts the location of the injected error in the first data frame. depicts the location of the bit error and corresponds to the error injection type selection. bit[20] bit[19] 01 single-byte error injection 10 double-adjacent byte error injection 00 no error injection note to tab l e 1 1? 2 : (1) bit[20] a nd bit[19] cannot both be set to 1 as this is not a valid selection. the error detection circuitry decodes this as no error injection. chapter 11: seu mitigation in stratix iv devices 11?5 error detection pin description ? march 2010 altera corporation stratix iv device handbook volume 1 1 after the test completes, altera recommends that you reconfigure the device. automated single-event upset detection stratix iv devices offer on-chip circuitry for automated checking of seu detection. some applications that require the device to operate error-free in high-neutron flux environments require periodic checks to ensure continued data integrity. the error detection crc feature ensures data reliability and is one of the best options for mitigating seu. you can implement the error detection crc feature with existing circuitry in stratix iv devices, eliminating the need for external logic. the crc_error pin reports a soft error when the configuration cram data is corrupted. you must decide whether to reconfigure the device or to ignore the error. error detection pin description depending on the type of error detection feature you choose, you must use different error detection pins to monitor the data during user mode. crc_error pin table 11?3 describes the crc_error pin. 1 the wysiwyg function performs optimization on the verilog quartus mapping (vqm) netlist within the quartus ii software. f for more information about the stratixiv_crcblock wysiwyg function, refer to the an 539: test methodology of error detection and recovery using crc in altera fpga devices . f for more information about the crc_error pin for stratix iv devices, refer to device pin-outs on the altera website. table 11?3. crc_error pin description pin name pin type description crc_error i/o and open-drain active-high signal indicates that the error detection circuit has detected errors in the configuration cram bits. this pin is optional and is used when the error detection crc circuit is enabled. when the error detection crc circuit is disabled, it is a user i/o pin. to u se th e crc_error pin, you can either tie this pin to v ccpgm through a 10k resistor or, depending on the input voltage specification of the system receiving the signal, you can tie this pin to a different pull-up voltage. 11?6 chapter 11: seu mitigation in stratix iv devices error detection block stratix iv device handbook volume 1 ? march 2010 altera corporation error detection block you can enable the stratix iv device error detection block in the quartus ii software (refer to ?software support? on page 11?10 ). this block contains the logic necessary to calculate the 16-bit crc signature for the configuration cram bits in the device. the crc circuit continues running even if an error occurs. when a soft error occurs, the device sets the crc_error pin high. two types of crc detection checks the configuration bits: cram error checking ability (16-bit crc), which occurs during user mode to be used by the crc_error pin. for each frame of data, the pre-calculated 16-bit crc enters the crc circuit at the end of the frame data and determines whether there is an error or not. if an error occurs, the search engine starts to find the location of the error. the error messages are shifted out through the jtag instruction or core interface logics while the error detection block continues running. the jtag interface reads out the 16-bit crc result for the first frame and also shifts the 16-bit crc bits to the 16-bit crc storage registers for test purposes. single error, double errors, or double-errors adjacent to each other are deliberately introduced to configuration memory for testing and design verification. 16-bit crc that is embedded in every configuration data frame. during configuration, after a frame of data is loaded into the stratix iv device, the pre-computed crc is shifted into the crc circuitry. at the same time, the crc value for the data frame shifted-in is calculated. if the pre-computed crc and calculated crc values do not match, nstatus is set low. every data frame has a 16-bit crc; therefore, there are many 16-bit crc values for the whole configuration bitstream. every device has different lengths of configuration data frame. 1 the ?error detection block? section describes the 16-bit crc only when the device is in user mode. error detection registers there is one set of 16-bit registers in the error detection circuitry that stores the computed crc signature. a non-zero value on the syndrome register causes the crc_error pin to be set high. chapter 11: seu mitigation in stratix iv devices 11?7 error detection block ? march 2010 altera corporation stratix iv device handbook volume 1 figure 11?1 shows the error detection circuitry, syndrome registers, and error injection block. table 11?4 defines the registers shown in figure 11?1 . figure 11?1. error detection block diagram error detection state machine fault injection register jtag fault injection register error injection block control signals 16-bit crc calculation and error search engine readback bit stream with expected crc included syndrome register 8 16 crc_error jtag update register user update register error message register 46 30 jtag shift register user shift register general routing jtag tdo table 11?4. error detection registers (part 1 of 2) register description syndrome register this register contains the crc signature of the current frame through the error detection verification cycle. the crc_error signal is derived from the contents of this register. error message register this 46-bit register contains information on the error type, location of the error, and the actual syndrome. the types of errors and location reported are single- and double-adjacent bit errors. the location bits for other types of errors are not identified by the error message register. the content of the register can be shifted out through the shift_ederror_reg jtag instruction or to the core through the core interface. jtag update register this register is automatically updated with the contents of the error message register one cycle after the 46-bit register content is validated. it includes a clock enable that must be asserted prior to being sampled into the jtag shift register. this requirement ensures that the jtag update register is not being written into by the contents of the error message register at the same time that the jtag shift register is reading its contents. 11?8 chapter 11: seu mitigation in stratix iv devices error detection timing stratix iv device handbook volume 1 ? march 2010 altera corporation error detection timing when you enable the crc feature through the quartus ii software, the device automatically activates the crc process upon entering user mode, after configuration, and after initialization is complete. if an error is detected within a frame, crc_error is driven high at the end of the error location search, after the error message register is updated. at the end of this cycle, the crc_error pin is pulled low for a minimum of 32 clock cycles. if the next frame contains an error, the crc_error is driven high again after the error message register is overwritten by the new value. you can start to unload the error message on each rising edge of the crc_error pin. the error detection runs until the device is reset. the error detection circuitry runs off an internal configuration oscillator with a divisor that sets the maximum frequency. table 11?5 lists the minimum and maximum error detection frequencies based on the best performance of the internal configuration oscillator. you can set a lower clock frequency by specifying a division factor in the quartus ii software (refer to ?software support? on page 11?10 ). the divisor is a power of two, in which n is between 1 and 8. the divisor ranges from 2 through 256. refer to equation 11?1 . user update register this register is automatically updated with the contents of the error message register, one cycle after the 46-bit register content is validated. it includes a clock enable that must be asserted prior to being sampled into the user shift register. this requirement ensures that the user update register is not being written into by the contents of the error message register at exactly the same time that the user shift register is reading its contents. jtag shift register this register is accessible by the jtag interface and allows the contents of the jtag update register to be sampled and read by the jtag instruction shift_ederror_reg . user shift register this register is accessible by the core logic and allows the contents of the user update register to be sampled and read by user logic. jtag fault injection register this 21-bit register is fully controlled by the jtag instruction ederror_inject . this register holds the information of the error injection that you want in the bitstream. fault injection register the content of the jtag fault injection register is loaded into this 21-bit register when it is being updated. table 11?4. error detection registers (part 2 of 2) register description table 11?5. minimum and maximum error detection frequencies device type error detection frequency maximum error detection frequency minimum error detection frequency valid divisors (n) stratix iv 100 mhz / 2 n 50 mhz 390 khz 1, 2, 3, 4, 5, 6, 7, 8 equation 11?1. error detection frequency 100 mhz 2 n ------------------- - = chapter 11: seu mitigation in stratix iv devices 11?9 error detection timing ? march 2010 altera corporation stratix iv device handbook volume 1 1 the error detection frequency reflects the frequency of the error detection process for a frame because the crc calculation in the stratix iv device is done on a per-frame basis. you must monitor the error message to avoid missing information in the error message register. the error message register is updated whenever an error occurs. the minimum interval time between each update for the error message register depends on the device and the error detection clock frequency. table 11?6 lists the estimated minimum interval time between each update for the error message register for stratix iv devices. crc calculation time for the error detection circuitry to check from the first until the last frame depends on the device and the error detection clock frequency. table 11?7 lists the estimated time for each crc calculation with minimum and maximum clock frequencies for stratix iv devices. the minimum crc calculation time is calculated by using the maximum error detection frequency with a divisor factor of one, and the maximum crc calculation time is calculated by using the minimum error detection frequency with a divisor factor of eight. table 11?6. minimum update interval for error message register (note 1) device timing interval ( s) ep4sgx70 13.8 ep4sgx110 13.8 ep4sgx180 19.8 ep4sgx230 19.8 ep4sgx290 21.8 ep4sgx360 21.8 ep4sgx530 26.8 ep4se230 19.8 ep4se360 21.8 ep4se530 26.8 ep4se820 33.8 ep4s40g2 19.8 ep4s40g5 26.8 ep4s100g2 19.8 ep4s100g3 26.8 ep4s100g4 26.8 ep4s100g5 26.8 note to tab l e 1 1? 6 : (1) these timing numbers are preliminary. 11?10 chapter 11: seu mitigation in stratix iv devices error detection timing stratix iv device handbook volume 1 ? march 2010 altera corporation software support the quartus ii software version 8.0 and onwards supports the error detection crc feature for stratix iv devices. enabling this feature generates the crc_error output to the optional dual purpose crc_error pin. the error detection crc feature is controlled by the device and pin options dialog box in the quartus ii software. to enable the error detection feature using crc, perform the following steps: 1. open the quartus ii software and load a project using a stratix iv device. 2. on the assignments menu, click settings . the settings dialog box is shown. 3. in the category list, select device . the device page is shown. 4. click device and pin options . the device and pin options dialog box is shown (refer to figure 11?2 ). 5. in the device and pin options dialog box, click the error detection crc tab. 6. turn on enable error detection crc ( figure 11?2 ). table 11?7. crc calculation time (note 1) device minimum time (ms) maximum time (s) ep4sgx70 111 30.90 ep4sgx110 111 30.90 ep4sgx180 225 62.44 ep4sgx230 225 62.44 ep4sgx290 296 82.05 ep4sgx360 296 82.05 ep4sgx530 398 110.38 ep4se230 225 62.44 ep4se360 296 82.05 ep4se530 398 110.38 ep4se820 577 160.00 ep4s40g2 225 62.44 ep4s40g5 398 110.38 ep4s100g2 225 62.44 ep4s100g3 398 110.38 ep4s100g4 398 110.38 ep4s100g5 398 110.38 note to tab l e 1 1? 7 : (1) these timing numbers are preliminary. chapter 11: seu mitigation in stratix iv devices 11?11 recovering from crc errors ? march 2010 altera corporation stratix iv device handbook volume 1 7. in the divide error check frequency by pull-down list, enter a valid divisor as listed in table 11?5 on page 11?8 . 1 the divide value divides the frequency of the configuration oscillator output clock that clocks the crc circuitry. 8. click ok . recovering from crc errors the system that the stratix iv device resides in must control the device reconfiguration. after detecting an error on the crc_error pin, strobing the nconfig signal low directs the system to perform the reconfiguration at a time when it is safe for the system to reconfigure the device. when the data bit is rewritten with the correct value by reconfiguring the device, the device functions correctly. while soft errors are uncommon in altera devices, certain high-reliability applications require a design to account for these errors. figure 11?2. enabling the error detection crc feature in the quartus ii software 11?12 chapter 11: seu mitigation in stratix iv devices document revision history stratix iv device handbook volume 1 ? march 2010 altera corporation document revision history table 11?8 lists the revision history for this chapter. table 11?8. document revision history date and document version changes made summary of changes march 2010 v3.1 updated table 11?3 and ta bl e 11 ?6 . minor text edits. ? november 2009 v3.0 updated table 11?3, table 11?5, table 11?6, and table 11?7. updated the ?crc_error pin? section. minor text edits. ? june 2009 v2.3 added an introductory paragraph to increase search ability. removed the conclusion section. minor text edits. ? april 2009 v2.2 updated table 11?6 and table 11?7. ? march 2009 v2.1 updated ?error detection timing? section. updated table 11?6. added table 11?7. removed ?critical error detection?, ?critical error pin?, and ?referenced documents? sections. ? november 2008 v2.0 minor text edits. ? may 2008 | v1.0 initial release. ? ? march 2010 altera corporation stratix iv device handbook volume 1 12. jtag boundary-scan testing in stratix iv devices the ieee std. 1149.1 boundary-scan test (bst) circuitry available in stratix ? iv devices provides a cost-effective and efficient way to test systems that contain devices with tight lead spacing. circuit boards with altera and other ieee std. 1149.1-compliant devices can use extest , sample/preload , and bypass modes to create serial patterns that internally test the pin connections between devices and check device operation. this chapter describes how to use the ieee std. 1 149.1 bst circuitry in stratix iv devices. the features are similar to stratix iii devices, unless stated otherwise in this document. this chapter contains the following sections: ?bst architecture? on page 12?1 ?bst operation control? on page 12?1 ?i/o voltage support in a jtag chain? on page 12?3 ?bst circuitry? on page 12?3 ?bsdl support? on page 12?4 bst architecture a device operating in ieee std. 1149.1 bst mode uses four required pins, tdi, tdo, tms, tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi, tms , and trst pins have internal weak pull-up resistors. the tdo output pin and all the jtag input pins are powered by the 2.5-v/3.0-v v ccpd supply of i/o bank 1a. all user i/o pins are tri-stated during jtag configuration. f for more information about the description and functionality of all jtag pins, registers used by the ieee std. 1 149.1 bst circuitry, and the test access port (tap) controller, refer to the ieee 1 149.1 (jtag) boundary-scan testing in stratix iii devices chapter in volume 1 of the stratix iii device handbook . bst operation control table 12?1 lists the boundary-scan register length for stratix iv devices. table 12?1. stratix iv devices boundary-scan register length (part 1 of 2) device boundary-scan register length ep4sgx70 1506 ep4sgx110 1506 ep4sgx180 2274 ep4sgx230 2274 ep4sgx290 (1) 2682 ep4sgx360 (1) 2682 siv51012-3.1 12?2 chapter 12: jtag boundary-scan testing in stratix iv devices bst operation control stratix iv device handbook volume 1 ? march 2010 altera corporation table 12?2 lists the idcode information for stratix iv devices. ep4sgx530 2970 ep4se230 2274 ep4se360 2682 ep4se530 2970 ep4se820 3402 ep4s40g2 2274 ep4s40g5 2970 ep4s100g2 2274 ep4s100g3 2970 ep4s100g4 2970 ep4s100g5 2970 note to tab l e 1 2? 1 : (1) for the f1932 package of ep4sgx290 and ep4sgx360 devices, the boundary-scan register length is 2970. table 12?1. stratix iv devices boundary-scan register length (part 2 of 2) device boundary-scan register length table 12?2. stratix iv devices idcode information (part 1 of 2) device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) ep4sgx70 0000 0010 0100 0010 0000 000 0110 1110 1 ep4sgx110 0000 0010 0100 0000 0000 000 0110 1110 1 ep4sgx180 0000 0010 0100 0010 0001 000 0110 1110 1 ep4sgx230 0000 0010 0100 0000 1001 000 0110 1110 1 ep4sgx290 (3) 0000 0010 0100 0010 0010 000 0110 1110 1 ep4sgx290 (4) 0000 0010 0100 0100 0011 000 0110 1110 1 ep4sgx360 (3) 0000 0010 0100 0000 0010 000 0110 1110 1 ep4sgx360 (4) 0000 0010 0100 1000 0011 000 0110 1110 1 ep4sgx530 0000 0010 0100 0000 0011 000 0110 1110 1 ep4se230 0000 0010 0100 0001 0001 000 0110 1110 1 ep4se360 0000 0010 0100 0001 0010 000 0110 1110 1 ep4se530 0000 0010 0100 0001 0011 000 0110 1110 1 ep4se820 0000 0010 0100 0000 0100 000 0110 1110 1 ep4s40g2 (5) 0000 0010 0100 0100 0001 000 0110 1110 1 ep4s40g5 (6) 0000 0010 0100 0010 0011 000 0110 1110 1 ep4s100g2 (5) 0000 0010 0100 0100 0001 000 0110 1110 1 ep4s100g3 0000 0010 0100 1010 0011 000 0110 1110 1 ep4s100g4 0000 0010 0100 0110 0011 000 0110 1110 1 chapter 12: jtag boundary-scan testing in stratix iv devices 12?3 i/o voltage support in a jtag chain ? march 2010 altera corporation stratix iv device handbook volume 1 1 if the device is in reset state, when the nconfig or nstatus signal is low, the device idcode might not be read correctly. to read the device idcode correctly, you must issue the idcode jtag instruction only when the nstatus signal is high. f for more information about the following topics, refer to the ieee 1149.1 (jtag) boundary-scan testing in stratix iii devices chapter in volume 1 of the stratix iii device handbook : jtag instruction codes with descriptions tap controller state-machine timing requirements for ieee std. 1149.1 signals instruction mode mandatory jtag instructions ( sample/preload , extest , and bypass) optional jtag instructions ( idcode , usercode, clamp , and highz) i/o voltage support in a jtag chain the jtag chain supports several devices. however, you must use caution if the chain contains devices that have different v ccio levels. f for more information, refer to the ieee 1 149.1 (jtag) boundary-scan testing in stratix iii devices chapter in volume 1 of the stratix iii device handbook . bst circuitry the ieee std. 1149.1 bst circuitry is enabled upon device power-up. you can perform bst on stratix iv devices before, during, and after configuration. stratix iv devices support bypass, idcode , and sample jtag instructions during configuration without interrupting configuration. to send all other jtag instructions, you must interrupt configuration using the config_io jtag instruction. f for more information, refer to an 39: ieee std. 1149.1 (jtag) boundary-scan testing in altera devices . ep4s100g5 (6) 0000 0010 0100 0010 0011 000 0110 1110 1 notes to ta bl e 12 ?2 : (1) the msb is on the left. (2) the lsb of the idcode is always 1. (3) the idcode is applicable for all packages except f1932. (4) the idcode is applicable for package f1932 only. (5) for the es1 device, the idcode is the same as the idcode of ep4sgx230. (6) for the es1 device, the idcode is the same as the idcode of ep4sgx530. table 12?2. stratix iv devices idcode information (part 2 of 2) device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) 12?4 chapter 12: jtag boundary-scan testing in stratix iv devices bsdl support stratix iv device handbook volume 1 ? march 2010 altera corporation f for more information about using the config_io jtag instruction for dynamic i/o buffer configuration, considerations when performing bst for configured devices, and jtag pin connections to mask-out the bst circuitry, refer to the ieee 1149.1 (jtag) boundary-scan testing in stratix iii devices chapter in volume 1 of the stratix iii device handbook . f for more information about using the ieee std.1149.1 circuitry for device configuration, refer to the configuration, design security, remote system upgrades chapter. f if you must perform bst for configured devices, you must use the quartus ii software version 8.1 and onwards to generate the design-specific boundary-scan description language (bsdl) files. for the procedure to generate post-configured bsdl files using the quartus ii software, refer to the bsdl files generation in quartus ii on the altera website. bsdl support bsdl, a subset of vhdl, provides a syntax that allows you to describe the features of an ieee std. 1149.1 bst-capable device that can be tested. f for more information about bsdl files for ieee std. 1149.1-compliant stratix iv devices, refer to the stratix iv bsdl files on the altera website. f bsdl files for ieee std. 1 149.1-compliant stratix iv devices can also be generated using the quartus ii software version 8.1 and onwards. for more information about the procedure to generate bsdl files using the quartus ii software, refer to the bsdl files generation in quartus ii on the altera website. document revision history table 12?3 shows the revision history for this chapter. table 12?3. document revision history (part 1 of 2) date and document version changes made summary of changes march 2010, v3.1 updated the hand note in the ?bst operation control? section. changed ?idcode jtag instruction? to read ?idcode? as needed. minor text edits ? november 2009, v3.0 updated table 12?1 and table 12?2. minor text edits. ? june 2009, v2.3 added an introductory paragraph to increase search ability. removed the conclusion section. minor text edits. ? april 2009 v2.2 updated table 12?1. ? march 2009 v2.1 updated table 12?1 and table 12?2. removed ?referenced documents? section. ? chapter 12: jtag boundary-scan testing in stratix iv devices 12?5 document revision history ? march 2010 altera corporation stratix iv device handbook volume 1 november 2008 v2.0 minor text edits. ? may 2008 v1.0 initial release. ? table 12?3. document revision history (part 2 of 2) date and document version changes made summary of changes 12?6 chapter 12: jtag boundary-scan testing in stratix iv devices document revision history stratix iv device handbook volume 1 ? march 2010 altera corporation ? march 2010 altera corporation stratix iv device handbook volume 1 13. power management in stratix iv devices this chapter describes power management in stratix ? iv devices. stratix iv devices offer programmable power technology options for low-power operation. you can use these options, along with speed grade choices, in different permutations to give the best power and performance combination. for thermal management, use the stratix iv internal temperature sensing device (tsd) with built-in analog-to-digital converter (adc) circuitry or external tsd with an external temperature sensor to easily incorporate this feature in your designs. being able to monitor the junction temperature of the device at any time also allows you the ability to control air flow to the device and save power for the whole system. overview stratix iv fpgas deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. stratix iv devices use advanced power management techniques to enable both density and performance increases while simultaneously reducing power dissipation. the total power of an fpga includes static and dynamic power. static power is the power consumed by the fpga when it is configured but no clocks are operating. dynamic power is comprised of switching power when the device is configured and running. you configure dynamic power with the equation shown in equation 13?1 . equation 13?1 shows that frequency is design-dependent. however, you can vary the voltage to lower dynamic power consumption by the square value of the voltage difference. stratix iv devices minimize static and dynamic power with advanced process optimizations and programmable power technology. these technologies enable stratix iv designs to optimally meet design-specific performance requirements with the lowest possible power. the quartus ? ii software optimizes all designs with stratix iv power technology to ensure performance is met at the lowest power consumption. this automatic process allows you to concentrate on the functionality of the design instead of the power consumption of the design. power consumption also affects thermal management. stratix iv devices offer a tsd feature that self-monitors the device junction temperature and can be used with external circuitry for other activities, such as controlling air flow to the stratix iv fpga. equation 13?1. dynamic power equation (note 1) note to equation 13?1 : (1) p = power; c = load capacitance; and v = supply voltage level. p 1 2 -- - cv 2 frequency = siv51013-3.1 13?2 chapter 13: power management in stratix iv devices stratix iv power technology stratix iv device handbook volume 1 ? march 2010 altera corporation this chapter contains the following sections: ?stratix iv power technology? ?stratix iv external power supply requirements? ?temperature sensing diode? stratix iv power technology the following sections describe stratix iv programmable power technology. programmable power technology stratix iv devices offer the ability to configure portions of the core, called tiles, for high-speed or low-power mode of operation performed by the quartus ii software without user intervention. setting a tile to high-speed or low-power mode is accomplished with on-chip circuitry and does not require extra power supplies brought into the stratix iv device. in a design compilation, the quartus ii software determines whether a tile must be in high-speed or low-power mode based on the timing constraints of the design. f for more information about how the quartus ii software uses programmable power technology when compiling a design, refer to an 514: power optimization in stratix iv fpgas . a stratix iv tile can consist of the following: memory logic array block (mlab)/logic array block (lab) pairs with routing to the pair mlab/lab pairs with routing to the pair and to adjacent digital signal processing (dsp)/memory block routing trimatrix memory blocks dsp blocks all blocks and routing associated with the tile share the same setting of either high-speed or low-power mode. by default, tiles that include dsp blocks or memory blocks are set to high-speed mode for optimum performance. unused dsp blocks and memory blocks are set to low-power mode to minimize static power. clock networks do not support programmable power technology. with programmable power technology, faster speed grade fpgas may require less power because there are fewer high-speed mlab and lab pairs, when compared with slower speed grade fpgas. the slower speed grade device may have to use more high-speed mlab and lab pairs to meet performance requirements, while the faster speed grade device can meet performance requirements with mlab and lab pairs in low-power mode. chapter 13: power management in stratix iv devices 13?3 stratix iv external power supply requirements ? march 2010 altera corporation stratix iv device handbook volume 1 the quartus ii software sets unused device resources in the design to low-power mode to reduce static and dynamic power. it also sets the following resources to low-power mode when they are not used in the design: labs and mlabs trimatrix memory blocks dsp blocks if a phase-locked loop (pll) is instantiated in the design, asserting the areset pin high keeps the pll in low-power mode. table 13?1 lists the available stratix iv programmable power capabilities. speed grade considerations can add to the permutations to give you flexibility in designing your system. stratix iv external power supply requirements this section describes the different external power supplies required to power stratix iv devices. you can supply some of the power supply pins with the same external power supply, provided they have the same voltage level. f for power supply pin connection guidelines and power regulator sharing, refer to the stratix iv gx and stratix iv e device family pin connection guidelines . f for each altera recommended power supply?s operating conditions, refer to the dc and switching characteristics chapter. temperature sensing diode the stratix iv tsd uses the characteristics of a pn junction diode to determine die temperature. knowing the junction temperature is crucial for thermal management. historically, junction temperature is calculated using ambient or case temperature, junction-to-ambient (ja) or junction to-case (jc) thermal resistance, and device power consumption. stratix iv devices can either monitor its die temperature with the internal tsd with built-in adc circuitry or the external tsd with an external temperature sensor. this allows you to control the air flow to the device. table 13?1. stratix iv programmable power capabilities feature programmable power technology lab yes routing yes memory blocks fixed setting (1) dsp blocks fixed setting (1) global clock networks no note to tab l e 1 3? 1 : (1) tiles with dsp blocks and memory blocks that are used in the design are always set to high-speed mode. by default, unused dsp blocks and memory blocks are set to low-power mode. 13?4 chapter 13: power management in stratix iv devices temperature sensing diode stratix iv device handbook volume 1 ? march 2010 altera corporation you can use the stratix iv internal tsd in two different modes of operations? power-up mode and user mode. for power-up mode, the internal tsd reads the die?s temperature during configuration if the alttemp_sense megafunction is enabled in your design. the alttemp_sense megafunction allows temperature sensing during device user mode by asserting the clken signal to the internal tsd circuitry. to reduce device static power, disable the internal tsd with built-in adc circuitry when not in use. f for more information about using the alttemp_sense megafunction, refer to the thermal sensor (alttemp_sense) megafunction u ser guide . the external temperature sensor steers bias current through the stratix iv external tsd, which measures forward voltage and converts this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). the 8-bit output represents the junction temperature of the stratix iv device and can be used for intelligent power management. external pin connections the stratix iv external tsd requires two pins for voltage reference. figure 13?1 shows howto connect the external tsd with an external temperature sensor device. as an example, external temperature sensing devices, such as max1619, max1617a, max6627, and adt 7411, can be connected to the two external tsd pins for temperature reading. f for more information about the external tsd specification, refer to the dc and switching characteristics chapter. the tsd is a very sensitive circuit that can be influenced by noise coupled from other traces on the board and possibly within the device package itself, depending on your device usage. the interfacing device registers? temperature is based on millivolts (mv) of difference, as seen at the external tsd pins. switching the i/o near the tsd pins can affect the temperature reading. altera recommends taking temperature readings during periods of inactivity in the device or use the internal tsd with built-in adc circuitry. the following are board connection guidelines for the tsd external pin connections: the maximum trace lengths for the tempdiode p /tempdiode n traces must be less than eight inches. route both traces in parallel and place them close to each other with grounded guard tracks on each side. altera recommends 10-mils width and space for both traces. figure 13?1. stratix iv tsd external pin connections stratix i v de vice tempdiodep external tsd tempdioden external te m p e r a t ure sensor chapter 13: power management in stratix iv devices 13?5 document revision history ? march 2010 altera corporation stratix iv device handbook volume 1 route traces through a minimum number of vias and crossunders to minimize the thermocouple effects. ensure that the number of vias are the same on both traces. ensure both traces are approximately the same length. avoid coupling with toggling signals (for example, clocks and i/o) by having the gnd plane between the diode traces and the high frequency signals. for high-frequency noise filtering, place an external capacitor (close to the external chip) between the tempdiode p /tempdiode n trace. for maxim devices, use an external capacitor between 2200 pf to 3300 pf. place a 0.1 uf bypass capacitor close to the external device. you can use internal tsd with built-in adc circuitry and external tsd at the same time. if you only use internal adc circuitry, the external tsd pins (tempdiode p /tempdiode n ) can connect these pins to gnd because the external tsd pins are not used. f for more information about the tempdiode p /tempdiode n pin connection when you are not using an external tsd, refer to the stratix iv pin connection guidelines . f for device specification and connection guidelines, refer to the external temperature sensor device data sheet from the device manufacturer. document revision history table 13?2 shows the revision history for this chapter. table 13?2. document revision history date and document version changes made summary of changes march 2010 v3.1 updated the ?external pin connections? section. minor text edits. ? november 2009 v3.0 updated the ?temperature sensing diode? and ?external pin connections? sections. updated equation 13?1. removed table 13-2: stratix iv external power supply pins. minor text edits. ? june 2009 v2.2 updated the ?external pin connections? section. added an introductory paragraph to increase search ability. removed the conclusion section. ? march 2009 v2.1 updated ?temperature sensing diode? and ?external pin connections? sections. updated figure 13?1. removed ?referenced documents? section. ? 13?6 chapter 13: power management in stratix iv devices document revision history stratix iv device handbook volume 1 ? march 2010 altera corporation november 2008 v2.0 minor text edits. ? may 2008 v1.0 initial release. ? table 13?2. document revision history date and document version changes made summary of changes 101 innovation drive san jose, ca 95134 www.altera.com stratix iv device handbook volume 2 siv5v2-4.1 copyright ? 2010 altera corporation. all rights reserved. altera, the programmable solutions company, the stylized altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of their respective holders. altera products are protected under numerous u.s. and foreign patents and pending ap- plications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specification s in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibilit y or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera cu stomers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services . ? march 2010 altera corporation stratix iv device handbook volume 2 contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix additional information about this handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-xi how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-xi typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-xi section i. transceiver architecture revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 chapter 1. stratix iv transceiver architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 transceiver channel locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 stratix iv gx device offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 stratix iv gt device offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 transceiver block architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 transceiver channel architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 transmitter channel datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 receiver channel datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 cmu channel architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-97 configuring cmu channels for clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-98 configuring cmu channels as transceiver channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-103 other cmu channel features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-106 dynamic reconfiguration of the cmu channel analog controls . . . . . . . . . . . . . . . . . . . . . . . . 1-107 functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-107 basic functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-108 deterministic latency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-119 pci express (pipe) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124 xaui mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-150 gige mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-161 sonet/sdh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-169 sdi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-175 (oif) cei phy interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-179 serial rapidio mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-180 basic (pma direct) functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-185 loopback modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-188 serial loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-188 parallel loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-189 reverse serial loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-191 reverse serial pre-cdr loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-191 pci express (pipe) reverse parallel loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 192 auxiliary transmit (atx) pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-193 6g atx pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-193 10g atx pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-194 input reference clocks for the atx pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-196 architecture of the atx pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-197 atx clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-198 the differences between 10g atx pll, 6g atx pll, and cmu pll . . . . . . . . . . . . . . . . . . . . . . 1-198 iv contents stratix iv device handbook volume 2 ? march 2010 altera corporation calibration blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-199 calibration block location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-199 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-203 input signals to the calibration block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-203 built-in self test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-204 bist mode pattern generators and verifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-204 prbs in single-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-206 prbs in double-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-206 transceiver port lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-207 reference information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-223 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-225 chapter 2. stratix iv transceiver clocking glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 input reference clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 input reference clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 refclk0 and refclk1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 inter-transceiver block (itb) clock lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 dedicated clk input pins on the fpga global clock network . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 clock output from left and right plls in the fpga fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 fpga fabric plls-transceiver plls cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 example 1: channel configuration with 4-gbps data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 dedicated left and right pll cascade network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 fpga fabric plls-transceiver plls cascading in the 780-pin package . . . . . . . . . . . . . . . . . . . . . 2-11 fpga fabric plls-transceiver plls cascading in the 1152-pin package . . . . . . . . . . . . . . . . . . . . 2-11 fpga fabric plls-transceiver plls cascading in the 1517-pin package . . . . . . . . . . . . . . . . . . . . 2-12 fpga fabric plls-transceiver plls cascading in the 1932-pin package . . . . . . . . . . . . . . . . . . . . 2-13 fpga fabric plls-transceiver plls cascading rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 example 2: design target?ep4sgx530nf45 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 left and right, left, or right pll in vco bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 7 transceiver channel datapath clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 transmitter channel datapath clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 transmitter channel-to-channel skew optimization for modes other than basic (pma direct) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 transmitter channel datapath clocking resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 transmitter channel clocking configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -23 non-bonded channel configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 bonded channel configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 non-bonded basic (pma direct) mode channel configurations . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 bonded basic (pma direct) n mode channel configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 receiver channel datapath clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 non-bonded channel configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 bonded channel configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 basic (pma direct) mode channel configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 fpga fabric-transceiver interface clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 fpga fabric-transmitter interface clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 quartus ii-selected transmitter phase compensation fifo write clock . . . . . . . . . . . . . . . . . . 2-51 user-selected transmitter phase compensation fifo write clock . . . . . . . . . . . . . . . . . . . . . . . 2-57 fpga fabric-receiver interface clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60 quartus ii software-selected receiver phase compensation fifo read clock . . . . . . . . . . . . . 2-61 user-selected receiver phase compensation fifo read clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68 using the cmu/atx pll for clocking user logic in the fpga fabric . . . . . . . . . . . . . . . . . . . . . . . . 2-71 contents v ? march 2010 altera corporation stratix iv device handbook volume 2 configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73 configuration example 1: configuring 24 channels in basic (pma direct) n mode in the ep4s100g5f45 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73 configuration example 2: configuring sixteen identical channels across four transceiver blocks . 2-75 configuration example 3: configuring sixteen channels across four transceiver blocks . . . . . . 2-76 configuration example 4: configuring left and right, left, or right pll in vco bypass mode 2-78 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81 chapter 3. configuring multiple protocols and data rates in a transceiver block overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 creating transceiver channel instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 general requirements to combine channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 transmitter buffer voltage (v cch ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 transceiver analog power (v cca_l/r ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 gxb_powerdown port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 reconfig_fromgxb and reconfig_togxb ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 calibration clock and power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 sharing cmu plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 multiple channels sharing a cmu pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 sharing atx plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 combining receiver only channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 combining transmitter channel and receiver channel instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 multiple transmitter channel and receiver channel instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 combining transceiver instances in multiple transceiver blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 example 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 combining transceiver instances using pll cascade clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 combining channels configured in protocol functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 combining channels in bonded functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 6 bonded 4 functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 bonded x8 functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 combining channels configured in deterministic latency mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 combining channels using the pci express hard ip block with other channels . . . . . . . . . . . . . 3-23 combining transceiver channels with basic (pma direct) configuration . . . . . . . . . . . . . . . . . . . . . . 3-24 combining multiple channels configured in basic (pma direct) 1 configurations . . . . . . . . . . 3-25 multiple basic (pma direct) 1 configuration instances with one channel per instance . . . . 3-25 one instance in basic (pma direct) 1 configuration with multiple transceiver channels . . 3-25 combining multiple instances of tx only and rx only configurations in basic (pma direct) 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 combining channels configured in basic (pma direct) 1 with non-basic (pma direct) modes 3-28 basic (pma direct) n configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 channel placement in a basic (pma direct) n mode instance . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 examples of combining multiple instances of basic (pma direct) n modes . . . . . . . . . . . . . . 3-34 vi contents stratix iv device handbook volume 2 ? march 2010 altera corporation combination requirements when channel reconfiguration is enabled . . . . . . . . . . . . . . . . . . . . . . . . 3-41 combination requirements when the use alternate cmu pll option is selected . . . . . . . . . . . . 3-41 example 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 key observations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 combination requirements when multiple tx plls are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 example 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 combining transceiver channels when the adaptive equalization (aeq) is enabled . . . . . . . . . . . 3-46 example 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 combination requirements for stratix iv gt devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 placement rules for transceiver channels at 9.9 gbps to 10.3125 gbps . . . . . . . . . . . . . . . . . . . . . . 3-48 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 chapter 4. reset control and power down user reset and power-down signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 blocks affected by the reset and power-down signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -3 transceiver reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 all supported functional modes except the pci express (pipe) functional mode . . . . . . . . . . . . . 4-5 bonded channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 non-bonded channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 pci express (pipe) functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 pci express (pipe) reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 pci express (pipe) initialization/compliance phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 pci express (pipe) normal phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 pma direct drive mode reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 basic (pma direct) drive n mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 transmitter only channel with no pll_l/r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4 transmitter only channel with a pll_l/r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 basic (pma direct) drive x1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 receiver and transmitter channel set-up?receiver cdr in automatic lock mode . . . . . . . 4-31 receiver and transmitter channel set-up?receiver cdr in manual lock mode . . . . . . . . . . 4-33 dynamic reconfiguration reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 reset sequence when using dynamic reconfiguration with the ?data rate division in tx? option . . . 4-34 reset sequence when using dynamic reconfiguration with the ?channel and tx pll select/reconfig? option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 simulation requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 reference information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 chapter 5. stratix iv dynamic reconfiguration glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 dynamic reconfiguration controller architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration . . . . . . . . 5-4 altgx megawizard plug-in manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 the reconfig_clk clock requirements for the altgx instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 altgx_reconfig megawizard plug-in manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 the reconfig_clk clock requirements for the altgx_reconfig instance . . . . . . . . . . . . . . . . 5-5 interfacing altgx and altgx_reconfig instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 logical channel addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 total number of channels option in the altgx_reconfig instance . . . . . . . . . . . . . . . . . . . 5-10 connecting the altgx and altgx_reconfig instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 contents vii ? march 2010 altera corporation stratix iv device handbook volume 2 dynamic reconfiguration modes implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 pma controls reconfiguration mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 dynamically reconfiguring pma controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 transceiver channel reconfiguration mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -19 memory initialization file (.mif) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 channel and cmu pll reconfiguration mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 channel reconfiguration with transmitter pll select mode details . . . . . . . . . . . . . . . . . . . . . . 5-48 cmu pll reconfiguration mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 central control unit reconfiguration mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 special guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 data rate division in transmitter mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -63 offset cancellation feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 altgx_reconfig instance signals transition during offset cancellation . . . . . . . . . . . . . . . 5-68 eyeq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 enabling the eyeq control logic and the eyeq hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 connections between the altgx and altgx_reconfig instances . . . . . . . . . . . . . . . . . . . . 5-70 controlling the eyeq hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71 adaptive equalization (aeq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74 adaptive equalization limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74 enabling the aeq control logic and aeq hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75 connections between the altgx and altgx_reconfig instances . . . . . . . . . . . . . . . . . . . . 5-75 controlling the aeq hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77 dynamic reconfiguration controller port list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78 error indication during dynamic reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91 dynamic reconfiguration duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92 pma controls reconfiguration duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92 offset cancellation duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94 dynamic reconfiguration duration for channel and transmitter pll select/reconfig modes . . . 5-94 dynamic reconfiguration (altgx_reconfig instance) resource utilization . . . . . . . . . . . . . . . . . 5-95 functional simulation of the dynamic reconfiguration process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96 dynamic reconfiguration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96 example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96 example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-101 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103 viii contents stratix iv device handbook volume 2 ? march 2010 altera corporation ? march 2010 altera corporation stratix iv device handbook volume 2 chapter revision dates the chapters in this book, stratix iv device handbook volume 2 , were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1 stratix iv transceiver architecture revised: march 2010 part number: siv52001-4.1 chapter 2 stratix iv transceiver clocking revised: march 2010 part number: siv52002-3.1 chapter 3 configuring multiple protocols and data rates in a transceiver block revised: november 2009 part number: siv52003-4.0 chapter 4 reset control and power down revised: november 2009 part number: siv52004-4.0 chapter 5 stratix iv dynamic reconfiguration revised: march 2010 part number: siv52005-3.1 x chapter revision dates stratix iv device handbook volume 2 ? march 2010 altera corporation ? march 2010 altera corporation stratix iv device handbook volume 2 additional information about this handbook this handbook provides comprehensive information about the altera ? stratix ? iv family of devices. how to contact altera for the most up-to-date information about altera products, see the following table. typographic conventions the following table shows the typographic conventions that this document uses. contact (note 1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature non-technical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicates command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicates document titles. for example, an 519: stratix iv design guidelines. italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, info?xii additional information stratix iv device handbook volume 2 ? march 2010 altera corporation courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . active-low signals are denoted by suffix n . for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). 1., 2., 3., and a., b., c., and so on. numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. r the angled arrow instructs you to press enter . f the feet direct you to more information about a particular topic. visual cue meaning ? march 2010 altera corporation stratix iv device handbook volume 2 section i. transceiver architecture this section provides a description of transceiver architecture and transceiver clocking for the stratix ? iv device family. it also describes configuring for multiple protocols and data rates, reset control and power down, and dynamic reconfiguration for stratix iv devices. this section includes the following chapters: chapter 1, stratix iv transceiver architecture chapter 2, stratix iv transceiver clocking chapter 3, configuring multiple protocols and data rates in a transceiver block chapter 4, reset control and power down chapter 5, stratix iv dynamic reconfiguration revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook. i?2 section i: transceiver architecture stratix iv device handbook volume 2 ? march 2010 altera corporation ? march 2010 altera corporation stratix iv device handbook volume 2 1. stratix iv transceiver architecture this chapter provides details about stratix ? iv gx and gt transceiver architecture, transceiver channels, available modes, and a description of transmitter and receiver channel datapaths. f for information about upcoming stratix iv device features, refer to the upcoming stratix iv device features document. f for information about changes to the currently published stratix iv device handbook , refer to the addendum to the stratix iv device handbook chapter. overview stratix iv fpgas deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise with two offerings: stratix iv gx and stratix iv gt. stratix iv gx devices are part of the altera ? 40 nm stratix iv device family. stratix iv gx devices provide up to 32 full-duplex cdr-based transceivers with physical coding sublayer (pcs) and physical medium attachment (pma), at serial data rates between 600 mbps and 8.5 gbps. also, stratix iv gx provides up to 16 additional full-duplex cdr-based transceivers with pma supporting serial data rates between 600 mbps and 6.5 gbps. table 1?1 shows the stratix iv gx serial protocols the transceiver channels support. to implement proprietary protocols, the transceiver channels in the stratix iv gx device supports the highly flexible basic single-width (600 mbps to 3.75 gbps) and basic double-width (1 gbps to 8.5 gbps) functional modes. tab le 1 ?1 . serial protocols supported by the stratix iv gx transceiver channels protocol description pci express (pipe) gen 1 at 2.5 gbps and gen 2 at 5.0 gbps xaui 3.125 gbps to 3.75 gbps for higig support gige 1.25 gbps serial rapidio 1.25 gbps, 2.5 gbps, and 3.125 gbps sonet/sdh oc-12 at 622 mbps, oc-48 at 2.488 gbps, and oc-96 at 4.976 gbps (oif) cei phy interface 4.976 gbps to 6.375 gbps for interlaken support serial digital interface (sdi) hd-sdi at 1.485 gbps and 1.4835 gbps 3g-sdi at 2.97 gbps and 2.967 gbps siv52001-4.l 1?2 chapter 1: stratix iv transceiver architecture overview stratix iv device handbook volume 2 ? march 2010 altera corporation stratix iv gt devices are also part of altera?s 40 nm stratix iv device family and contain serial transceivers that support data rates between 2.488 gbps and 11.3 gbps. stratix iv gt devices are targeted towards implementing 40 gbps/100 gbps transceiver links. example applications include 40g/100g ethernet and sfi-s. stratix iv gt devices can be broadly classified into the following: stratix iv gt devices targeted to achieve 100 gbps ingress/egress data rates?48 full duplex clock and clock data recovery (cdr)-based transceivers, 32 of which support data rates up to 11.3 gbps stratix iv gt devices targeted to achieve 40 gbps ingress/egress data rates?36 full duplex cdr-based transceivers, 12 of which support data rates up to 11.3 gbps though optimized for 40 gbps/100 gbps systems, stratix iv gt transceivers also provide pma and pcs support for the protocols shown in table 1?2 . to implement proprietary protocols, the transceiver channels in the stratix iv gt device support the highly flexible basic single-width (2.488 gbps to 3.75 gbps) and basic double-width (2.488 gbps to 11.3 gbps) functional modes. f stratix iv gx and gt devices have pci express hard ip, pcs, and pma blocks. for more information, refer to the pci express compiler user guide . f for more information about stratix iv gx and gt protocols, refer to the configuring multiple protocols and data rates in a transceiver block chapter. tab le 1 ?2 . serial protocols supported by the stratix iv gt transceiver channels protocol description pci express (pipe) gen 1 at 2.5 gbps and gen 2 at 5.0 gbps xaui 3.125 gbps up to higig at 3.75 gbps serial rapidio 2.5 gbps and 3.125 gbps sonet/sdh oc-48 and oc-96 (oif) cei phy interface 4.976 gbps to 6.375 gbps serial digital interface (sdi) 3g-sdi at 2.97gbps and 2.967 gbps chapter 1: stratix iv transceiver architecture 1?3 overview ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?1 shows an example of the stratix iv gx and gt transceiver architecture. links to the corresponding transceiver architecture descriptions are listed below. this is an elementary diagram and does not represent an actual transceiver block. descriptions for the example transceiver architecture are as follows: 1. ?transceiver block architecture? on page 1?11 2. ?transceiver channel architecture? on page 1?12 3. ?transmitter channel datapath? on page 1?14 4. ?transmitter local clock divider block? on page 1?35 5. ?receiver channel datapath? on page 1?36 6. ?cmu channel architecture? on page 1?97 7. ?loopback modes? on page 1?188 figure 1?1. example of a transceiver block transceiver block gxbl1 transceiver channel 3 transceiver channel 2 transceiver channel 1 transceiver channel 0 transceiver block transceiver block gxbl0 transceiver block gxbr1 transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel central control unit (ccu) atx pll block local clock divider block calibration block 6 6 8 atx pll block 8 2 2 2 transmitter channel datapath 3 4 receiver channel datapath 5 bist loopback 7 bist 10 loopback 7 bist loopback 7 bist 10 loopback 7 calibration block 9 calibration block calibration block 9 1 2 1 9 9 10 10 1?4 chapter 1: stratix iv transceiver architecture transceiver channel locations stratix iv device handbook volume 2 ? march 2010 altera corporation 8. ?auxiliary transmit (atx) pll block? on page 1?193 9. ?calibration blocks? on page 1?199 10. ?built-in self test modes? on page 1?204 transceiver channel locations stratix iv gx and gt transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks. the total number of transceiver channels and the location of transceiver blocks varies from device to device. stratix iv gx device offerings table 1?3 summarizes the total number of transceiver channels and transceiver block locations in each stratix iv gx device member. tab le 1 ?3 . number of transceiver channels and transceiver block locations in stratix iv gx devices (part 1 of 2) device member tot al n umbe r of transceiver channels transceiver channel location ep4sgx70df29 ep4sgx110df29 ep4sgx180df29 ep4sgx230df29 8 eight transceiver channels located in two transceiver blocks: right side? gxbr0 and gxbr1 refer to figure 1?2 on page 1?5 . ep4sgx290fh29 ep4sgx360fh29 ep4sgx110ff35 ep4sgx180ff35 ep4sgx230ff35 ep4sgx290ff35 ep4sgx360ff35 16 eight transceiver channels located in two transceiver blocks: right side? gxbr0 and gxbr1 left side? gxbl0 and gxbl1 refer to figure 1?2 on page 1?5 . ep4sgx180hf35 ep4sgx230hf35 ep4sgx290hf35 ep4sgx360hf35 ep4sgx530hh35 24 eight regular transceiver channels supporting data rates between 600 mbps and 8.5 gbps and four clock multiplier unit (cmu) channels supporting data rates between 600 mbps and 6.5 gbps located in two transceiver blocks: right side? gxbr0 and gxbr1 left side? gxbl0 and gxbl1 refer to figure 1?3 on page 1?6 . chapter 1: stratix iv transceiver architecture 1?5 transceiver channel locations ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?2 shows transceiver channel locations in each stratix iv gx device member that have 8 or 16 transceiver channels. ep4sgx180kf40 ep4sgx230kf40 ep4sgx290kf40 ep4sgx360kf40 ep4sgx530kf40 36 twelve regular transceiver channels supporting data rates between 600 mbps and 8.5 gbps and six cmu channels supporting data rates between 600 mbps and 6.5 gbps located in three transceiver blocks: right side? gxbr0 , gxbr1 , and gxbr2 left side? gxbl0 , gxbl1 , and gxbl2 refer to figure 1?3 on page 1?6 . ep4sgx530nf45 48 sixteen regular transceiver channels supporting data rates between 600 mbps and 8.5 gbps and eight cmu channels supporting data rates between 600 mbps and 6.5 gbps located in four transceiver blocks: right side? gxbr0 , gxbr1 , gxbr2 , and gxbr3 left side? gxbl0 , gxbl1 , gxbl2 , and gxbl3 refer to figure 1?3 on page 1?6 . tab le 1 ?3 . number of transceiver channels and transceiver block locations in stratix iv gx devices (part 2 of 2) device member tot al n umbe r of transceiver channels transceiver channel location figure 1?2. stratix iv gx devices with 8 and 16 transceiver channels ep4sgx70df29 ep4sgx110df29 ep4sgx180df29 ep4sgx230df29 (8 transceivers) transceiver block gxbr1 transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 transceiver block gxbl1 transceiver block gxbl0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 ep4sgx290fh29, ep4sgx360fh29, ep4sgx110ff35, ep4sgx180ff35, ep4sgx230ff35, ep4sgx290ff35, ep4sgx360ff35 (16 transceivers) atx pll r0 (6g) atx pll r0 (6g) 1?6 chapter 1: stratix iv transceiver architecture transceiver channel locations stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?3 shows transceiver channel locations in each stratix iv gx device member that have 24, 36, or 48 transceiver channels. figure 1?3. stratix iv gx device with 24, 36, or 48 transceiver channels note to figure 1?3 : (1) the 6g atx pll r1 and l1 blocks are not availa ble in the ep4sgx230kf40 and ep4sgx530kf40 devices. ep4sgx530nf45, ep4sgx290nf45, ep4sgx360nf45, (48 transceivers) transcei v er block gxbl3 transcei v er block gxbl2 transcei v er block gxbr2 transcei v er block gxbl1 transcei v er block gxbr1 transcei v er block gxbl0 transcei v er block gxbr0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 transcei v er block gxbr3 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 ep4sgx180kf40, ep4sgx230kf40 (1), ep4sgx290kf40, ep4sgx290kf43, ep4sgx360kf43, ep4sgx530kf43, ep4sgx360kf40, ep4sgx530kf40 (1), (36 transceivers) ep4sgx180hf35, ep4sgx230hf35, ep4sgx290hf35, ep4sgx360hf35, ep4sgx530hh35, (24 transceivers) atx pll l1 (6g) (1) atx pll r1 (6g) (1) atx pll l0 (6g) atx pll r01 (6g) chapter 1: stratix iv transceiver architecture 1?7 transceiver channel locations ? march 2010 altera corporation stratix iv device handbook volume 2 stratix iv gt device offerings table 1?4 lists the stratix iv gt device offerings along with the number of transceiver channels available in each device. table 1?5 lists the transceiver blocks in each stratix iv gt device that support transceiver channels up to 11.3 gbps. tab le 1 ?4 . stratix iv gt device offerings and transceiver channels available in each device transceiver channels ep4s40g2f40 (4) ep4s40g5h40 ep4s100g2f40 (4) ep4s100g5h40 ep4s100g3f45, ep4s100g4f45 ep4s100g5f45 tot al transceiver channels 36 36 36 36 48 48 10g transceiver channels (1) 12 12 24 24 24 32 8g transceiver channels (2) 12 12 0 0 8 0 cmu channels (pma-only) (3) 12 12 12 12 16 16 notes to ta bl e 1? 4 : (1) 10g transceiver channels support data rates between 2.488 gbps and 11.3 gbps. (2) 8g transceiver channels support data ra tes between 2.488 gbps and 8.5 gbps. all 10g tr ansceiver channels can also be configure d as 8g transceiver channels. for example, the ep4s 40g2f40 device has twenty-four 8g transceiver channels and the ep4s100g5f45 device h as thirty-two 8g transceiver channels. (3) cmu channels that support data rates between 2.488 gbps and 6.5 gbps are pma-only channels that do not have pcs circuitry. for more information, refer to ?cmu channel architecture? on page 1?97 . (4) f40 devices use 1517-pin flip chip packages. h40 devices use 1517-pin hybrid flip chip packages. f45 devices use 1932-pin fl ip chip packages. tab le 1 ?5 . transceiver blocks in stratix iv gt devices supporting transceiver channels up to 11.3 gbps (part 1 of 2) device member total number of transceiver channels transceiver channel location ep4s40g2f40 36 12 regular transceiver channels (six 10g and six 8g), located in three transceiver blocks: left side?4 in gxbl2, 2 in gxbl1 right side?4 in gxbr2, 2 in gxbr1 refer to figure 1?4 on page 1?9 . ep4s40g5h40 36 12 regular transceiver channels (six 10g and six 8g), located in three transceiver blocks: left side?4 in gxbl2, 4 in gxbl1, 4 in gxbl0 right side?4 in gxbr2, 4 in gxbr1, 4 in gxbr0 refer to figure 1?4 on page 1?9 . 1?8 chapter 1: stratix iv transceiver architecture transceiver channel locations stratix iv device handbook volume 2 ? march 2010 altera corporation ep4s100g2f40 36 12 regular transceiver channels, capable of 10g each, located in three transceiver blocks: left side?4 in gxbl2, 4 in gxbl1, 4 in gxbl0 right side?4 in gxbr2, 4 in gxbr1, 4 in gxbr0 refer to figure 1?5 on page 1?10 . ep4s100g5h40 36 12 regular transceiver channels, capable of 10g each, located in three transceiver blocks: left side?4 in gxbl2, 4 in gxbl1, 4 in gxbl0 right side?4 in gxbr2, 4 in gxbr1, 4 in gxbr0 refer to figure 1?5 on page 1?10 . ep4s100g3f45 48 16 regular transceiver channels (twelve 10g and four 8g) located in four transceiver blocks: left side?4 in gxbl3, 4 in gxbl2, 4 in gxbl1, 4 in gxbl0 right side?4 in gxbr3, 4 in gxbr2, 4 in gxbr1, 4 in gxbr0 refer to figure 1?5 on page 1?10 . ep4s100g4f45 48 16 regular transceiver channels (twelve 10g and four 8g) located in four transceiver blocks: left side?4 in gxbl3, 4 in gxbl2, 4 in gxbl1, 4 in gxbl0 right side?4 in gxbr3, 4 in gxbr2, 4 in gxbr1, 4 in gxbr0 refer to figure 1?5 on page 1?10 . ep4s100g5f45 48 16 regular transceiver channels, all capable of 10g each, located in four transceiver blocks: left side?4 in gxbl3, 4 in gxbl2, 4 in gxbl1, 4 in gxbl0 right side?4 in gxbr3, 4 in gxbr2, 4 in gxbr1, 4 in gxbr0 refer to figure 1?5 on page 1?10 . tab le 1 ?5 . transceiver blocks in stratix iv gt devices supporting transceiver channels up to 11.3 gbps (part 2 of 2) device member total number of transceiver channels transceiver channel location chapter 1: stratix iv transceiver architecture 1?9 transceiver channel locations ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?4 and figure 1?5 show transceiver channel and pll locations for all stratix iv gt devices offered. figure 1?4. transceiver channel and pll locations in ep4s40g2f40 and ep4s40g5h40 devices (note 1) note to figure 1?4 : (1) ep4s40g2f40c2es1 devices do not have 10g auxiliary transmit (atx) pll blocks. use the cmu pll to generate transceiver clocks for channels configured at 11.3 gbps. atx pll (10g) atx pll (6g) atx pll (10g) atx pll (6g) transcei v er block gxbr0 transcei v er block gxbr1 transcei v er block gxbr2 transcei v er block gxbl0 transcei v er block gxbl1 transcei v er block gxbl2 10g channel 3 10g channel 2 cmu channel 1 cmu channel 0 10g channel 1 10g channel 0 10g channel 3 10g channel 2 cmu channel 1 cmu channel 0 8g channel 1 8g channel 0 8g channel 3 8g channel 2 cmu channel 1 cmu channel 0 8g channel 1 8g channel 0 10g channel 3 10g channel 2 cmu channel 1 cmu channel 0 10g channel 1 10g channel 0 10g channel 3 10g channel 2 cmu channel 1 cmu channel 0 8g channel 1 8g channel 0 8g channel 3 8g channel 2 cmu channel 1 cmu channel 0 8g channel 1 8g channel 0 ep4s40g2f40, ep4s40g5h40 1?10 chapter 1: stratix iv transceiver architecture transceiver channel locations stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?5. transceiver channel and pll locations in ep4s100g2f40, ep4s100g5h40, ep4s100g3f45, ep4s100g4f45, and ep4s100g5f45 devices note to figure 1?5 : (1) ep4s100g2f40c2es1 devices do not have 10g atx pll blocks. use the cmu pll to generate transceiver clocks for channels config ured at 11.3 gbps. (2) ep4s100g5f45 devices are the same as ep4s100g3f45 and ep4s100g4f45 devices except that the gxbr0 transceiver block is 10g in stead of 8g. atx pll (10g) atx pll (6g) atx pll (10g) atx pll (6g) transceiver block gxbr0 transceiver block gxbr1 transceiver block gxbr2 transceiver block gxbl0 transceiver block gxbl1 transceiver block gxbl2 ep4s100g2f40 ep4s100g5h40 transceiver block gxbr0 atx pll (6g) transceiver block gxbl0 atx pll (6g) ep4s100g3f45, ep4s100g4f45 channel 3 (10g) channel 2 (10g) cmu channel 1 cmu channel 0 channel 1 (10g) channel 0 (10g) channel 3 (8g) channel 2 (8g) cmu channel 1 cmu channel 0 channel 1 (8g) channel 0 (8g) atx pll (10g) atx pll (6g) transceiver block gxbr0 transceiver block gxbr1 transceiver block gxbr2 transceiver block gxbr0 atx pll (6g) ep4s100g5f45 (2) cmu channel 0 channel 1 (10g) channel 0 (10g) channel 3 (10g) channel 2 (10g) cmu channel 1 cmu channel 0 channel 1 (10g) channel 0 (10g) channel 3 (10g) channel 2 (10g) cmu channel 1 cmu channel 0 channel 1 (10g) channel 0 (10g) channel 3 (10g) channel 2 (10g) cmu channel 1 cmu channel 0 channel 1 (10g) channel 0 (10g) channel 3 (10g) channel 2 (10g) cmu channel 1 cmu channel 0 channel 1 (10g) channel 0 (10g) channel 3 (10g) channel 2 (10g) cmu channel 1 cmu channel 0 channel 1 (10g) channel 0 (10g) channel 3 (8g) channel 2 (8g) cmu channel 1 cmu channel 0 channel 1 (8g) channel 0 (8g) channel 3 (10g) channel 2 (10g) cmu channel 1 cmu channel 0 channel 1 (10g) channel 0 (10g) channel 3 (10g) channel 2 (10g) cmu channel 1 cmu channel 0 channel 1 (10g) channel 0 (10g) channel 3 (10g) channel 2 (10g) cmu channel 1 cmu channel 0 channel 1 (10g) channel 0 (10g) channel 3 (10g) channel 2 (10g) cmu channel 1 cmu channel 0 channel 1 (10g) channel 0 (10g) chapter 1: stratix iv transceiver architecture 1?11 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 transceiver block architecture figure 1?6 shows the transceiver block architecture of stratix gx and gt devices. each transceiver block has the following components: 1. four full-duplex (transmitter and receiver) transceiver channels that support serial data rates from 600 mbps to 8.5 gbps in stratix iv gx devices and 2.488 gbps to 11.3 gbps in stratix iv gt devices. for more information, refer to ?transceiver channel architecture? on page 1?12 . 2. two cmu channels? cmu0 and cmu1 channels?that provide the high-speed serial and low-speed parallel clock to the transceiver channels. for more information, refer to ?cmu channel architecture? on page 1?97 . 3. central control unit (ccu) that implements the xaui state machine for xgmii-to-pcs code group conversion, xaui deskew state machine, shared control signal generation block, pci express (pipe) rateswitch controller block, and reset control logic the shared control signal generation block provides control signals to the transceiver channels in bonded functional modes, such as xaui, pci express (pipe), and basic 4. the pci express (pipe) rateswitch controller block controls the rateswitch circuit in the cmu0 channel in 4 configurations. in pci express (pipe) 8 configuration, the pci express (pipe) rateswitch controller block of the ccu in the master transceiver block is active. for more information, refer to ?pci express (pipe) gen2 (5 gbps) support? on page 1?138 . figure 1?6. top-level view of a transceiver block transceiver block gxbl1 transceiver channel 3 transceiver channel 2 transceiver channel 1 transceiver channel 0 transceiver block transceiver block gxbl0 transceiver block gxbr1 transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel central control unit (ccu) 1 2 2 1 1 1 3 1?12 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the stratix iv gt transceiver architecture has the following components: regular transceiver channels with pma and pcs support cmu channels with pma-only support atx pl l blocks four transceiver channels and two cmu channels are located in each transceiver block on the left and right sides of the device. each stratix iv gt device also has two 10g atx plls that support data rates between 9.9 gbps and 11.3 gbps. additionally, each stratix iv gt device has two 6g atx plls that support data rates between 2.488 gbps and 6.5 gbps, except the ep4s100g5f45 device that has four 6g atx plls. 1 the 6g atx pll does not support all data rates between 2.488 gbps and 6.5 gbps. transceiver channel architecture figure 1?7 shows the stratix iv gx and gt transceiver channel datapath. each transceiver channel consists of the: transmitter channel, further divided into: transmitter channel pcs transmitter channel pma receiver channel, further divided into: receiver channel pcs receiver channel pma figure 1?7. stratix iv gx and gt transceiver datapath byte deserializer byte serializer 8b10 decoder 8b/10b encoder rate match fifo receiver channel pcs receiver channel pma deskew fifo word aligner rx_datain deserializer cdr transmitter channel pcs transmitter channel pma tx_dataout serializer wrclk wrclk rdclk rdclk pci express hard ip fpga fabric pipe interface transmitter channel datapath receiver channel datapath tx phase compensation fifo byte ordering rx phase compensation fifo chapter 1: stratix iv transceiver architecture 1?13 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 each transceiver channel interfaces to either the pci express (pipe) hard ip block (pci express [pipe] hard ip-transceiver interface) or directly to the fpga fabric (fpga fabric-transceiver interface). the transceiver channel interfaces to the pci express (pipe) hard ip block if the hard ip block is used to implement the pci express (pipe) phy mac, data link layer, and transaction layer. otherwise, the transceiver channel interfaces directly to the fpga fabric. each regular stratix iv gt transceiver channel can be categorized into: 8g transceiver channel?supports data rates between 2.488 gbps and 8.5 gbps 10g transceiver channel?supports data rates between 2.488 gbps and 11.3 gbps 1 the pci express (pipe) hard ip-transceiver interface is beyond the scope of this chapter. this chapter describes the fpga fabric-transceiver interface. f for more information about the pci express (pipe) hard ip block, refer to the pci express compiler user guide . figure 1?8 shows the fpga fabric-transceiver interface and transceiver pma-pcs interface. the transceiver channel datapath can be divided into the following two modes based on the fpga fabric-transceiver interface width (channel width) and the transceiver channel pma-pcs width (serialization factor): single-width mode double-width mode figure 1?8. fpga fabric-transceiver interface and transceiver pma-pcs interface pma-pcs interface fpga fabric byte deserializer byte serializer 8b10 decoder 8b/10b encoder rate match fifo receiver channel pcs deskew fifo transmitter channel pcs wrclk wrclk rdclk rdclk tx phase compensation fifo byte ordering rx phase compensation fifo transmitter channel pma rx_datain cdr tx_dataout serializer receiver channel pma word aligner deserializer tx_clkout tx_clkout fpga fabric pma-pcs interface fpga fabric-transceiver interface pci express hard ip pipe interface 1?14 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation table 1?6 shows the fpga fabric-transceiver interface widths (channel width) and transceiver pma-pcs widths (serialization factor) allowed in single-width and double-width modes. transmitter channel datapath the transmitter channel datapath, shown in figure 1?7 on page 1?12 , consists of the following blocks: tx phase compensation fifo byte serializer 8b/10b encoder transmitter output buffer the stratix iv gx and gt transceiver provides the enable low latency pcs mode option in the altgx megawizard ? plug-in manager. if you select this option, the 8b/10b encoder in the datapath is disabled. tx phase compensation fifo the tx phase compensation fifo interfaces the transmitter channel pcs and the fpga fabric pci express (pipe) interface. it compensates for the phase difference between the low-speed parallel clock and the fpga fabric interface clock. the tx phase compensation fifo operates in low-latency and high-latency modes. figure 1?9 shows the datapath and clocking of the tx phase compensation fifo. tab le 1 ?6 . fpga fabric-transceiver interface width and transceiver pma-pcs widths name single-width double-width pma-pcs interface widths 8/10 bit 16/20 bit fpga fabric-transceiver interface width 8/10 bit 16/20 bit 16/20 bit 32/40 bit supported functional modes pci express (pipe) gen1 and gen2 xaui gige serial rapidio sonet/sdh oc12 and oc48 sdi basic single-width (oif) cei phy interface sonet/sdh oc96 basic double-width data rate range in basic functional mode 0.6 gbps to 3.75 gbps 1 gbps to 8.5 gbps chapter 1: stratix iv transceiver architecture 1?15 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 table 1?7 lists the tx phase compensation fifo modes. f for more information about the tx phase compensation fifo, refer to the ?limitations of the quartus ii software-selected transmitter phase compensation fifo write clock? section of the stratix iv transceiver clocking chapter. input data in pci express (pipe) functional mode, the input data comes from the pci express (pipe) interface. in all other functional modes, the input data comes directly from the fpga fabric. output data destination block the output from the tx phase compensation fifo is used by the byte serializer block, 8b/10b encoder, or serializer block. table 1?8 lists the conditions under which the tx phase compensation fifo outputs are provided to these blocks. figure 1?9. tx phase compensation fifo data path from the fpga fabric or pipe interface tx_coreclk tx_clkout coreclkout data path to the byte serializer or the 8b/10b encoder or serializer tx phase compensation fifo wr_clk rd_clk tab le 1 ?7 . tx phase compensation fifo modes modes description low-latency the fifo is four words deep. latency through the fifo is two to three fpga fabric parallel clock cycles (pending characterization). the default setting for every mode. high-latency the fifo is eight words deep. the latency through the fifo is four to five fpga parallel cycles (pending characterization). non-bonded functional for example, in gige mode, the read port of the phase compensation fifo is clocked by the low-speed parallel clock. the write clock is fed by the tx_clkout port of the associated channel. bonded functional for example, in xaui mode, the write clock of the fifo is clocked by coreclkout provided by the cmu0 clock divider block. you can clock the write side using tx_coreclk provided from the fpga fabric by enabling the tx_coreclk port in the altgx megawizard plug-in manager. if you use this port, ensure that there is 0 parts-per-million (ppm) difference in frequency between the write and read side. the quartus ? ii software requires that you provide a 0 ppm assignment in the assignment editor. 1?16 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation tx phase compensation fifo status signal an optional tx_phase_comp_fifo_error port is available in all functional modes to indicate a receiver phase compensation fifo overflow or under-run condition. the tx_phase_comp_fifo_error signal is asserted high when the tx phase compensation fifo either overflows or under-runs due to any frequency ppm difference between the fifo read and write clocks. if the tx_phase_comp_fifo_error flag is asserted, verify the fpga fabric-transceiver interface clocking to ensure that there is 0 ppm difference between the tx phase compensation fifo read and write clocks. byte serializer the byte serializer divides the input datapath by two. this allows you to run the transceiver channel at higher data rates while keeping the fpga fabric interface frequency within the maximum limit stated in the ?interface frequency? section in the dc and switching characteristics chapter. in single-width mode, it converts the two-byte-wide datapath to a one-byte-wide datapath. in double-width mode, it converts the four-byte-wide datapath to a two-byte-wide datapath. it is optional in configurations that do not exceed the fpga fabric-transceiver interface maximum frequency limit. for example, if you want to run the transceiver channel at 6.25 gbps, without the byte serializer in double-width mode, the fpga fabric interface clock frequency must be 312.5 mhz (6.25/20). this violates the fpga fabric interface frequency limit. when you use the byte serializer, the fpga fabric interface frequency is 156.25 mhz (6.25g/40). you can enable the byte serializer in single-width or double-width mode. 1 the byte deserializer is required in configurations that exceed the fpga fabric-transceiver interface maximum frequency limit. f for more information about the maximum frequency limit for the transceiver interface, refer to the stratix iv device datasheet section . tab le 1 ?8 . output data destination block for the tx phase compensation fifo output data byte serializer 8b/10b encoder serializer if you select: single-width mode and channel width = 16 or 20 if you select: single-width mode and channel width = 8 and 8b/10b encoder enabled if you select: low-latency pcs bypass mode enabled or single-width mode and channel width = 8 or 10 if you select: double-width mode and channel width = 32 or 40 if you select: double-width mode and channel width = 16 and 8b/10b encoder enabled if you select: low-latency pcs bypass mode enabled or double-width mode and channel width = 16 or 20 chapter 1: stratix iv transceiver architecture 1?17 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 single-width mode figure 1?10 shows the byte serializer datapath in single-width mode. for data port width, refer to table 1?9 . the byte serializer forwards the lsbyte first, followed by the msbyte. the input data width to the byte serializer depends on the channel width option that you selected in the altgx megawizard plug-in manager. for example, in single-width mode, assuming a channel width of 20, the byte serializer sends out the least significant word datain[9:0] of the parallel data from the fpga fabric, followed by datain[19:10]. ta b l e 1 ?9 lists the input and output data widths of the byte serializer in single-width mode. figure 1?10. byte serializer datapath in single-width mode (note 1) , (2) notes to figure 1?10 : (1) for the datain[] and dataout[] port widths, refer to table 1?9. (2) the datain signal is the input from the fpga fabric that has already passed through the tx phase compensation fifo. tab le 1 ?9 . input and output data width of the byte serializer in single-width mode deserialization width input data width to the byte serializer output data width from the byte serializer single-width mode 16 8 20 10 /2 datain[] dataout[] low-speed parallel clock byte serializer 1?18 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation double-width mode figure 1?11 shows the byte serializer datapath in double-width mode. for data port width, refer to table 1?10 . the operation in double-width mode is similar to that of single-width mode. for example, assuming a channel width of 40, the byte serializer forwards datain[19:0] first, followed by datain[39:20]. table 1?10 lists the input and output data widths of the byte serializer in double-width mode. asserting the tx_digitalreset signal resets the byte serializer block. if you select the 8b/10b encoder option in the altgx megawizard plug-in manager, the 8b/10b encoder uses the output from the byte serializer. otherwise, the byte serializer output is forwarded to the serializer. figure 1?11. byte serializer datapath in double-width mode (note 1) , (2) notes to figure 1?11 : (1) for the datain[] and dataout[] port width, refer to table 1?10. (2) the datain signal is the input from the fpga fabric that has already passed through the tx phase compensation fifo. table 1?10. input and output data width of the byte serializer in double-width mode deserialization width input data width to the byte serializer output data width from the byte serializer double-width mode 32 16 40 20 /2 byte serializer datain[] dataout[] low-speed parallel clock chapter 1: stratix iv transceiver architecture 1?19 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 8b/10b encoder the 8b/10b encoder generates 10-bit code groups from the 8-bit data and 1-bit control identifier. the 8b/10b encoder operates in two modes: single-width and double-width. figure 1?12 shows the 8b/10b encoder in single-width and double-width mode. single-width mode the left side of figure 1?12 shows the 8b/10b encoder in single-width mode. in this mode, the 8b/10b encoder translates the 8-bit data to a 10-bit code group (control word or data word) with proper disparity. if the control_code input is high, the 8b/10b encoder translates the input data[7:0] to a 10-bit control word. if the control_code input is low, the 8b/10b encoder translates the input data[7:0] to a 10-bit data word. you can use the tx_forcedisp and tx_dispval ports to control the running disparity of the generated output data. for more information, refer to ?controlling running disparity? on page 1?23 . figure 1?12. 8b/10b encoder in single-width mode from the byte serializer datain[15:8] tx_forcedisp[1] tx_dispval[1] to the serializer dataout[19:10] 8b/10b encoder msb encoding lsb encoding dataout[9:0] datain[7:0] control_code[0] tx_forcedisp[0] tx_dispval[0] single width double width from the byte serializer to the serializer 8b/10b encoder datain[7:0] control_code tx_forcedisp tx_dispval dataout[9:0] control_code[1] 1?20 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?13 shows the conversion format. the lsb is transmitted first. control code encoding the altgx megawizard plug-in manager provides the tx_ctrlenable port to indicate whether the 8-bit data at the tx_datain port should be encoded as a control word (kx.y). when tx_ctrlenable is low, the 8b/10b encoder block encodes the byte at the tx_datain port (the user-input port) as data (dx.y). when tx_ctrlenable is high, the 8b/10b encoder encodes the input data as a kx.y code group. the waveform in figure 1?14 shows the second 0 bc encoded as a control word (k28.5). the rest of the tx_datain bytes are encoded as a data word (dx.y). the ieee 802.3 8b/10b encoder specification identifies only a set of 8-bit characters for which tx_ctrlenable should be asserted. if you assert tx_ctrlenable for any other set of bytes, the 8b/10b encoder might encode the output 10-bit code as an invalid code (it does not map to a valid dx.y or kx.y code), or unintended valid dx.y code, depending on the value entered. it is possible for a downstream 8b/10b decoder to decode an invalid control word into a valid dx.y code without asserting code error flags. figure 1?13. 8b/10b conversion format 7 6 5 4 3 2 1 0 hgf edcba 7 6 5 4 3 2 1 0 9 8 gf iedcba jh lsb msb control_code 8b/10b conversion figure 1?14. control word and data word transmission clock tx_datain[7:0] tx_ctrlenable code group 83 78 bc bc 0f 00 bf 3c d3.4 d24.3 d28.5 k28.5 d15.0 d0.0 d31.5 d28.1 chapter 1: stratix iv transceiver architecture 1?21 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 1 for example, depending on the current running disparity, the invalid code k24.1 ( tx_datain = 8'h38 + tx_ctrl = 1'b1) can be encoded to 10'b0110001100 (0 18c), which is equivalent to a d24.6+ (8'hd8 from the rd+ column). altera recommends that you do not assert tx_ctrlenable for unsupported 8-bit characters. reset condition the tx_digitalreset signal resets the 8b/10b encoder. during reset, running disparity and data registers are cleared. also, the 8b/10b encoder outputs a k28.5 pattern from the rd- column continuously until tx_digitalreset is de-asserted. the input data and control code from the fpga fabric is ignored during the reset state. after reset, the 8b/10b encoder starts with a negative disparity (rd-) and transmits three k28.5 code groups for synchronization before it starts encoding and transmitting the data on its output. 1 while tx_digitalreset is asserted, the downstream 8b/10b decoder that receives the data might observe synchronization or disparity errors. figure 1?15 shows the reset behavior of the 8b/10b encoder. when in reset ( tx_digitalreset is high), a k28.5- (k28.5 10-bit code group from the rd- column) is sent continuously until tx_digitalreset is low. due to some pipelining of the transmitter channel pcs, some ?don?t cares? (10'hxxx) are sent before the three synchronizing k28.5 code groups. user data follows the third k28.5 code group. double-width mode in double-width mode, the 8b/10b encoder operates in a cascaded mode, as shown on the right side of figure 1?15 on page 1?21 . the lsbyte of the input data is encoded and transmitted prior to the msbyte. in double-width mode, the cascaded 8b/10b encoder generates two 10-bit code groups from two 8-bit data and their respective control code identifiers. figure 1?16 shows the conversion format. the lsb shown in figure 1?16 is transmitted first. figure 1?15. 8b/10b encoder output during tx_digitalreset assertion clock tx_digitalreset dataout[9:0] k28.5- k28.5- k28.5- xxx ... k28.5- xxx k28.5- k28.5+ dx.y+ 1?22 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation control code encoding in double-width mode, the tx_ctrlenable[1:0] port is used to identify which 8-bit data is to be encoded as a control word. the lower bit, tx_ctrlenable[0] , is associated with the lsbyte; the upper bit, tx_ctrlenable[1] , is associated with the msbyte. when tx_ctrlenable is low, the byte at the tx_datain port of the transceiver is encoded as data (dx.y); otherwise, it is encoded as a control code (kx.y). figure 1?17 shows that only the lower byte of the tx_datain[15:0] port is encoded as a control code because tx_ctrlenable[0] is high in the second clock cycle. the 8b/10b encoder does not check to see if the code word entered is one of the 12 valid control code groups specified in the ieee 802.3 8b/10b encoder specification. if an invalid control code is entered, the resulting 10-bit code may be encoded as an invalid code (it does not map to a valid dx.y or kx.y code), or unintended valid dx.y code, depending on the value entered. the following is an example of an invalid control word encoded into a valid dx.y code. with an encoding invalid code k24.1 ( tx_datain = 8'h38 + tx_ctrl = 1'b1), depending on the current running disparity, the k24.1 can be encoded as 10'b0110001100 (0 18c), which is equivalent to a d24.6+ (8'hd8 from the rd+ column). an 8b/10b decoder can decode this and not assert a code error flag. figure 1?16. 8b/10b conversion format in double-width mode g' f' e' d' c' b' a' h' gf edcba h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb msb g' f' i' e' d' c' b' a' j' h ' g f i e d c b a jh 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ctrl[1:0] parallel data cascaded 8b/10b conversion figure 1?17. encoded control word and data word transmission clock tx_datain[15:0] tx_ctrlenable[1:0] code group 8378 bcbc 0f00 bf3c 00 1 d3.4 d24.3 d28.5 k28.5 d15.0 d0.0 d31.5 d28.1 chapter 1: stratix iv transceiver architecture 1?23 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 1 altera does not recommend sending invalid control words to the 8b/10b encoder. reset condition the tx_digitalreset signal resets the 8b/10b encoder. during reset, the running disparity and data registers are cleared. also, the 8b/10b encoder outputs a k28.5 pattern with proper disparity continuously until tx_digitalreset goes low. the inputs from the tx_datain and tx_ctrlenable ports are ignored during the reset state. after reset, the 8b/10b encoder starts the lsbyte with a negative disparity (rd-) and the msbyte with a positive disparity (rd+) and transmits six k28.5 code groups (three on the lsbyte and three on the msbyte encoder) for synchronizing before it starts encoding and transmitting data. 1 if the tx_digitalreset signal is asserted, the downstream 8b/10b decoder receiving the data might get synchronization or disparity errors. figure 1?18 shows the reset behavior of the 8b/10b encoder. when in reset ( tx_digitalreset is high), a k28.5- on lsb and k28.5+ on msb is sent continuously until tx_digitalreset is low. due to pipelining of the tx channel, there will be some ?don?t cares? (10'hxxx) until the first k28.5 is sent ( figure 1?18 shows six ?don?t cares?, but the number of ?don?t cares? can vary). both the lsbyte and msbyte transmit three k28.5s before the data at the tx_datain port is encoded and sent out. controlling running disparity after power on or reset, the 8b/10b encoder has a negative disparity and chooses the 10-bit code from the rd- column (refer to the 8b/10b encoder specification for the rd+ and rd- column values). the altgx megawizard plug-in manager provides the tx_forcedisp and tx_dispval ports to control the running disparity of the output from the 8b/10b encoder. these ports are available only in basic single-width and basic double-width modes. a high value on the tx_forcedisp port is the control signal to the disparity value of the output data. the disparity value (rd+ or rd-) is indicated by the value on the tx_dispval port. if the tx_forcedisp port is low, tx_dispval is ignored and the current running disparity is not altered. forcing disparity can either maintain the current running disparity calculations if the forced disparity value (on the tx_dispval bit) matches the current running disparity, or flip the current running disparity calculations if it does not. if the forced disparity flips the current running disparity, the downstream 8b/10b decoder might detect a disparity error. table 1?11 shows the tx_forcedisp and tx_dispval port values. figure 1?18. transmitted output data when tx_digitalreset is asserted clock tx_digitalreset dataout[19:10] dataout[9:0] k28.5+ k28.5+ k28.5+ xxx xxx xxx k28.5+ k28.5+ k28.5+ dx.y+ k28.5- k28.5- k28.5- dx.y- xxx xxx xxx k28.5- k28.5- k28.5- 1?24 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?19 shows the current running disparity being altered in basic single-width mode by forcing a positive disparity k28.5 when it was supposed to be a negative disparity k28.5. in this example, a series of k28.5 code groups are continuously being sent. the stream alternates between a positive running disparity (rd+) k28.5 and a negative running disparity (rd-) k28.5 to maintain a neutral overall disparity. the current running disparity at time n + 3 indicates that the k28.5 in time n + 4 should be encoded with a negative disparity. because tx_forcedisp is high at time n + 4, and tx_dispval is low, the k28.5 at time n + 4 is encoded as a positive disparity code group. figure 1?20 shows the current running disparity being altered in basic double-width mode by forcing a positive disparity on a negative disparity k28.5. in this example, a series of k28.5 are continuously being sent. the stream alternates between a positive ending running disparity (rd+) k28.5 and a negative ending running disparity (rd-) k28.5 as governed by the 8b/10b encoder specification to maintain a neutral overall disparity. the current running disparity at the end of time n + 2 indicates that the k28.5 at the low byte position in time n + 4 should be encoded with a positive disparity. because tx_forcedisp is high at time n + 4, the low signal level of tx_dispval is used to convert the lower byte k28.5 to be encoded as a positive disparity code word. as the upper bit of tx_forcedisp is low at n + 4, the high byte k28.5 takes the current running disparity from the low byte. table 1?11. tx_forcedisp and tx_dispval port values tx_forcedisp tx_dispval disparity value 0 x current running disparity has no change 1 0 encoded data has positive disparity 1 1 encoded data has negative disparity figure 1?19. 8b/10b encoder force running disparity operation in single-width mode current running disparity clock tx_in[7:0] tx_forcedisp bc bc bc bc bc bc bc tx_ctrlenable bc dataout[9:0] 17c 283 17c 283 283 283 17c 17c rd- rd+ rd+ rd- rd+ rd- rd+ rd- n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 tx_dispval chapter 1: stratix iv transceiver architecture 1?25 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 transmitter polarity inversion the positive and negative signals of a serial differential link might accidentally be swapped during board layout. solutions like a board re-spin or major updates to the logic in the fpga fabric can be expensive. the transmitter polarity inversion feature is provided to correct this situation. an optional tx_invpolarity port is available in all functional modes except (oif) cei phy to dynamically enable the transmitter polarity inversion feature. in single-width mode, a high value on the tx_invpolarity port inverts the polarity of every bit of the 8-bit or 10-bit input data word to the serializer in the transmitter datapath. in double-width mode, a high value on the tx_invpolarity port inverts the polarity of every bit of the 16-bit or 20-bit input data word to the serializer in the transmitter datapath. because inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is seen by the receiver. tx_invpolarity is a dynamic signal and might cause initial disparity errors at the receiver of an 8b/10b encoded link. the downstream system must be able to tolerate these disparity errors. figure 1?20. 8b/10b encoder force current running disparity in double-width mode current running disparity clock bc bc bc bc bc bc bc bc tx_dataout[19:0] 17c 283 17c 283 283 283 17c 17c rd - rd + rd + rd - rd+ rd- rd+ rd- n 01 00 00 00 tx_datain[15:0] tx_ctrlenable[1:0] tx_forcedisp[1:0] tx_dispval[1:0] 11 n + 2 n + 4 1?26 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?21 shows the transmitter polarity inversion feature in a single-width and double-width datapath configuration. figure 1?21. transmitter polarity inversion in single-width and double-width mode 0 1 1 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 1 0 0 0 1 0 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 lsb lsb msb msb tx_invpolarity = high tx_invpolarity = high single-width configuration output from tr ansmitter pcs con verted data output to the transmitter serializer double-width configuration chapter 1: stratix iv transceiver architecture 1?27 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 transmitter bit reversal table 1?12 shows the transmission bit order with and without the transmitter bit reversal enabled. figure 1?22 shows the transmitter bit reversal feature in basic single-width for a 10-bit wide datapath configuration. table 1?12. transmission bit order for the bit reversal feature transmitter bit reversal feature single-width mode (8- or 10-bit) double-width mode (16- or 20-bit) not enabled (default) lsb to msb lsb to msb enabled msb to lsb for example: 8-bit? d[7:0] rewired to d[0:7] 10-bit? d[9:0] rewired to d[0:9] msb to lsb for example: 16-bit? d[15:0] rewired to d[0:15] 20-bit? d[19:0] rewired to d[0:19] figure 1?22. transmitter bit reversal operation in basic single-width mode output from transmitter pcs converted data output to the transmitter serializer tx bit reversal option enabled in the altgx megawizard d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] d[8] d[9] 1?28 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?23 shows the transmitter bit reversal feature in basic double-width mode for a 20-bit wide datapath configuration. serializer the serializer converts the incoming low-speed parallel signal from the transceiver pcs to high-speed serial data and sends it to the transmitter buffer. the serializer supports an 8-bit or 10-bit serialization factor in single-width mode and a 16-bit or 20-bit serialization factor in double-width mode. the serializer block drives the serial data to the output buffer, as shown in figure 1?24 . the serializer block sends out the lsb of the input data. figure 1?23. transmitter bit reversal operation in basic double-width mode output from transmitter pcs converted data output to the transmitter serializer d[0] d[2] d[1] d[4] d[3] d[6] d[5] d[8] d[7] d[10] d[9] d[12] d[11] d[15] d[13] d[14] d[17] d[16] d[19] d[18] d[18] d[19] d[16] d[17] d[15] d[13] d[14] d[11] d[12] d[9] d[10] d[7] d[8] d[5] d[6] d[3] d[4] d[1] d[2] d[0] tx bit reversal option enabled in the altgx megawizard chapter 1: stratix iv transceiver architecture 1?29 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?25 shows the serial bit order of the serializer block output. in this example, a constant 8'h6a (01101010) value is serialized and the serial data is transmitted from lsb to msb. figure 1?24. serializer block in 8-bit pcs-pma interface note to figure 1?24 : (1) the cmu0 clock divider of the master transceiver block provides the cl ocks. it is used only in bonded modes (for example, basic 8, pci express [pipe] 8 mode). d7 d6 d5 d4 d3 d2 d1 d0 8 d7 d6 d5 d4 d3 d2 d1 d0 to output buffer low-speed parallel clock high-speed serial clock parallel clock from local divider block parallel clock from cmu0 clock divider parallel clock from master transceiver block (1) serial clock from local divider block serial clock from cmu0 clock divider serial clock from master transceiver block (1) figure 1?25. serializer bit order (note 1) note to figure 1?25 : (1) it is assumed that the input data to the serializer is 8 bits (channel width = 8 bits or 16 bits with the 8b/10b encoder disabled). low-speed parallel clock 01101010 01 0 0 0 11 1 00000000 high-speed serial clock tx_datain[7..0] tx_dataout[0] 1?30 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation transmitter output buffer the stratix iv gx and gt transmitter buffers are architecturally similar to each other. they both support programmable output differential voltage (v od ), pre-emphasis, and on-chip termination (oct) settings. the transmitter buffer power supply only provides voltage to the transmitter output buffers in the transceiver channels. the transmitter output buffer, shown in figure 1?26 , has additional circuitry to improve signal integrity, such as v od , programmable three-tap pre-emphasis circuit, internal termination circuitry, and receiver detect capability to support pci express (pipe) functional mode. table 1?13 and table 1?14 list the supported settings of the transmitter buffers in the stratix iv gx and gt devices, respectively. figure 1?26. transmitter output buffer table 1?13. supported settings for the stratix iv gx and gt transmitter buffer parameter setting data rate 600 mbps to 8.5 gbps (1.4 v) 600 mbps to 6.5 gbps (1.5 v) transmitter buffer power ( v cch_gxbl/rn ) 1.4 v or 1.5 v transmitter buffer i/o standard 1.4-v and 1.5-v pseudo current mode logic (pcml) transmitter buffer v cm 0.65 v table 1?14. supported settings for the stratix iv gt transmitter buffer parameter setting data rate 2.488 gbps?11.3 gbps transmitter buffer power ( v cch_gxbl/rn )1 . 4 v transmitter buffer i/o standard 1.4-v pcml transmitter buffer v cm 0.65 v 50 ?? , 60 , 75 transmitter output pins programmable pre-emphasis and v od +vtt- receiver detect 42.5, 50 ? , 60 , 75 42.5, chapter 1: stratix iv transceiver architecture 1?31 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 programmable transmitter termination the stratix iv gx and gt transmitter buffers includes programmable on-chip differential termination of 85, 100, 120, or 150 . the resistance is adjusted by the on-chip calibration circuit in the calibration block (for more information, refer to ?calibration blocks? on page 1?199 ), which compensates for temperature, voltage, and process changes. the stratix iv gx and gt transmitter buffers in the transceiver are current mode drivers. therefore, the resultant v od is a function of the transmitter termination value. for more information about resultant v od values, refer to ?programmable output differential voltage? on page 1?31 . you can disable oct and use external termination. if you select external termination, the transmitter common mode is tri-stated. you can set the transmitter termination in the altgx megawizard plug-in manager. you can also set the oct through the assignment editor. set the assignment shown in table 1?15 to the transmitter serial output pin. programmable output differential voltage the stratix iv gx and gt devices allow you to customize the differential output voltage to handle different trace lengths, various backplanes, and receiver requirements, as shown in figure 1?27 . you can change the v od values using the dynamic reconfiguration controller. set the v od value through the tx_vodctrl[2:0] port of the dynamic reconfiguration controller. for example, to set v od to a value of 3, set the tx_vodctrl[2:0] to 011. f for more information about stratix iv gx and gt v od values, refer to the dc and switching characteristics chapter. table 1?15. stratix iv gx and gt oct assignment settings assign to transmitter serial output data pin assignment name output termination available values oct 85 , oct 100 , oct 120 , oct 150 figure 1?27. v od (differential) signal level single-ended waveform differential waveform v a v b +v od +v od -v od v od (differential) 0-v differential +700 -700 - v od (differential) = v a ? v b 1?32 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation programmable pre-emphasis the programmable pre-emphasis module in each transmit buffer boosts high frequencies in the transmit data signal, which might be attenuated in the transmission media. using pre-emphasis can maximize the data opening at the far-end receiver. the transmission line?s transfer function can be represented in the frequency domain as a low-pass filter. any frequency components below ?3db can pass through with minimal loss. frequency components greater than ?3db are attenuated. this variation in frequency response yields data-dependent jitter and other inter-symbol interference (isi) effects. by applying pre-emphasis, the high-frequency components are boosted; that is, pre-emphasized. pre-emphasis equalizes the frequency response at the receiver so the difference between the low-frequency and high-frequency components is reduced, which minimizes the isi effects from the transmission medium. pre-emphasis requirements increase as data rates through legacy backplanes increase. you set the pre-emphasis settings in the altgx megawizard plug-in manager. the stratix iv gx and gt transceivers provide three pre-emphasis taps?pre tap, first post tap, and second post tap. the altgx megawizard plug-in manager provides options to select the different values on these three taps. the pre tap sets the pre-emphasis on the data bit before the transition. the first post tap and second post tap set the pre-emphasis on the transition bit and the successive bit, respectively. the pre tap and second post tap also provide inversion control, shown by negative values on the corresponding tap settings in the altgx megawizard plug-in manager. the altgx megawizard plug-in manager only shows the valid pre-emphasis tap values for a selected v od and transmitter termination resistance setting. programmable transmitter output buffer power (v cch ) the altgx megawizard plug-in manager provides an option to select v cch . table 1?16 lists the data rates for the two v cch options. link coupling for stratix iv gx and gt devices a high-speed serial link can be ac-coupled or dc-coupled, depending on the serial protocol being implemented. ac-coupled links in an ac-coupled link, the ac-coupling capacitor blocks the transmitter dc v cm . the on-chip or off-chip receiver termination and biasing circuitry automatically restores the selected v cm . figure 1?28 shows an ac-coupled link. table 1?16. v cch option data rates v cch options stratix iv gx data rate stratix iv gt data rate 1.4 v 600 mbps to 8.5 gbps 2.488 gbps to 11.3 gbps 1.5 v 600 mbps to 6.5 gbps ? chapter 1: stratix iv transceiver architecture 1?33 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 the following protocols supported by stratix iv gx and gt devices mandate ac-coupled links: pci express (pipe) gigabit ethernet serial rapidio xaui sdi stratix iv gt devices allow the high-speed links to be ac-coupled for the entire data rate range between 2.488 gbps and 11.3 gbps. dc-coupled links in a dc-coupled link, the transmitter dc v cm is seen unblocked at the receiver buffer. the link v cm depends on the transmitter v cm and the receiver v cm . the on-chip or off-chip receiver termination and biasing circuitry must ensure compatibility between the transmitter and receiver v cm . figure 1?29 shows a dc-coupled link. figure 1?28. ac-coupled link physical medium transmitter receiver tx v cm rx v cm tx termination rx termination ac coupling capacitor ac coupling capacitor physical medium 1?34 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the stratix iv gx and gt transmitter can be dc-coupled to a stratix iv gx and gt receiver for the entire operating data rate range of stratix iv gx, from 600 mbps to 8.5 gbps. the stratix iv gt transmitter can be dc-coupled to the stratix iv gt receiver for the entire data rate range of 2.488 gbps to 11.3 gbps with tx vcm = 0.65 v and rx vcm = 0.82 v. for more information on the dc coupling capabilities of the stratix iv gt device, refer to table 1?23 on page 1?44 . pci express (pipe) receiver detect the stratix iv gx and gt transmitter buffers have a built-in receiver detection circuit for use in the pci express (pipe) mode for gen1 and gen2 data rates. this circuit detects if there is a receiver downstream by sending out a pulse on the common mode of the transmitter and monitoring the reflection. this mode requires the transmitter buffer to be tri-stated (in electrical idle mode), oct utilization, and a 125 mhz fixedclk signal. you can enable this feature in pci express (pipe) mode by setting the tx_forceelecidle and tx_detectrxloopback ports to 1'b1 . receiver detect circuitry is active only in the p1 power state. f for more information about power states, refer to the pci express (pipe) 2.0 specification. in the p1 power state, the transmitter output buffer is tri-stated because the transmitter output buffer is in electrical idle. a high on the tx_detectrxloopback port triggers the receiver detect circuitry to alter the transmitter output buffer v cm . the sudden change in v cm effectively appears as a step voltage at the tri-stated transmitter buffer output. if a receiver (that complies with pci express [pipe] input impedance requirements) is present at the far end, the time constant of the step voltage is higher. if a receiver is not present or is powered down, the time constant of the step voltage is lower. the receiver detect circuitry snoops the transmitter buffer output for the time constant of the step voltage to detect the presence of the receiver at figure 1?29. dc-coupled link physical medium transmitter receiver tx v cm rx v cm tx termination rx termination physical medium chapter 1: stratix iv transceiver architecture 1?35 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 the far end. a high pulse is driven on the pipephydonestatus port and 3'b011 is driven on the pipestatus port to indicate that a receiver has been detected. there is some latency after asserting the tx_detectrxloopback signal, before the receiver detection is indicated on the pipephydonestatus port. for signal timing to perform the receiver detect operation, refer to figure 1?105 on page 1?131 . 1 the tx_forceelecidle port must be asserted at least 10 parallel clock cycles prior to the tx_detectrxloopback port to ensure that the transmitter buffer is tri-stated. pci express (pipe) electrical idle the stratix iv gx and gt transmitter output buffers support transmission of pci express (pipe) electrical idle (or individual transmitter tri-state). the tx_forceelecidle port puts the transmitter buffer in electrical idle mode. this port has a specific functionality in each power state. for the signal timing to perform the electrical idle transmission in pci express (pipe) mode, refer to figure 1?104 on page 1?130 . f for more information about using the tx_forceelecidle signal under different power states, refer to the pci express (pipe) specification 2.0. transmitter local clock divider block each transmitter channel contains a local clock divider block. it receives the high-speed clock from the cmu0 pll or cmu1 pll and generates the high-speed serial clock for the serializer and the low-speed parallel clock for the transmitter pcs datapath. the low-speed parallel clock is also forwarded to the fpga fabric ( tx_clkout ). the local clock divider block allows each transmitter channel to run at /1, /2, or /4 of the cmu pll data rate. the local clock divider block is used only in non-bonded functional modes (for example, gige, sonet/sdh, and sdi mode). figure 1?30 shows the transmitter local clock divider block. figure 1?30. transmitter local clock divider block 4, 5, 8, or 10 high-speed serial cloc k low-speed parallel clock cmu0 pll high-speed clock cmu1 pll high-speed clock 1, 2, or 4 n 1?36 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation receiver channel datapath this section describes the stratix iv gx and gt receiver channel datapath architecture. the sub-blocks in the receiver datapath are described in order from the serial receiver input buffer to the receiver phase compensation fifo buffer at the fpga fabric-transceiver interface. figure 1?7 on page 1?12 shows the receiver channel datapath in stratix iv gx and gt devices. the receiver channel pma datapath consists of the following blocks: receiver input buffer clock and data recovery (cdr) unit deserializer the receiver channel pcs datapath consists of the following blocks: word aligner deskew fifo rate match (clock rate compensation) fifo 8b/10b decoder byte deserializer byte ordering receiver phase compensation fifo pci express (pipe) interface the receiver datapath is very flexible and allows multiple configurations, depending on the selected functional mode. you can configure the receiver datapath using the altgx megawizard plug-in manager. receiver input buffer the stratix iv gx and gt receiver input buffers are architecturally similar to each other. they both support programmable common mode voltage (rx vcm), equalization, dc gain, and on-chip termination (oct) settings. table 1?17 lists the supported settings of the receiver input buffers in stratix iv gx and gt devices. the receiver input buffer receives serial data from the rx_datain port and feeds it to the cdr unit. in the reverse serial loopback (pre-cdr) configuration, it also feeds the received serial data to the transmitter output buffer. figure 1?31 shows the receiver input buffer. chapter 1: stratix iv transceiver architecture 1?37 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 table 1?17 shows the electrical features supported by the stratix iv gx and gt receiver input buffer. the stratix iv gx and gt receiver buffers support the following features: programmable differential oct programmable v cm ac and dc coupling programmable equalization and dc gain signal threshold detection circuitry figure 1?31. receiver input buffer rx vcm to cdr receiver input buffer signal detect from serial data input pins (rx_datain) 85/100/ 120/150- 0.82/1.1-v equalization and dc gain circuitry signal threshold detection circuitry to the transmitter output buffer in the reverse serial loopback (pre-cdr) configuration table 1?17. electrical features supported by the receiver input buffer for stratix iv gx and gt devices (note 1) data rate (gbps) i/o standard differential oct with calibration ( )v cm (v) coupling programmable dc gain (db) stratix iv gx 0.6 to 8.5 1.4 v pcml 85, 100, 120, 150 0.82 ac, dc up to 16 1.5 v pcml 85, 100, 120, 150 0.82 ac, dc up to 16 2.5 v pcml 85, 100, 120, 150 0.82 ac up to 16 lvpecl 85, 100, 120, 150 0.82 ac up to 16 lvds 85, 100, 120, 150 1.1 ac, dc up to 16 stratix iv gt 2.488 to 11.3 1.4 v pcml 85, 100, 120, 150 0.82 ac, dc 0, 3, 6, 9, and 12 lvds 85, 100, 120, 150 1.1 ac, dc 0, 3, 6, 9, and 12 note to tab l e 1 ?1 7 : (1) programmable equalization settings are 0 to 16 db for stratix iv gx and gt devices. 1?38 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation programmable differential on-chip termination the stratix iv gx and gt receiver buffers support optional differential oct resistors of 85, 100, 120, and 150 . to select the desired receiver oct resistor, make the assignments shown in table 1?18 in the quartus ii software assignment editor. 1 the stratix iv gx and gt receiver oct resistors have calibration support to compensate for process, voltage, and temperature variations. for more information about oct calibration support, refer to ?calibration blocks? on page 1?199 . programmable v cm the stratix iv gx and gt receiver buffers have on-chip biasing circuitry to establish the required v cm at the receiver input. it supports v cm settings of 0.82 v and 1.1 v that you can select in the altgx megawizard plug-in manager. you must select 0.82 v as the receiver buffer v cm for the following receiver input buffer i/o standards: 1.4-v pcml 1.5-v pcml 2.5-v pcml lv p e c l yo u mu s t se l ec t 1.1 v as the receiver buffer v cm for the lvds receiver input buffer i/o standard. 1 on-chip biasing circuitry is effective only if you select on-chip receiver termination . if you select external termination , you must implement off-chip biasing circuitry to establish the v cm at the receiver input buffer. link coupling for stratix iv gx devices a high-speed serial link can either be ac-coupled or dc-coupled, depending on the serial protocol being implemented. most of the serial protocols require links to be ac-coupled, but protocols such as common electrical i/o (cei) optionally allow dc coupling. table 1?18. stratix iv gx and gt receiver on-chip termination assignment settings assign to rx_datain (receiver input data pins) assignment name input termination stratix iv gx available values oct 85 , oct 100 , oct 120 , oct 150 , off stratix iv gt available values oct 85 ,oct 100 , oct 120 , oct 150 chapter 1: stratix iv transceiver architecture 1?39 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 ac-coupled links in an ac-coupled link, the ac coupling capacitor blocks the transmitter dc v cm . the on-chip or off-chip receiver termination and biasing circuitry automatically restores the selected v cm . figure 1?32 shows an ac-coupled link. the following protocols supported by stratix iv gx and gt devices mandate ac-coupled links: pci express (pipe) gigabit ethernet serial rapidio xaui sdi figure 1?32. ac-coupled link note to figure 1?32 : (1) the receiver termination and biasing can be on-chip or off-chip. physical medium transmitter receiver tx v cm rx v cm tx termination rx termination ac coupling capacitor ac coupling capacitor physical medium 1?40 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation dc-coupled links in a dc-coupled link, the transmitter dc v cm is seen unblocked at the receiver buffer. link v cm depends on the transmitter v cm and the receiver v cm . the on-chip or off-chip receiver termination and biasing circuitry must ensure compatibility between the transmitter and the receiver v cm . figure 1?33 shows a dc-coupled link. you might choose to use the dc-coupled high-speed link for these functional modes only: basic single- and double-width (oif) cei phy interface the following sections describe dc-coupling requirements for a high-speed link with a stratix iv gx device used as the transmitter, receiver, or both. specifically, the following link configurations are described: stratix iv gx transmitter (pcml) to stratix iv gx receiver (pcml) stratix ii gx transmitter (pcml) to stratix iv gx receiver (pcml) stratix iv gx transmitter (pcml) to stratix ii gx receiver (pcml) lvds transmitter to stratix iv gx receiver (pcml) figure 1?33. dc-coupled link note to figure 1?33 : (1) the receiver termination and biasing can be on-chip or off-chip. physical medium transmitter receiver tx v cm rx v cm tx termination rx termination physical medium chapter 1: stratix iv transceiver architecture 1?41 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?34 shows a typical stratix iv gx transmitter (pcml) to stratix iv gx receiver (pcml) dc-coupled link. table 1?19 shows the allowed transmitter and receiver settings in a stratix iv gx transmitter (pcml) to stratix iv gx receiver (pcml) dc-coupled link. figure 1?34. stratix iv gx transmitter (pcml) to stratix iv gx receiver (pcml) note to figure 1?34 : (1) r s is the parasitic resistance present in the on-chip rx termination and biasing circuitry. physical medium stratix iv gx receiver tx v cm rx v cm v cch = 1.4 v/1.5 v stratix iv gx transmitter 42.5/50/60/75- tx termination 0.65 v 0.82 v r s 42.5/50/60/75- tx termination 42.5/50/60/75- rx termination 42.5/50/60/75- rx termination physical medium (1) table 1?19. settings for a stratix iv gx transmitter (pcml) to stratix iv gx receiver (pcml) dc-coupled link transmitter (stratix iv gx) settings receiver (stratix iv gx) settings data rate v cch (1) tx v cm differential termination data rate rx v cm differential termination 600-8500 mbps 1.4 v/1.5 v 0.65 v 85/100/120/150 600-8500 mbps 0.82 v 85/100/120/150 note to tab l e 1 ?1 9 : (1) v cch = 1.5 v can support data rates from 600 mbps to 6.5g mbps. v cch = 1.4 v can support data rates from 600 mbps to 8500 mbps. 1?42 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?35 shows the stratix ii gx transmitter (pcml) to stratix iv gx receiver (pcml) coupled link. table 1?20 shows the allowed transmitter and receiver settings in a stratix ii gx to stratix iv gx dc-coupled link. figure 1?35. stratix ii gx transmitter (pcml) to stratix iv gx receiver (pcml) note to figure 1?35 : (1) r s is the parasitic resistance present in the on-chip rx termination and biasing circuitry. physical medium stratix iv gx receiver tx v cm rx v cm v cch = 1.2 v/1.5 v stratix ii gx transmitter 50/60/75- tx termination 50/60/75- tx termination 0.6 v/0.7 v 42.5/50/60/75- rx termination 0.82 v r s 42.5/50/60/75- rx termination (1) physical medium table 1?20. settings for a stratix ii gx to stratix iv gx dc-coupled link transmitter (stratix ii gx) settings receiver (stratix iv gx) settings data rate v cch (1) tx v cm (1) differential termination data rate rx v cm differential termination 600-6375 mbps 1.5 v (1.5 v pcml) 0.6 v/0.7 v 100/120/150 600-6375 mbps 0.82 v 100/120/150 note to tab l e 1 ?2 0 : (1) v cch = 1.5 v with tx v cm = 0.7 v can support data rates from 600 mbps to 3125 mbps. v cch = 1.5 v with tx v cm = 0.6 v can support data rates from 600 mbps to 6375 mbps. chapter 1: stratix iv transceiver architecture 1?43 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?36 shows the stratix iv gx transmitter (pcml) to stratix ii gx receiver (pcml) dc-coupled link. table 1?21 shows the allowed transmitter and receiver settings in a stratix iv gx transmitter (pcml) to stratix ii gx receiver (pcml) dc-coupled link. figure 1?36. stratix iv gx transmitter (pcml) to stratix ii gx receiver (pcml) note to figure 1?36 : (1) r s is the parasitic resistance present in the on-chip rx termination and biasing circuitry. physical medium stratix ii gx receiver tx v cm rx v cm 50/60/75- rx termination v cch = 1.4/1.5 v stratix iv gx transmitter 42.5/50/60/75- tx termination 0.65 v 50/60/75- rx termination 0.85 v r s 42.5/50/60/75- tx termination physical medium (1) table 1?21. settings for a stratix iv gx to stratix ii gx dc-coupled link transmitter (stratix iv gx) settings receiver (stratix ii gx) settings data rate v cch (1) tx v cm differential termination data rate i/o standard rx v cm differential te rmin ati on 600-6375 mbps 1.4/1.5 v 0.65 v 100/120/150 600-6375 mbps 1.4/1.5 v pcml 0.85 v 100/120/150 note to tab l e 1 ?2 1 : (1) v cch = 1.5 v can support data rates from 600 mbps to 6.5g mbps. v cch = 1.4 v can support data rates from 600 mbps to 6375 mbps. 1?44 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?37 shows the lvds transmitter to stratix iv gx receiver (pcml) dc-coupled link. table 1?22 shows the allowed transmitter and receiver settings in a lvds transmitter to stratix iv gx receiver dc-coupled link. link coupling for stratix iv gt devices stratix iv gt devices allow the high-speed links to be ac- or dc-coupled links (ac-coupling allowed for the entire data rate range between 2.488 gbps and 11.3 gbps). table 1?23 lists the allowed dc-coupling scenarios for stratix iv gt devices. figure 1?37. lvds transmitter to stratix iv gx receiver (pcml) note to figure 1?37 : (1) r s is the parasitic resistance present in the on-chip rx termination and biasing circuitry. table 1?22. settings for a lvds transmitter to stratix iv gx receiver dc-coupled link (note 1) receiver (stratix iv gx) settings rx v cm differential termination r s 1.1 v 100 (2) notes to ta bl e 1? 22 : (1) when dc-coupling an lvds transmitter to the stratix iv gx receiver, use rx v cm = 1.1 v and series resistance value rs to verify compliance with the lvds specification. (2) pending characterization. physical medium (1) stratix iv gx receiver rx v cm lvds transmitter 50- rx termination 1.1 v r s 50- rx termination physical medium table 1?23. allowed dc-coupling scenarios for stratix iv gt devices (part 1 of 2) from (transmitter i/o standard) to (receiver i/o standard) data rate range conditions stratix iv gt transmitter (1.4-v pcml) stratix iv gt receiver (1.4-v pcml) 2.488 gbps to 11.3 gbps tx v cm = 0.65 v rx v cm = 0.82 v stratix iv gx transmitter (1.4-v pcml) stratix iv gt receiver (1.4-v pcml) 2.488 gbps to 8.5 gbps tx v cm = 0.65 v rx v cm = 0.82 v chapter 1: stratix iv transceiver architecture 1?45 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 programmable equalization and dc gain the transfer function of the physical medium can be represented as a low-pass filter in the frequency domain. frequency components below ?3 db frequency pass through with minimal loss. frequency components greater than ?3 db frequency are attenuated as a function of frequency due to skin-effect and dielectric losses. this variation in frequency response yields data-dependent jitter and other isi effects, which can cause incorrect sampling of the input data. each stratix iv gx and gt receiver buffer has independently programmable equalization circuitry that boosts the high-frequency gain of the incoming signal, thereby compensating for the low-pass filter effects of the physical medium. the amount of high-frequency gain required depends on the loss characteristics of the physical medium. stratix iv gx and gt equalization circuitry supports 16 equalization settings that provide up to 16 db of high-frequency boost. you can select the appropriate equalization setting in the altgx megawizard plug-in manager. stratix iv gx and gt receiver buffers also support programmable dc gain circuitry. unlike equalization circuitry, dc gain circuitry provides equal boost to the incoming signal across the frequency spectrum. the receiver buffer supports dc gain settings of 0, 3, 6, 9, and 12 db. you can select the appropriate dc gain setting in the altgx megawizard plug-in manager. signal threshold detection circuitry in pci express (pipe) mode, you can enable the optional signal threshold detection circuitry by not selecting the force signal detection option in the altgx megawizard plug-in manager. if enabled, this option senses whether the signal level present at the receiver input buffer is above the signal detect threshold voltage that you specified in the what is the signal detect and signal loss threshold? option in the altgx megawizard plug-in manager. 1 the appropriate signal detect threshold level that complies with the pci express (pipe) compliance parameter vrx-idle-detdiffp-p is available in the dc and switching characteristics chapter. signal threshold detection circuitry has a hysteresis response that filters out any high-frequency ringing caused by inter-symbol interference or high-frequency losses in the transmission medium. if the signal threshold detection circuitry senses the signal level present at the receiver input buffer to be higher than the signal detect threshold, it asserts the rx_signaldetect signal high. otherwise, the signal threshold detection circuitry de-asserts the rx_signaldetect signal low. stratix ii gx transmitter (1.5-v pcml) stratix iv gt receiver (1.4-v pcml) 2.488 gbps to 6.375 gbps tx v cm = 0.7 v (2.488 gbps to 3.125 gbps) tx v cm = 0.6 v (3.125 gbps to 6.375 gbps) rx v cm = 0.82 v third-party lvds transmitter stratix iv gt receiver (lvds) 2.488 gbps to 6.5 gbps rx v cm = 1.1 v table 1?23. allowed dc-coupling scenarios for stratix iv gt devices (part 2 of 2) from (transmitter i/o standard) to (receiver i/o standard) data rate range conditions 1?46 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation adaptive equalization (aeq) stratix iv gx and gt receivers offer an adaptive equalization feature that automatically compensates for losses on the receiver channels. high-speed interface systems are used at different data rates with multiple backplane environments. these systems require different equalization settings to compensate for changing data rates and back plane characteristics. manually selecting optimal equalization settings is cumbersome under these changing system characteristics. the adaptive equalization feature solves this problem by enabling the stratix iv device to continuously tune the receiver equalization settings based on the frequency content of the incoming signal and comparing it with internally generated reference signals. without this feature, you would have to tune the receiver channel?s equalization stages manually, finding the optimal settings through trial and error, then locking in those values at compile time. the aeq block resides within the pma of the receiver channel and is available on the four regular channels of a transceiver block. to use aeq, you must first enable the aeq hardware in the altgx megawizard plug-in manager and the aeq control block in the altgx_reconfig megawizard plug-in manager. to enable the aeq feature, in altgx and altgx_reconfig megawizard plug-in managers, select the enable adaptive equalizer control option. when you select aeq, two ports, aeq_fromgxb[] and aeq_togxb[] , become available on the altgx and altgx_reconfig instances. these ports provide an interface between the pma of the receiver channel and the aeq control block in the altgx_reconfig megawizard plug-in manager. 1 aeq hardware is not present in the cmu channels. chapter 1: stratix iv transceiver architecture 1?47 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?38 shows the receiver channel data path with the aeq feature. modes of operation of the aeq depending on the value you set for reconfig_mode_sel[3:0] , the aeq has three modes of operation: continuous mode?the aeq continuously monitors the frequency content of the received signal and adapts to it by providing dynamically changing equalizer settings to the stratix iv gx and gt receiver. this mode is available on one channel or all channels of the receiver. the reconfig_mode_sel[3:0] = 1000 in this mode. one-time mode?the aeq finds a stable setting of the receiver equalizer and locks that value. once locked, the equalizer values are no longer changed. this mode is available in one channel or all channels of the receiver. the reconfig_mode_sel[3:0] = 1001 in this mode. powerdown mode?in this mode, the aeq of the specific channel is placed in standby mode. this mode is available in one channel or all channels of the receiver. the reconfig_mode_sel[3:0] = 1010 in this mode. you are allowed to switch between these modes dynamically. the aeq comes out of standby mode as soon as the value on reconfig_mode_sel is changed to another mode of the aeq control modes. after the aeq goes into powerdown mode and comes out, it does not remember the converged equalization value. by design, the aeq starts at the maximum equalization value after powering up again. figure 1?38. receiver channel data path showing aeq recei v er channel 0 aeq hard ware busy error user logic altgx instance 1 aeq_togxb[23:0] aeq_fromgxb[7:0] logical_channel_address = 0 rx_datain[0] altgx instance 2 recei v er channel 1 logical_channel_address = 4 aeq hard ware rx_datain[1] altgx_reconfig aeq control block aeq_fromgxb[15:8] aeq_togxb[47:24] reconfig_mode_sel[3:0] 1?48 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation to control the aeq hardware in any of the above modes, follow these steps: 1. watch for busy to be low, then write the appropriate value on reconfig_mode_sel[3:0]. 2. assert write_all , then watch for busy to be asserted. 3. de-assert write_all and watch for the de-assertion of busy . de-assertion of busy indicates that adaptive equalization has ended. figure 1?39 shows a waveform of the aeq process. f for more information about the aeq port connections and various waveforms in all the above modes, refer to the stratix iv dynamic reconfiguration chapter. eyeq the eyeq hardware is available in stratix iv gx and gt transceivers to analyze the receiver data recovery path, including receiver gain, clock jitter and noise level. you can use eyeq to monitor the width of the incoming data eye and assess the quality of the incoming signal. normally, the receiver cdr samples the incoming signal at the center of the eye. when you enable the eyeq hardware, it allows the cdr to sample across 32 different positions within one unit interval (ui) of a data eye. you can manually control the sampling points and check the bit-error rate (ber) at each of these 32 sampling points. at the center of the eye, the ber is 0. as the sampling point is moved away from the center of the eye towards an edge, the ber increases. by observing sampling points with 0 ber and sampling points with higher ber, you can determine the eye width. 1 the eyeq hardware is available for both regular transceiver channels and cmu channels. the eyeq block resides within the pma of the receiver channel and is available for both the transceiver channels and cmu channels of a transceiver block. figure 1?40 shows the eyeq feature within a receiver channel datapath. 1 you must implement logic to check the bit error rate (ber). this includes a pattern generator and checker. figure 1?39. aeq process waveform bu sy reconfig_mode_sel[3:0] w rite_all completion of the adoptiv e equalization process chapter 1: stratix iv transceiver architecture 1?49 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?40 shows the receiver channel data path using the eyeq feature. f for more information about using the eyeq feature, refer to the stratix iv dynamic reconfiguration chapter. figure 1?40. receiver channel data path showing the eyeq feature busy error ctrl_ w ritedata[15:0] ctrl_address[15:0] ctrl_ w rite ctrl_read reconfig_fromgxb[17:0] reconfig_togxb[3:0] rx_datain[0] altgx instance eyeq hard w are receiv er channel 0 altgx_reconfig instance eyeq control block ctrl_ w aitrequest ctrl_readdata[15:0] reconfig_mode_sel[3:0] 1?50 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation clock and data recovery unit each stratix iv gx and gt receiver channel has an independent cdr unit to recover the clock from the incoming serial data stream. the high-speed and low-speed recovered clocks are used to clock the receiver pma and pcs blocks. figure 1?41 shows the cdr block diagram. the cdr operates either in ltr mode or ltd mode. in ltr mode, the cdr tracks the input reference clock. in ltd mode, the cdr tracks the incoming serial data. after the receiver power up and reset cycle, the cdr must be kept in ltr mode until it locks to the input reference clock. after it is locked to the input reference clock, the cdr output clock is trained to the configured data rate. the cdr can now switch to ltd mode to recover the clock from incoming data. the ltr/ltd controller controls the switch between ltr and ltd modes. lock-to-reference (ltr) mode in ltr mode, the phase frequency detector in the cdr tracks the receiver input reference clock, rx_cruclk. the pfd controls the charge pump that tunes the vco in the cdr. depending on the data rate and the selected input reference clock frequency, the quartus ii software automatically selects the appropriate /m and /l divider values such that the cdr output clock frequency is half the data rate. an active high, the rx_pll_locked status signal is asserted to indicate that the cdr has locked to the phase and frequency of the receiver input reference clock. figure 1?41 on page 1?50 shows the active blocks (in blue) when the cdr is in ltr mode. 1 the phase detector (pd) is inactive in ltr mode. figure 1?41. clock and data recovery unit (note 1) note to figure 1?41 : (1) the blue colored path is active in lock-to-reference mode; the red colored path is active in lock-to-data mode. clock and data recovery (cdr) unit up down rx_locktorefclk rx_locktodata signal detect rx_freqlocked rx_datain rx_cruclk ltr/ltd controller phase frequency detector (pfd) /2 charge pump + loop filter vco /l /m rx_pll_locked low-speed recovered clock high-speed recovered clock phase detector (pd) down up /2 /1, /2, /4 chapter 1: stratix iv transceiver architecture 1?51 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 you can drive the receiver input reference clock with the following clock sources: dedicated refclk pins ( refclk0 and refclk1 ) of the associated transceiver block inter-transceiver block (itb) clock lines from other transceiver blocks on the same side of the device (up to six itb clock lines, two from each transceiver block) global pld clock driven by a dedicated clock input pin clock output from the left and right plls in the fpga fabric table 1?24 lists cdr specifications in ltr mode. for input reference clock frequencies greater than 325 mhz, the quartus ii software automatically selects the appropriate /1, /2, or /4 pre-divider to meet the pfd input frequency limitation of 325 mhz. lock-to-data (ltd) mode the cdr must be in ltd mode to recover the clock from the incoming serial data during normal operation. in ltd mode, the phase detector (pd) in the cdr tracks the incoming serial data at the receiver buffer. depending on the phase difference between the incoming data and the cdr output clock, the pd controls the cdr charge pump that tunes the vco. figure 1?41 on page 1?50 shows the active blocks (in red) when the cdr is in ltd mode. 1 the pfd is inactive in ltd mode. the rx_pll_locked signal toggles randomly and has no significance in ltd mode. after switching to ltd mode, it can take a maximum of 1 ms for the cdr to get locked to the incoming data and produce a stable recovered clock. the actual lock time depends on the transition density of the incoming data and the ppm difference between the receiver input reference clock and the upstream transmitter reference clock. the receiver pcs logic must be held in reset until the cdr produces a stable recovered clock. f for more information about receiver reset recommendations, refer to the reset control and power down chapter. table 1?24. cdr specifications in lock-to-reference mode parameter value input reference clock frequency 50 mhz to 672 mhz (1) pfd input frequency 50 mhz to 325 mhz /m divider 4, 5, 8, 10, 16, 20, 25 /l divider 1, 2, 4, 8 note to tab l e 1 ?2 4 : (1) the maximum reference clock frequency of 672 mhz is only applicable to speed grades -2 and -3. for speed grade -4, the maximum reference clock frequency is 637.5 mhz. 1?52 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation pci express (pipe) clock switch circuitry the feedback path from the cdr vco to the pd has a /2 divider that is used in pci express (pipe) mode configured at gen2 (5 gbps) data rate for the dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates. when the phy-mac layer instructs a gen2-to-gen1 signaling rateswitch, the /2 divider is enabled. when the phy-mac layer instructs a gen1-to-gen2 signaling rateswitch, the /2 divider is disabled. for more information about the pci express (pipe) signaling rateswitch, refer to ?dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rate? on page 1?138 . 1 the /2 divider in the receiver cdr between the vco and the pd is disabled in all other functional modes. ltr/ltd controller the ltr/ltd controller controls whether the cdr is in ltr or ltd mode. you can configure the ltr/ltd controller either in automatic lock mode or manual lock mode. two optional input ports ( rx_locktorefclk and rx_locktodata ) allow you to configure the ltr/ltd controller in either automatic lock mode or manual lock mode. table 1?25 lists the relationship between these optional input ports and the ltr/ltd controller lock mode. 1 if you do not instantiate the optional rx_locktorefclk and rx_locktodata signals, the quartus ii software automatically configures the ltr/ltd controller in automatic lock mode. automatic lock mode in automatic lock mode, the ltr/ltd controller initially sets the cdr to lock to the input reference clock (ltr mode). after the cdr locks to the input reference clock, the ltr/ltd controller automatically sets it to lock to the incoming serial data (ltd mode) when the following three conditions are met: signal threshold detection circuitry indicates the presence of valid signal levels at the receiver input buffer valid for pci express (pipe) mode only. this condition is defaulted to true for all other modes. the cdr output clock is within the configured ppm frequency threshold setting with respect to the input reference clock (frequency locked) the cdr output clock and the input reference clock are phase matched within approximately 0.08 ui (phase locked) table 1?25. optional input ports and ltr/ltd controller lock mode rx_locktorefclk rx_locktodata ltr/ltd controller lock mode 1 0 manual ? ltr mode x 1 manual ? ltd mode 0 0 automatic lock mode chapter 1: stratix iv transceiver architecture 1?53 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 the switch from ltr to ltd mode is indicated by the assertion of the rx_freqlocked signal. in ltd mode, the cdr uses a phase detector to keep the recovered clock phase-matched to the data. if the cdr does not stay locked to data due to frequency drift or severe amplitude attenuation, the ltr/ltd controller switches the cdr back to ltr mode to lock to the input reference clock. in automatic lock mode, the ltr/ltd controller switches the cdr from ltd to ltr mode when the following conditions are met: signal threshold detection circuitry indicates the absence of valid signal levels at the receiver input buffer valid for pci express (pipe) mode only. this condition is defaulted to true for all other modes. the cdr output clock is not within the configured ppm frequency threshold setting with respect to the input reference clock the switch from ltd to ltr mode is indicated by the de-assertion of the rx_freqlocked signal . manual lock mode in automatic lock mode, the ltr/ltd controller relies on the ppm detector and the phase relationship detector to set the cdr in ltr or ltd mode. the ppm detector and phase relationship detector reaction times can be too long for some applications that require faster cdr lock time. you can manually control the cdr to reduce its lock time using the rx_locktorefclk and rx_locktodata ports. in manual lock mode, the ltr/ltd controller sets the cdr in ltr or ltd mode depending on the logic level on the rx_locktorefclk and rx_locktodata signals. when the rx_locktorefclk signal is asserted high, the ltr/ltd controller forces the cdr to lock to the reference clock. when the rx_locktodata signal is asserted high , it forces the cdr to lock to data. when both signals are asserted, the rx_locktodata signal takes precedence over the rx_locktorefclk signal, forcing the cdr to lock to data. when the rx_locktorefclk signal is asserted high, the rx_freqlocked signal does not have any significance and is always driven low, indicating that the cdr is in ltr mode. when the rx_locktodata signal is asserted high, the rx_freqlocked signal is always driven high, indicating that the cdr is in ltd mode. if both signals are de-asserted, the cdr is in automatic lock mode. 1 the altera-recommended transceiver reset sequence varies depending on the cdr lock mode. f for more information about reset sequence recommendations, refer to the reset control and power down chapter . 1?54 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation offset cancellation in the receiver buffer and receiver cdr as silicon progresses towards smaller process nodes, the performance of circuits at these smaller nodes depends more on process variations. these process variations result in analog voltages that can be offset from the required ranges. offset cancellation logic corrects these offsets. the receiver buffer and receiver cdr require offset cancellation. offset cancellation is executed automatically once each time a stratix iv gx and gt device is powered on. the control logic for offset cancellation is integrated into the altgx_reconfig megafunction. the reconfig_fromgxb and reconfig_togxb buses and the necessary clocks must be connected between the altgx instance and the altgx_reconfig instance. f for more information about offset cancellation control logic connectivity, refer to the stratix iv dynamic reconfiguration chapter. 1 during offset cancellation, signified by a high on the busy signal, rx_analogreset is not relevant until the busy signal goes low. offset cancellation logic requires a separate clock. in pci express (pipe) mode, you must connect the clock input to the fixedclk port provided by the altgx megawizard plug-in manager. the frequency of this clock input must be 125 mhz. for all other functional modes, connect the clock input to the reconfig_clk port provided by the altgx megawizard plug-in manager. the frequency of the clock connected to the reconfig_clk port must be within the range of 37.5 to 50 mhz. figure 1?42 shows the interface of the offset cancellation control logic (altgx_reconfig instance) and the altgx instance. figure 1?42. interface of offset cancellation control logic to the altgx instance [ altgx_reco nfig instance offset cancellation logic transceiver block reconfig_togxb reconfig_fromgxb rx tx buffer cdr rx tx buffer cdr rx tx buffer cdr rx tx buffer cdr dynamic re-config logic busy altgx instance with 4 channels reconfig_clk reconfig_clk chapter 1: stratix iv transceiver architecture 1?55 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 the offset cancellation process begins by disconnecting the path from the receiver input buffer to the receiver cdr. it then sets the receiver cdr into a fixed set of dividers to guarantee a vco clock rate that is within the range necessary to provide proper offset cancellation. subsequently, the offset cancellation process goes through various states and culminates in the offset cancellation of the receiver buffer and the receiver cdr. after offset cancellation is complete, the divider settings are restored. then the reconfiguration block sends and receives data to the altgx instance using the reconfig_togxb and reconfig_fromgxb buses. connect the buses between the altgx_reconfig and altgx instances. the de-assertion of the busy signal from the offset cancellation control logic indicates the offset cancellation process is complete. f due to the offset cancellation process, the transceiver reset sequence has changed. for more information about the offset cancellation process, refer to the reset control and power down chapter. deserializer the deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes it using the low-speed parallel recovered clock. it forwards the deserialized data to the receiver pcs channel. in single-width mode, the deserializer supports 8-bit and 10-bit deserialization factors. in double-width mode, the deserializer supports 16-bit and 20-bit deserialization factors. figure 1?43 shows the deserializer operation in single-width mode with a 10-bit deserialization factor. figure 1?43. deserializer operation in single-width mode d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 10 high-speed serial recovered clock low-speed parallel recovered clock clock recovery unit received data to word aligner 1?56 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?44 shows the serial bit order of the deserializer block input and the parallel data output of the deserializer block in single-width mode with a 10-bit deserialization factor. the serial stream (0101111 100) is deserialized to a value 10'h17c. the serial data is assumed to be received lsb to msb. word aligner because the data is serialized before transmission and then deserialized at the receiver, it loses the word boundary of the upstream transmitter upon deserialization. the word aligner receives parallel data from the deserializer and restores the word boundary based on a pre-defined alignment pattern that must be received during link synchronization. serial protocols such as pci express (pipe), xaui, gigabit ethernet, serial rapidio, and sonet/sdh, specify a standard word alignment pattern. for proprietary protocols, the stratix iv gx and gt transceiver architecture allows you to select a custom word alignment pattern specific to your implementation. in addition to restoring the word boundary, the word aligner also implements the following features: synchronization state machine in functional modes such as pci express (pipe), xaui, gige, serial rapidio, and basic single-width programmable run length violation detection in all functional modes receiver polarity inversion in all functional modes except pci express (pipe) receiver bit reversal in basic single-width and basic double-width modes receiver byte reversal in basic double-width modes depending on the configured functional mode, the word aligner operates in one of the following three modes: manual alignment mode automatic synchronization state machine mode bit-slip mode figure 1?44. deserializer bit order in single-width mode 0101111100 1010000011 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 low-speed parallel clock high-speed serial clock datain dataout chapter 1: stratix iv transceiver architecture 1?57 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?45 shows the word aligner operation in all supported configurations. word aligner in single-width mode in single-width mode, the pma-pcs interface is either 8 or 10 bits wide. in 8-bit wide pma-pcs interface modes, the word aligner receives 8-bit wide data from the deserializer. in 10-bit wide pma-pcs interface modes, the word aligner receives 10-bit wide data from the deserializer. depending on the configured functional mode, you can configure the word aligner in manual alignment mode, automatic synchronization state machine mode, or bit-slip mode. word aligner in single-width mode with 8-bit pma-pcs interface modes the following functional modes support the 8-bit pma-pcs interface: sonet/sdh oc-12 sonet/sdh oc-48 basic single-width table 1?26 shows the word aligner configurations allowed in functional modes with an 8-bit pma-pcs interface. manual alignment mode word aligner with 8-bit pma-pcs interface modes in manual alignment mode, the word aligner operation is controlled by the input signal rx_enapatternalign . the word aligner operation is edge-sensitive to the rx_enapatternalign signal. after de-assertion of rx_digitalreset, a rising edge on the rx_enapatternalign signal triggers the word aligner to look for the word alignment pattern in the received data stream. in sonet/sdh oc-12 and oc-48 modes, the word aligner looks for 16'hf628 (a1a2) or 32'hf6f62828 figure 1?45. word aligner in all supported configurations pma-pcs interface width single-width 8-bit wide 10-bit wide manual alignment (oc-12, oc-48, basic single-width) bit-slip (basic single-width) manual alignment (basic single-width) automatic synchronization state machine (pci express [pipe] xaui, gige, basic single-width, serial rapidio) bit-slip (basic single-width, sdi) double-width 16-bit wide 20-bit wide manual alignment (basic double-width, oc-96) bit-slip (basic double-width) manual alignment (basic double-width) bit-slip (basic double-width) table 1?26. word aligner configurations with an 8-bit pma-pcs interface functional mode allowed word configurations allowed word alignment pattern length sonet/sdh oc-12 manual alignment 16 bits sonet/sdh oc-48 manual alignment 16 bits basic single-width manual alignment, bit-slip 16 bits 1?58 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation (a1a1a2a2), depending on whether the input signal rx_a1a2size is driven low or high, respectively. in basic single-width mode, the word aligner looks for the 16-bit word alignment pattern programmed in the altgx megawizard plug-in manager. the word aligner aligns the 8-bit word boundary to the first word alignment pattern received after the rising edge on the rx_enapatternalign signal. two status signals, rx_syncstatus and rx_patterndetect, with the same latency as the datapath, are forwarded to the fpga fabric to indicate word aligner status. on receiving the first word alignment pattern after the rising edge on the rx_enapatternalign signal, both the rx_syncstatus and rx_patterndetect signals are driven high for one parallel clock cycle synchronous to the msbyte of the word alignment pattern. any word alignment pattern received thereafter in the same word boundary causes only the rx_patterndetect signal to go high for one clock cycle. 1 for the word aligner to re-synchronize to a new word boundary, you must de-assert rx_enapatternalign and re-assert it again to create a rising edge. after a rising edge on the rx_enapatternalign signal, if the word alignment pattern is found in a different word boundary, the word aligner re-synchronizes to the new word boundary and asserts the rx_syncstatus and rx_patterndetect signals for one parallel clock cycle. figure 1?46 shows word aligner behavior in sonet/sdh oc-12 functional mode. the lsbyte (8'hf6) and the msbyte (8'h28) of the 16-bit word alignment pattern are received in parallel clock cycles n and n + 1, respectively. the rx_syncstatus and rx_patterndetect signals are both driven high for one parallel clock cycle synchronous to the msbyte (8'h28) of the word alignment pattern. after initial word alignment, the 16-bit word alignment pattern is again received across the word boundary in clock cycles m, m + 1, and m + 2. the word aligner does not re-align to the new word boundary because of the lack of a preceding rising edge on the rx_enapatternalign signal. if you create a rising edge on the rx_enapatternalign signal before the word alignment pattern is received across clock cycles m, m + 1, and m + 2, the word aligner re-aligns to the new word boundary, causing both the rx_syncstatus and rx_patterndetect signals to go high for one parallel clock cycle. figure 1?46. bit-slip mode in 8-bit pma-pcs interface mode 11110110 00101000 10001111 28 rx_dataout[7:0] rx_enapatternalign rx_patterndetect rx_syncstatus 0110xxxx xxxx0010 f6 6x 8f x2 n n + 1 m m + 1 m + 2 chapter 1: stratix iv transceiver architecture 1?59 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 bit-slip mode word aligner with 8-bit pma-pcs interface modes basic single-width mode with 8-bit pma-pcs interface width allows the word aligner to be configured in bit-slip mode. the word aligner operation is controlled by the input signal rx_bitslip in bit-slip mode. at every rising edge of the rx_bitslip signal, the bit-slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. in bit-slip mode, the word aligner status signal rx_patterndetect is driven high for one parallel clock cycle when the received data after bit-slipping matches the 16-bit word alignment pattern programmed in the altgx megawizard plug-in manager. you can implement a bit-slip controller in the fpga fabric that monitors either the rx_dataout signal and/or the rx_patterndetect signal and controls the rx_bitslip signal to achieve word alignment. figure 1?47 shows an example of the word aligner configured in bit-slip mode. for this example, consider that 8'b11110000 is received back-to-back and 16'b0000 111100011110 is specified as the word alignment pattern. a rising edge on the rx_bitslip signal at time n + 1 slips a single bit 0 at the msb position, forcing the rx_dataout to 8'b01111000. another rising edge on the rx_bitslip signal at time n + 5 forces rx_dataout to 8'b00111100. another rising edge on the rx_bitslip signal at time n + 9 forces rx_dataout to 8'b00011110. another rising edge on the rx_bitslip signal at time n + 13 forces the rx_dataout to 8'b00001111. at this instance, rx_dataout in cycles n + 12 and n + 13 is 8'b00011110 and 8'b0000 1111, respectively, which matches the specified 16-bit alignment pattern 16'b0000 111100011110. this results in the assertion of the rx_patterndetect signal. figure 1?47. word aligner configured in bit-slip mode 01111000 n 11110000 00111100 00011110 00001111 rx_clkout rx_datain rx_dataout[7:0] rx_bitslip rx_patterndetect 11110000 n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14 1?60 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation word aligner in single-width mode with 10-bit pma-pcs interface modes the following functional modes support the 10-bit pma-pcs interface: pci express (pipe) gen1 and gen2 serial rapidio xaui gige sdi basic single-width mode this section describes the following word aligner 10-bit pma-pcs interface modes: automatic synchronization state machine mode with 10-bit pma-pcs interface mode manual alignment mode with 10-bit pma-pcs interface mode bit-slip mode with 10-bit pma-pcs interface mode table 1?27 shows the word aligner configurations allowed in functional modes with a 10-bit pma-pcs interface. automatic synchronization state machine mode word aligner with 10-bit pma-pcs interface mode protocols such as pci express (pipe), xaui, gigabit ethernet, and serial rapidio require the receiver pcs logic to implement a synchronization state machine to provide hysteresis during link synchronization. each of these protocols defines a specific number of synchronization code groups that the link must receive to acquire synchronization and a specific number of erroneous code groups that it must receive to fall out of synchronization. in pci express (pipe), xaui, gigabit ethernet, and serial rapidio functional modes, the quartus ii software configures the word aligner in automatic synchronization state machine mode. it automatically selects the word alignment pattern length and pattern as specified by each protocol. in each of these functional modes, the protocol-compliant synchronization state machine is implemented in the word aligner. table 1?27. word aligner configurations with a 10-bit pma-pcs interface functional mode allowed word aligner configurations allowed word alignment pattern length pci express (pipe) automatic synchronization state machine 10 bits serial rapidio automatic synchronization state machine 10 bits xaui automatic synchronization state machine 7 bits, 10 bits gige automatic synchronization state machine 7 bits, 10 bits sdi bit-slip n/a basic single-width mode manual alignment, automatic synchronization state machine, bit-slip 7 bits, 10 bits chapter 1: stratix iv transceiver architecture 1?61 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 in basic single-width functional mode with a 10-bit pma-pcs interface, you can configure the word aligner in automatic synchronization state machine mode by selecting the use the built-in synchronization state machine option in the altgx megawizard plug-in manager. it also allows you to program a custom 7-bit or 10-bit word alignment pattern that the word aligner uses for synchronization. 1 the 10-bit input data to the word aligner configured in automatic synchronization state machine mode must be 8b/10b encoded. table 1?28 shows the synchronization state machine parameters that the quartus ii software allows in supported functional modes. the synchronization state machine parameters are fixed for pci express (pipe), xaui, gige, and serial rapidio modes as specified by the respective protocol. for basic single-width mode, you can program these parameters as suited to your proprietary protocol implementation. after de-assertion of the rx_digitalreset signal in automatic synchronization state machine mode, the word aligner starts looking for the word alignment pattern or synchronization code groups in the received data stream. when the programmed number of valid synchronization code groups or ordered sets is received, the rx_syncstatus signal is driven high to indicate that synchronization is acquired. the rx_syncstatus signal is constantly driven high until the programmed number of erroneous code groups is received without receiving intermediate good groups; after which the rx_syncstatus is driven low. the word aligner indicates loss of synchronization ( rx_syncstatus remains low) until the programmed number of valid synchronization code groups are received again. manual alignment mode word aligner with 10-bit pma-pcs interface mode in basic single-width mode with a 10-bit pma-pcs interface, you can configure the word aligner in manual alignment mode by selecting the use manual word alignment mode option in the altgx megawizard plug-in manager. in manual alignment mode, the word aligner operation is controlled by the input signal rx_enapatternalign . the word aligner operation is level-sensitive to the rx_enapatternalign signal. if the rx_enapatternalign signal is held high, the word aligner looks for the programmed 7-bit or 10-bit word alignment pattern in the received data stream. it updates the word boundary if it finds the word alignment pattern in a new word boundary. if the rx_enapatternalign signal is de-asserted low, the word aligner maintains the current word boundary even when it sees the word alignment pattern in a new word boundary. table 1?28. synchronization state machine functional modes functional mode pci express (pipe) xaui gige serial rapidio basic single-width mode number of valid synchronization code groups or ordered sets received to achieve synchronization 4 4 3 127 1 to 256 number of erroneous code groups received to lose synchronization 17 4 4 3 1 to 64 number of continuous good code groups received to reduce the error count by one 16 4 4 255 1 to 256 1?62 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation two status signals, rx_syncstatus and rx_patterndetect, with the same latency as the datapath, are forwarded to the fpga fabric to indicate the word aligner status. after receiving the first word alignment pattern after the rx_enapatternalign signal is asserted high, both the rx_syncstatus and rx_patterndetect signals are driven high for one parallel clock cycle. any word alignment pattern received thereafter in the same word boundary causes only the rx_patterndetect signal to go high for one clock cycle. any word alignment pattern received thereafter in a different word boundary causes the word aligner to re-align to the new word boundary only if the rx_enapatternalign signal is held high. the word aligner asserts the rx_syncstatus signal for one parallel clock cycle whenever it re-aligns to the new word boundary. figure 1?48 shows the manual alignment mode word aligner operation with 10-bit pma-pcs interface mode. in this example, a /k28.5/ (10'b010 1111 100) is specified as the word alignment pattern. the word aligner aligns to the /k28.5/ alignment pattern in cycle n because the rx_enapatternalign signal is asserted high. the rx_syncstatus signal goes high for one clock cycle, indicating alignment to a new word boundary. the rx_patterndetect signal also goes high for one clock cycle to indicate initial word alignment. at time n + 1, the rx_enapatternalign signal is de-asserted to instruct the word aligner to lock the current word boundary. the alignment pattern is detected again in a new word boundary across cycles n + 2 and n + 3. the word aligner does not align to this new word boundary because the rx_enapatternalign signal is held low. the /k28.5/ word alignment pattern is detected again in the current word boundary during cycle n + 5, causing the rx_patterndetect signal to go high for one parallel clock cycle. 1 if the word alignment pattern is known to be unique and does not appear between word boundaries, you can constantly hold the rx_enapatternalign signal high because there is no possibility of false word alignment. if there is a possibility of the word alignment pattern occurring across word boundaries, you must control the rx_enapatternalign signal to lock the word boundary after the desired word alignment is achieved to avoid re-alignment to an incorrect word boundary. bit-slip mode word aligner with 10-bit pma-pcs interface mode in some basic single-width configurations with a 10-bit pma-pcs interface, you can configure the word aligner in bit-slip mode by selecting the use manual bit slipping mode option in the altgx megawizard plug-in manager. figure 1?48. word aligner with 10-bit pma-pcs manual alignment mode rx_clkout rx_enapatternalign rx_patterndetect rx_syncstatus rx_dataout[10..0] 111110000 0101111100 111110000 111110000 1000000101 0101111100 1111001010 n n + 1 n + 2 n + 3 n + 4 n + 5 chapter 1: stratix iv transceiver architecture 1?63 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 the word aligner operation for basic single-width with a 10-bit pma-pcs interface is similar to the word aligner operation in basic single-width mode with an 8-bit pma-pcs interface. for word aligner operation in bit-slip mode, refer to ?manual alignment mode word aligner with 8-bit pma-pcs interface modes? on page 1?57 . the only difference is that the bit-slip word aligner with 10-bit pma-pcs interface modes allows 7-bit and 10-bit word alignment patterns, whereas the one with 8-bit pma-pcs interface modes allows only 16-bit word alignment patterns. word aligner in double-width mode in double-width mode, the pma-pcs interface is either 16 or 20 bits wide. in 16-bit pma-pcs interface modes, the word aligner receives 16 bit wide data from the deserializer. in 20-bit pma-pcs interface modes, the word aligner receives 10-bit wide data from the deserializer. depending on the configured functional mode, you can configure the word aligner in manual alignment mode or bit-slip mode. automatic synchronization state machine mode is not supported for word aligner in double-width mode. word aligner in double-width mode with 16-bit pma-pcs interface modes the following functional modes support the 16-bit pma-pcs interface: sonet/sdh oc-96 (oif) cei phy interface basic double-width table 1?29 shows the word aligner configurations allowed in functional modes with a 16-bit pma-pcs interface. manual alignment mode word aligner with 16-bit pma-pcs interface modes in manual alignment mode, the word aligner starts looking for the programmed 8-bit, 16-bit, or 32-bit word alignment pattern in the received data stream as soon as rx_digitalreset is de-asserted low. it aligns to the first word alignment pattern received regardless of the logic level driven on the rx_enapatternalign signal. any word alignment pattern received thereafter in a different word boundary does not cause the word aligner to re-align to this new word boundary. after the initial word alignment following de-assertion of the rx_digitalreset signal, if a word re-alignment is required, you must use the rx_enapatternalign signal. table 1?29. word aligner configurations with 16-bit pma-pcs interface (note 1) functional mode allowed word aligner configurations allowed word alignment pattern length sonet/sdh oc-96 manual alignment 16 bits, 32 bits basic double-width manual alignment, bit-slip 8 bits, 16 bits, 32 bits note to tab l e 1 ?2 9 : (1) the word aligner is bypassed in (oif) cei phy interface mode. 1?64 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation word aligner operation is controlled by the input signal rx_enapatternalign and is edge-sensitive to the rx_enapatternalign signal. a rising edge on the rx_enapatternalign signal triggers the word aligner to look for the word alignment pattern in the received data stream. the word aligner aligns the 16-bit word boundary to the first word alignment pattern received after the rising edge on the rx_enapatternalign signal. any word alignment pattern received thereafter in a different word boundary does not cause the word aligner to re-align to this new word boundary. if another word re-alignment is required, you must de-assert and re-assert the rx_enapatternalign signal to create a rising edge on this signal. two status signals, rx_syncstatus and rx_patterndetect , with the same latency as the datapath, are forwarded to the fpga fabric to indicate word aligner status. after receiving the first word alignment pattern, the rx_patterndetect signal is driven high for one parallel clock cycle synchronous to the data that matches the msbyte of the word alignment pattern. any word alignment pattern received thereafter in the same word boundary causes rx_patterndetect to go high for one parallel clock cycle. after receiving the first word alignment pattern, the rx_syncstatus signal is constantly driven high until the word aligner sees another rising edge on the rx_enapatternalign signal. the rising edge on the rx_enapatternalign signal re-triggers the word alignment operation. figure 1?49 shows the manual alignment mode word aligner operation in 16-bit pma-pcs interface mode. in this example, a 16'hf628 is specified as the word alignment pattern. the word aligner aligns to the 16'hf628 pattern received in cycle n after de-assertion of rx_digitalreset . the rx_patterndetect[1] signal is driven high for one parallel clock cycle. the rx_syncstatus[1] signal is driven high constantly until cycle n + 2, after which it is driven low because of the rising edge on the rx_enapatternalign signal that re-triggers the word aligner operation. the word aligner receives the word alignment pattern again in cycle n + 4, causing the rx_patterndetect[1] signal to be driven high for one parallel clock cycle and the rx_syncstatus[1] signal to be driven high constantly. figure 1?49. manual alignment mode word aligner in 16-bit pma-pcs interface modes xxxx f628 xxxx xxxx xxxx f628 xxxx xxxx 00 10 00 11 10 11 00 10 10 00 00 n n + 1 n + 2 n + 3 n + 4 rx_dataout rx_digitalreset rx_enapatternalign rx_syncstatus[1:0] rx_patterndetect[1:0] chapter 1: stratix iv transceiver architecture 1?65 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 bit-slip mode word aligner with 16-bit pma-pcs interface modes in some basic double-width configurations with 16-bit pma-pcs interface, you can configure the word aligner in bit-slip mode by selecting the use manual bit slipping mode option in the altgx megawizard plug-in manager. the word aligner operation for basic double-width with 16-bit pma-pcs interface is similar to the word aligner operation in basic single-width mode with 8-bit pma-pcs interface. for word aligner operation in bit-slip mode, refer to ?word aligner in single-width mode with 8-bit pma-pcs interface modes? on page 1?57 . the only difference is that the bit-slip word aligner in 16-bit pma-pcs interface modes allows 8-bit and 16-bit word alignment patterns, whereas the bit-slip word aligner in 8-bit pma-pcs interface modes allows only a 16-bit word alignment pattern. word aligner in double-width mode with 20-bit pma-pcs interface modes a 20-bit pma-pcs interface is supported only in basic double-width mode. table 1?30 shows the word aligner configurations allowed in functional modes with a 20-bit pma-pcs interface. manual alignment mode word aligner with 20-bit pma-pcs interface modes the word aligner operation in basic double-width mode with 20-bit pma-pcs interface is similar to the word aligner operation in basic double-width mode with a 16-bit pma-pcs interface. for word aligner operation in manual alignment mode, refer to ?word aligner in double-width mode with 16-bit pma-pcs interface modes? on page 1?63 . the only difference is that the manual alignment mode word aligner in 20-bit pma-pcs interface modes allows 7-, 10-, and 20-bit word alignment patterns, whereas the manual alignment mode word aligner in 16-bit pma-pcs interface modes allows only 8-, 16-, and 32-bit word alignment patterns. bit-slip mode word aligner with 20-bit pma-pcs interface modes in some basic single-width configurations with 20-bit pma-pcs interface, you can configure the word aligner in bit-slip mode by selecting the use manual bit slipping mode option in the altgx megawizard plug-in manager. the word aligner operation for basic double-width with 20-bit pma-pcs interface is similar to the word aligner operation in basic single-width mode with an 8-bit pma-pcs interface. for word aligner operation in bit-slip mode, refer to ?word aligner in single-width mode with 8-bit pma-pcs interface modes? on page 1?57 . the difference is that the bit-slip word aligner in 20-bit pma-pcs interface modes allows only 7-, 10-, and 20-bit word alignment patterns, whereas the bit-slip word aligner in 8-bit pma-pcs interface modes allows only a 16-bit word alignment pattern. table 1?30. word aligner in 20-bit pma-pcs interface modes functional mode allowed word aligner configurations allowed word alignment pattern length basic double-width manual alignment, bit-slip 7 bits, 10 bits, 20 bits 1?66 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation table 1?31 summarizes the word aligner options available in basic single-width and double-width modes. table 1?31. word aligner options available in basic single-width and double-width modes (note 1) (part 1 of 2) functional mode pma-pcs interface width word alignment mode word alignment pattern length rx_enapatternalign sensitivity rx_syncstatus behavior rx_patterndetect behavior basic single-width 8-bit manual alignment 16-bit rising edge sensitive asserted high for one parallel clock cycle when the word aligner aligns to a new word boundary. asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. bit-slip 16-bit n/a n/a asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. 10-bit manual alignment 7- and 10-bit level sensitive asserted high for one parallel clock cycle when the word aligner aligns to a new word boundary. asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. bit-slip 7- and 10-bit n/a n/a asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. automatic synchronization state machine 7- and 10-bit n/a stays high as long as the synchronization conditions are satisfied. asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. chapter 1: stratix iv transceiver architecture 1?67 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 basic double- width 16-bit manual alignment 8-, 16-, and 32-bit rising edge sensitive stays high after the word aligner aligns to the word alignment pattern. goes low on receiving a rising edge on rx_enapatte rnalign until a new word alignment pattern is received. asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. bit-slip 8-, 16-, and 32-bit n/a n/a asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. 20-bit manual alignment 7-, 10-, and 20-bit rising edge sensitive stays high after the word aligner aligns to the word alignment pattern. goes low on receiving a rising edge on rx_enapatte rnalign until a new word alignment pattern is received. asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. bit-slip 7-, 10-, and 20-bit n/a n/a asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. note to tab l e 1 ?3 1 : (1) for more information about word aligner operation, refer to ?word aligner in single-width mode? on page 1?57 and ?word aligner in double- width mode? on page 1?63 . table 1?31. word aligner options available in basic single-width and double-width modes (note 1) (part 2 of 2) functional mode pma-pcs interface width word alignment mode word alignment pattern length rx_enapatternalign sensitivity rx_syncstatus behavior rx_patterndetect behavior 1?68 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation programmable run length violation detection the programmable run length violation circuit resides in the word aligner block and detects consecutive 1s or 0s in the data. if the data stream exceeds the preset maximum number of consecutive 1s or 0s, the violation is signified by the assertion of the rx_rlv signal. the run length violation status signal on the rx_rlv port has lower latency when compared with the parallel data on the rx_dataout port. the rx_rlv signal in each channel is clocked by its parallel recovered clock. the fpga fabric clock might have phase difference and/or ppm difference (in asynchronous systems) with respect to the recovered clock. to ensure that the fpga fabric clock can latch the rx_rlv signal reliably, the run length violation circuitry asserts the rx_rlv signal for a minimum of two recovered clock cycles in single-width modes and a minimum of three recovered clock cycles in double-width modes. the rx_rlv signal can be asserted longer, depending on the run length of the received data. in single-width mode, the run length violation circuit detects up to a run length of 128 (for an 8-bit deserialization factor) or 160 (for a 10-bit deserialization factor). the settings are in increments of four or five for the 8-bit or 10-bit deserialization factors, respectively. in double-width mode, the run length violation circuit maximum run length detection is 512 (with a run length increment of eight) and 640 (with a run length increment of 10) for the 16-bit and 20-bit deserialization factors, respectively. table 1?32 summarizes the detection capabilities of the run length violation circuit. receiver polarity inversion the positive and negative signals of a serial differential link are often erroneously swapped during board layout. solutions like board re-spin or major updates to the pld logic can be expensive. the receiver polarity inversion feature is provided to correct this situation. an optional rx_invpolarity port is available in all single-width and double-width modes except (oif) cei phy and pci express (pipe) modes to dynamically enable the receiver polarity inversion feature. in single-width modes, a high value on the rx_invpolarity port inverts the polarity of every bit of the 8-bit or 10-bit input data word to the word aligner in the receiver datapath. in double-width modes, a high value on the rx_invpolarity port inverts the polarity of every bit of the 16-bit or 20-bit input data word to the word aligner in the receiver datapath. because table 1?32. detection capabilities of the run length violation circuit mode pma-pcs interface width run length violation detector range minimum maximum single-width mode 8-bit 4 128 10-bit 5 160 double-width mode 16-bit 8 512 20-bit 10 640 chapter 1: stratix iv transceiver architecture 1?69 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is seen by the receiver. rx_invpolarity is a dynamic signal and can cause initial disparity errors in an 8b/10b encoded link. the downstream system must be able to tolerate these disparity errors. the generic receiver polarity inversion feature is different from the pci express (pipe) 8b/10b polarity inversion feature. the generic receiver polarity inversion feature inverts the polarity of the data bits at the input of the word aligner and is not available in pci express (pipe) mode. the pci express (pipe) 8b/10b polarity inversion feature inverts the polarity of the data bits at the input of the 8b/10b decoder and is available only in pci express (pipe) mode. figure 1?50 shows the receiver polarity inversion feature in single-width and double-width datapath configurations. figure 1?50. receiver polarity inversion in single-width and double width mode 1 0 1 0 0 0 0 0 1 1 output from deserializer input to word aligner 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 single-width configuration single-width configuration double-width configuration double-width configuration rx_invpolarity = high rx_invpolarity = high to the word aligner to the word aligner 1?70 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation receiver bit reversal by default, the stratix iv gx and gt receiver assumes a lsb-to-msb transmission. if the transmission order is msb-to-lsb, the receiver forwards the bit-flipped version of the parallel data to the fpga fabric on the rx_dataout port. the receiver bit reversal feature is available to correct this situation. the receiver bit reversal feature is available through the rx_revbitordwa port only in basic single-width and double-width modes with the word aligner configured in bit-slip mode. when the rx_revbitordwa signal is driven high in basic single-width mode, the 8-bit or 10-bit data d[7:0] or d[9:0] at the output of the word aligner gets rewired to d[0:7] or d[0:9] , respectively. when the rx_revbitordwa signal is driven high in basic double-width mode, the 16-bit or 20-bit data d[15:0] or d[19:0] at the output of the word aligner gets rewired to d[0:15] or d[0:19], respectively. flipping the parallel data using this feature allows the receiver to forward the correct bit-ordered data to the fpga fabric on the rx_dataout port in the case of msb-to-lsb transmission. figure 1?51 shows the receiver bit reversal feature in basic single-width 10-bit wide datapath configurations. figure 1?51. receiver bit reversal in single-width mode d [ 9 ] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] d[8] d[9] output of word aligner before rx bit reversal output of word aligner after rx bit reversal rx_revbitordwa = high chapter 1: stratix iv transceiver architecture 1?71 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?52 shows the receiver bit reversal feature in basic double-width 20-bit wide datapath configurations. because receiver bit reversal is done at the output of the word aligner, a dynamic bit reversal also requires a reversal of the word alignment pattern. as a result, the receiver bit reversal feature is dynamic only if the receiver is dynamically reconfigurable (it allows changing the word alignment pattern dynamically) or uses manual bit slip alignment mode (no word alignment pattern). the receiver bit reversal feature is static in all other basic mode configurations. you can enable this feature using the megawizard plug-in manager. in configurations where the receiver bit reversal feature is dynamic, an rx_revbitordwa port is available to control the bit reversal dynamically. a high on the rx_revbitordwa port reverses the bit order at the input of the word aligner. figure 1?52. receiver bit reversal in double-width mode to serializer d[0] d[2] d[1] d[4] d[3] d[6] d[5] d[8] d[7] d[10] d[9] d[12] d[11] d[15] d[13] d[14] d[17] d[16] d[19] d[18] d[18] d[19] d[16] d[17] d[15] d[13] d[14] d[11] d[12] d[9] d[10] d[7] d[8] d[5] d[6] d[3] d[4] d[1] d[2] d[0] output of word aligner before rx bit reversal output of word aligner after rx bit reversal rx_revbitordwa = high 1?72 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation receiver byte reversal in basic double-width modes the msbyte and lsbyte of the input data to the transmitter may be erroneously swapped. the receiver byte reversal feature is available to correct this situation. an optional port, rx_revbyteordwa , is available only in basic double-width mode to enable receiver byte reversal. in 8b/10b enabled mode, a high value on rx_revbyteordwa exchanges the 10-bit msbyte for the lsbyte of the 20-bit word at the output of the word aligner in the receiver datapath. in non-8b/10b enabled mode, a high value on rx_revbyteordwa exchanges the 8-bit msbyte for the lsbyte of the 16-bit word at the output of the word aligner in the receiver datapath. this compensates for the erroneous exchanging at the transmitter and corrects the data received by the downstream systems. rx_revbyteorderwa is a dynamic signal and can cause an initial disparity error at the receiver of an 8b/10b encoded link. the downstream system must be able to tolerate this disparity error. figure 1?53 shows the receiver byte reversal feature. deskew fifo code groups received across four lanes in a xaui link can be misaligned with respect to one another because of skew in the physical medium or differences between the independent clock recoveries per lane. the xaui protocol allows a maximum skew of 40 ui (12.8 ns) as seen at the receiver of the four lanes. xaui protocol requires the physical layer device to implement a deskew circuitry to align all four channels. to enable the deskew circuitry at the receiver to align the four channels, the transmitter sends a /a/ (/k28.3/) code group simultaneously on all four channels during inter-packet gap (ipg). the skew introduced in the physical medium and the receiver channels can cause the /a/ code groups to be received misaligned. figure 1?53. receiver byte reversal feature 01 00 03 02 05 04 07 06 09 08 0b 0a msbyte lsbyte xx xx xx xx 07 06 09 08 0b 0a msbyte lsbyte 00 01 02 03 04 05 06 07 08 09 0a 0b msbyte lsbyte data to be transmitted input data to transmitter rx_revbyteordwa word aligner output with rx_revbyteordwa asserted chapter 1: stratix iv transceiver architecture 1?73 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 deskew circuitry performs the deskew operation by the xaui functional mode. deskew circuitry consists of: a 16-word deep deskew fifo in each of the four channels control logic in the cmu0 channel of the transceiver block that controls the deskew fifo write and read operations in each channel 1 deskew circuitry is only available in xaui mode. the deskew fifo in each channel receives data from its word aligner. the deskew operation begins only after link synchronization is achieved on all four channels as indicated by a high level on the rx_syncstatus signal from the word aligner in each channel. until the first /a/ code group is received, the deskew fifo read and write pointers in each channel are not incremented. after the first /a/ code group is received, the write pointer starts incrementing for each word received but the read pointer is frozen. if the /a/ code group is received on each of the four channels within 10 recovered clock cycles of each other, the read pointer for all four deskew fifos is released simultaneously, aligning all four channels. figure 1?54 shows lane skew at the receiver input and how the deskew fifo uses the /a/ code group to align the channels. after alignment of the first ||a|| column, if three additional aligned ||a|| columns are observed at the output of the deskew fifos of the four channels, the rx_channelaligned signal is asserted high, indicating channel alignment is acquired. after acquiring channel alignment, if four misaligned ||a|| columns are seen at the output of the deskew fifos in all four channels with no aligned ||a|| columns in between, the rx_channelaligned signal is de-asserted low, indicating loss-of-channel alignment. figure 1?54. deskew fifo?lane skew at the receiver input lanes are deskewed by lining up the "align"/a/, code groups lane skew at receiver input a lane 0 k k r a k r r k k k rr lane 1 k k r a k r r k k k rr lane 0 k k r k r r k k k rr lane 1 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr 1?74 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the deskew operation in xaui functional mode is compliant to the pcs deskew state machine diagram specified in clause 48 of ieee p802.3ae, as shown in figure 1?55 . rate match (clock rate compensation) fifo in asynchronous systems, the upstream transmitter and local receiver can be clocked with independent reference clocks. frequency differences in the order of a few hundred ppm can corrupt the data when latching from the recovered clock domain (the same clock domain as the upstream transmitter reference clock) to the local receiver reference clock domain. the rate match fifo compensates for small clock frequency differences between the upstream transmitter and the local receiver clocks by inserting or removing skp symbols or ordered sets from the ipg or idle streams. it deletes skp symbols or ordered sets when the upstream transmitter reference clock frequency is higher than the local receiver reference clock frequency. it inserts skp symbols or ordered-sets when the local receiver reference clock frequency is higher than the upstream transmitter reference clock frequency. figure 1?55. deskew fifo operation in xaui functional mode (note 1) note to figure 1?55 : (1) this figure is from ieee p802.3ae. reset + (sync_status=fail * sudi) sync_status ok * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi sudi(![/||a||/]) loss_of_alignment align_status ? fail enable_deskew ? true audi align_detect_1 enable_deskew ? false audi align_detect_2 audi align_detect_3 audi 3 !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) align _acquired_1 enable_deskew ? false audi align _acquired_2 audi align _acquired_3 audi 1 2 3 !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) align _acquired_4 audi 2 sudi(![/||a||/]) 1 sudi(![/||a||/]) chapter 1: stratix iv transceiver architecture 1?75 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 the rate match fifo consists of a 20-word deep fifo and necessary logic that controls insertion and deletion of a skip character or ordered set, depending on the ppm difference. the rate match fifo is mandatory and cannot be bypassed in the following functional modes: pci express (pipe) xaui gige the rate match fifo is optional in the following functional modes: basic single-width basic double-width srio the rate match fifo receives data from the word aligner (non-xaui functional modes) or deskew fifo (xaui functional mode) in the receiver datapath. it provides the following status signals forwarded to the fpga fabric: rx_rmfifodatainserted ?indicates insertion of a skip character or ordered set rx_rmfifodatadeleted ?indicates deletion of a skip character or ordered set rx_rmfifofull ?indicates rate match fifo full condition rx_rmfifoempty ?indicates rate match fifo empty condition 1 the rate match fifo status signals are not available in pci express (pipe) mode. these signals are encoded on the pipestatus[2:0] signal in pci express (pipe) mode as specified in the pci express (pipe) specification. rate match fifo in pci express (pipe) mode in pci express (pipe) mode, the rate match fifo is capable of compensating up to 300 ppm (total 600 ppm) difference between the upstream transmitter and the local receiver. the pci express (pipe) protocol requires the transmitter to send skp ordered sets during ipgs, adhering to rules listed in the base specification. the skp ordered set is defined as a /k28.5/ com symbol followed by three consecutive /k28.0/ skp symbol groups. the pci express (pipe) protocol requires the receiver to recognize a skp ordered set as a /k28.5/ com symbol followed by one to five consecutive /k28.0/ skp symbols. the rate match fifo operation is compliant to pci express (pipe) base specification 2.0. the rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. the rate match fifo looks for the skp ordered set and deletes or inserts skp symbols as necessary to prevent the rate match fifo from overflowing or under-running. 1?76 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the rate match fifo inserts or deletes only one skp symbol per skp ordered set received. rate match fifo insertion and deletion events are communicated to the fpga fabric on the pipestatus[2:0] port from each channel. the pipestatus[2:0] signal is driven to 3'b001 for one clock cycle synchronous to the /k28.5/ com symbol of the skp ordered set in which the /k28.0/ skp symbol is inserted. the pipestatus[2:0] signal is driven to 3'b010 for one clock cycle synchronous to the /k28.5/ com symbol of the skp ordered set from which the /k28.0/ skp symbol is deleted. figure 1?56 shows an example of rate match deletion in the case where two /k28.0/ skp symbols are required to be deleted. only one /k28.0/ skp symbol is deleted per skp ordered set received. figure 1?57 shows an example of rate match insertion in the case where two skp symbols are required to be inserted. only one /k28.0/ skp symbol is inserted per skp ordered set received. the rate match fifo full and empty conditions are communicated to the fpga fabric on the pipestatus[2:0] port from each channel. the rate match fifo in pci express (pipe) mode automatically deletes the data byte that causes the fifo to go full and drives pipestatus[2:0] = 3'b101 synchronous to the subsequent data byte. figure 1?56. rate match deletion in pci express (pipe) mode datain dataout pipestatus[2:0] first skip ordered set k28.5 k28.0 k28.0 dx.y k28.5 k28.0 dx.y k28.5 k28.5 k28.0 k28.0 k28.0 k28.0 second skip ordered set skip symbol deleted 3'b010 xxx xxx xxx 3'b010 xxx figure 1?57. rate match insertion in pci express (pipe) mode datain dataout pipestatus[2:0] first skip ordered set k28.0 k28.0 dx.y k28.5 k28.5 k28.0 k28.0 k28.0 second skip ordered set skip symbol inserted k28.5 k28.0 dx.y k28.5 k28.0 k28.0 k28.0 k28.0 k28.0 k28.0 xxx xxx 3'b001 xxx xxx 3'b001 xxx xxx xxx xxx chapter 1: stratix iv transceiver architecture 1?77 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?58 shows the rate match fifo full condition in pci express (pipe) mode. the rate match fifo becomes full after receiving data byte d4. the rate match fifo automatically inserts /k30.7/ (9'h1fe) after the data byte that causes the fifo to go empty and drives pci express (pipe)status[2:0] = 3?b110 flag synchronous to the inserted /k30.7/ (9'h1fe). figure 1?59 shows rate match fifo empty condition in pci express (pipe) mode. the rate match fifo becomes empty after reading out data byte d3. 1 you can configure the rate match fifo in low latency mode by turning off the enable rate match fifo option in the altgx megawizard plug-in manager. rate match fifo in xaui mode in xaui mode, the rate match fifo is capable of compensating for up to 100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. the xaui protocol requires the transmitter to send /r/ (/k28.0/) code groups simultaneously on all four lanes (denoted as ||r|| column) during inter-packet gaps, adhering to rules listed in the ieee p802.3ae specification. the rate match fifo operation in xaui mode is compliant to the ieee p 802.3ae specification. the rate match operation begins after: the synchronization state machine in the word aligner of all four channels indicates synchronization was acquired by driving its rx_syncstatus signal high the deskew fifo block indicates alignment was acquired by driving the rx_channelaligned signal high the rate match fifo looks for the ||r|| column (simultaneous /r/ code group on all four channels) and deletes or inserts the ||r|| column to prevent the rate match fifo from overflowing or under-running. it can insert or delete as many ||r|| columns as necessary to perform the rate match operation. figure 1?58. rate match fifo full condition in pci express (pipe) mode d1 d2 d1 d2 d7 datain dataout d4 d4 d5 d6 d7 d8 d3 d3 d6 xx d8 xx xx xxx xxx xxx 3'b101 xxx xxx xxx xxx pipestatus[2:0] figure 1?59. rate match fifo empty condition in pci express (pipe) mode d1 d2 d1 d2 d5 datain dataout /k30.7/ d4 d5 d6 d3 d3 d4 pipestatus[2:0] 3'b110 xxx xxx xxx xxx xxx 1?78 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , that indicate rate match fifo deletion and insertion events, respectively, are forwarded to the fpga fabric. if an ||r|| column is deleted, the rx_rmfifodeleted flag from each of the four channels goes high for one clock cycle per deleted ||r|| column. if an ||r|| column is inserted, the rx_rmfifoinserted flag from each of the four channels goes high for one clock cycle per inserted ||r|| column. figure 1?60 shows an example of rate match deletion in the case where three ||r|| columns must be deleted. figure 1?60. rate match deletion in xaui mode datain[3] rx_rmfifodatadeleted k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 first ||r|| column second ||r|| column third ||r|| column fourth ||r|| column k28.5 datain[2] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 datain[1] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 datain[0] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 dataout[3] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[2] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[1] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[0] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 chapter 1: stratix iv transceiver architecture 1?79 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?61 shows an example of rate match insertion in the case where two ||r|| columns are required to be inserted. two flags, rx_rmfifofull and rx_rmfifoempty , are forwarded to the fpga fabric to indicate rate match fifo full and empty conditions. in xaui mode, the rate match fifo does not automatically insert or delete code groups to overcome fifo empty and full conditions, respectively. it asserts the rx_rmfifofull and rx_rmfifoempty flags for at least three recovered clock cycles to indicate rate match fifo full and empty conditions, respectively. 1 in the case of rate match fifo full and empty conditions, you must assert the rx_digitalreset signal to reset the receiver pcs blocks. rate match fifo in gige mode in gige mode, the rate match fifo is capable of compensating for up to 100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. the gige protocol requires the transmitter to send idle ordered sets /i1/ (/k28.5/d5.6/) and /i2/ (/k28.5/d16.2/) during inter-packet gaps, adhering to rules listed in the ieee 802.3 specification. the rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. the rate match fifo is capable of deleting or inserting the /i2/ (/k28.5/d16.2/) ordered set to prevent the rate match fifo from overflowing or under running during normal packet transmission. the rate match fifo is also capable of deleting or inserting the first two bytes of the /c2/ ordered set (/k28.5/d2.2/dx.y/dx.y/) to prevent the rate match fifo from overflowing or under running during the auto negotiation phase. figure 1?61. rate match insertion in xaui mode dataout[3] rx_rmfifodatainserted k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 first ||r|| column second ||r|| column k28.5 dataout[2] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 dataout[1] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 dataout[0] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 datain[3] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 datain[2] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 datain[1] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 datain[0] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 1?80 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the rate match fifo can insert or delete as many /i2/ or /c2/ (first two bytes) as necessary to perform the rate match operation. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , that indicate rate match fifo deletion and insertion events, respectively, are forwarded to the fpga fabric. both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are asserted for two clock cycles for each deleted and inserted /i2/ ordered set, respectively. figure 1?62 shows an example of rate match fifo deletion in the case where three symbols are required to be deleted. because the rate match fifo can only delete /i2/ ordered set, it deletes two /i2/ ordered sets (four symbols deleted). figure 1?63 shows an example of rate match fifo insertion in the case where one symbol is required to be inserted. because the rate match fifo can only insert a /i2/ ordered set, it inserts one /i2/ ordered set (two symbols inserted). two flags, rx_rmfifofull and rx_rmfifoempty , are forwarded to the fpga fabric to indicate rate match fifo full and empty conditions. in gige mode, the rate match fifo does not insert or delete code groups automatically to overcome fifo empty and full conditions, respectively. it asserts the rx_rmfifofull and rx_rmfifoempty flags for at least two recovered clock cycles to indicate rate match fifo full and empty conditions, respectively. 1 in the case of rate match fifo full and empty conditions, you must assert the rx_digitalreset signal to reset the receiver pcs blocks. figure 1?62. rate match deletion in gige mode datain dataout rx_rmfifodatadeleted first /i2/ ordered set dx.y k28.5 k28.5 second /i2/ ordered set /i2/ ordered set deleted d16.2 d16.2 k28.5 d16.2 dx.y third /i2/ ordered set dx.y k28.5 d16.2 dx.y figure 1?63. rate match insertion in gige mode datain dataout rx_rmfifodatainserted first /i2/ ordered set dx.y k28.5 k28.5 second /i2/ ordered set d16.2 d16.2 dx.y k28.5 d16.2 d16.2 dx.y k28.5 d16.2 k28.5 chapter 1: stratix iv transceiver architecture 1?81 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 rate match fifo in basic single-width mode in basic single-width mode, the rate match fifo is capable of compensating for up to 300 ppm (600 ppm total) difference between the upstream transmitter and the local receiver reference clock. 1 to enable the rate match fifo in basic single-width mode, the transceiver channel must have both the transmitter and receiver channel instantiated. you must select the receiver and transmitter option in the what is the operation mode? field in the altgx megawizard plug-in manager. you must also enable the 8b/10b encoder/decoder in basic single-width mode with rate match fifo enabled. depending on your proprietary protocol implementation, you can select two 20-bit rate match patterns in the altgx megawizard plug-in manager under the what is the rate match pattern1 and what is the rate match pattern2 fields. each of the two programmed 20-bit rate match patterns consists of a 10-bit skip pattern and a 10-bit control pattern. you must choose 10-bit code groups that have a neutral disparity as the skip patterns. the rate match fifo operation begins after the word aligner synchronization status rx_syncstatus goes high. when the rate matcher receives either of the two 10-bit control patterns followed by the respective 10-bit skip pattern, it inserts or deletes the 10-bit skip pattern as necessary to avoid the rate match fifo from overflowing or under running. the rate match fifo can delete a maximum of four skip patterns from a cluster, if there is one skip pattern left in the cluster after deletion. the rate match fifo can insert a maximum of four skip patterns in a cluster, if there are no more than five skip patterns in the cluster after insertion. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , indicating rate match fifo deletion and insertion events, respectively, are forwarded to the fpga fabric. figure 1?64 shows an example of rate match fifo deletion in the case where three skip patterns are required to be deleted. in this example, /k28.5/ is the control pattern and neutral disparity /k28.0/ is the skip pattern. the first skip cluster has a /k28.5/ control pattern followed by two /k28.0/ skip patterns. the second skip cluster has a /k28.5/ control pattern followed by four /k28.0/ skip patterns. the rate match fifo deletes only one /k28.0/ skip pattern from the first skip cluster to maintain at least one skip pattern in the cluster after deletion. two /k28.0/ skip patterns are deleted from the second cluster for a total of three skip patterns deletion requirement. figure 1?64. rate match deletion in basic single-width mode datain dataout rx_rmfifodatadeleted first skip cluster k28.5 k28.5 second skip cluster three skip patterns deleted k28.0 k28.0 k28.0 k28.0 k28.0 k28.0 k28.5 k28.0 k28.5 k28.0 k28.0 k28.0 1?82 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?65 shows an example of rate match fifo insertion in the case where three skip patterns are required to be inserted. in this example, /k28.5/ is the control pattern and neutral disparity /k28.0/ is the skip pattern. the first skip cluster has a /k28.5/ control pattern followed by three /k28.0/ skip patterns. the second skip cluster has a /k28.5/ control pattern followed by one /k28.0/ skip pattern. the rate match fifo inserts only two /k28.0/ skip patterns into the first skip cluster to maintain a maximum of five skip patterns in the cluster after insertion. one /k28.0/ skip pattern is inserted into the second cluster for a total of three skip patterns to meet the insertion requirement. two flags, rx_rmfifofull and rx_rmfifoempty , are forwarded to the fpga fabric to indicate rate match fifo full and empty conditions. the rate match fifo in basic single-width mode automatically deletes the data byte that causes the fifo to go full and asserts the rx_rmfifofull flag synchronous to the subsequent data byte. figure 1?66 shows the rate match fifo full condition in basic single-width mode. the rate match fifo becomes full after receiving data byte d4. the rate match fifo automatically inserts /k30.7/ (9'h1fe) after the data byte that causes the fifo to go empty and asserts the rx_fifoempty flag synchronous to the inserted /k30.7/ (9'h1fe). figure 1?65. rate match insertion in basic single-width mode datain dataout rx_rmfifoinserted first skip cluster k28.0 k28.5 second skip cluster three skip patterns inserted k28.0 k28.0 k28.5 k28.0 dx.y k28.5 k28.0 k28.0 k28.0 k28.0 k28.0 k28.0 k28.5 k28.0 dx.y k28.0 k28.0 figure 1?66. rate match fifo full condition in basic single-width mode d1 d2 d1 d2 d7 datain dataout d4 d4 d5 d6 d7 d8 d3 d3 d6 rx_rmfifofull xx d8 xx xx chapter 1: stratix iv transceiver architecture 1?83 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?67 shows the rate match fifo empty condition in basic single-width mode. the rate match fifo becomes empty after reading out data byte d3. rate match fifo in basic double-width mode in basic double-width mode, the rate match fifo is capable of compensating up to 300 ppm (total 600 ppm total) difference between the upstream transmitter and the local receiver reference clock. 1 to enable the rate match fifo in basic double-width mode, the transceiver channel must have both the transmitter and receiver channel instantiated. you must select the receiver and transmitter option in the what is the operation mode? field in the altgx megawizard plug-in manager. you must also enable the 8b/10b encoder/decoder in basic double-width mode with rate match fifo enabled. depending on your proprietary protocol implementation, you can select two 20-bit rate match patterns in the altgx megawizard plug-in manager under the what is the rate match pattern1 and what is the rate match pattern2 fields. each of the two programmed 20-bit rate match patterns consists of a 10-bit skip pattern and a 10-bit control pattern. you must choose 10-bit code groups that have a neutral disparity as the skip patterns. the rate match fifo operation begins after the word aligner synchronization status rx_syncstatus goes high. when the rate matcher receives either of the two 10-bit control patterns followed by the respective 10-bit skip pattern, it inserts or deletes a pair of 10-bit skip patterns as necessary to avoid the rate match fifo from overflowing or under running. the rate match fifo can delete as many pairs of skip patterns from a cluster necessary to avoid the rate match fifo from overflowing. the rate match fifo can delete a pair of skip patterns only if the two 10-bit skip patterns appear in the same clock cycle on the lsbyte and msbyte of the 20-bit word. if the two skip patterns appear straddled on the msbyte of a clock cycle and the lsbyte of the next clock cycle, the rate match fifo cannot delete the pair of skip patterns. the rate match fifo can insert as many pairs of skip patterns into a cluster necessary to avoid the rate match fifo from under running. the 10-bit skip pattern can appear on msbyte or lsbyte, or both, of the 20-bit word. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , indicating rate match fifo deletion and insertion events, respectively, are forwarded to the fpga fabric. figure 1?67. rate match fifo empty condition in basic single-width mode d1 d2 d1 d2 d5 datain dataout /k30.7/ d4 d5 d6 d3 d3 d4 rx_rmfifoempty 1?84 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?68 shows an example of rate match fifo deletion in the case where three skip patterns are required to be deleted. in this example, /k28.5/ is the control pattern and neutral disparity /k28.0/ is the skip pattern. the first skip cluster has a /k28.5/ control pattern in the lsbyte and /k28.0/ skip pattern in the msbyte of a clock cycle followed by one /k28.0/ skip pattern in the lsbyte of the next clock cycle. the rate match fifo cannot delete the two skip patterns in this skip cluster because they do not appear in the same clock cycle. the second skip cluster has a /k28.5/ control pattern in the msbyte of a clock cycle followed by two pairs of /k28.0/ skip patterns in the next two cycles. the rate match fifo deletes both pairs of /k28.0/ skip patterns (for a total of four skip patterns deleted) from the second skip cluster to meet the three skip pattern deletion requirement. figure 1?69 shows an example of rate match fifo insertion in the case where three skip patterns are required to be inserted. in this example, /k28.5/ is the control pattern and neutral disparity /k28.0/ is the skip pattern. the first skip cluster has a /k28.5/ control pattern in the lsbyte and /k28.0/ skip pattern in the msbyte of a clock cycle followed by one /k28.0/ skip pattern in the lsbyte of the next clock cycle. the rate match fifo inserts pairs of skip patterns in this skip cluster to meet the three skip pattern insertion requirement. figure 1?68. rate match deletion in basic double-width mode datain[19:10] rx_rmfifodatadeleted k28.5 k28.0 dx.y k28.0 k28.0 dx.y first skip cluster second skip cluster dx.y datain[9:0] dx.y k28.5 k28.0 k28.0 k28.0 dx.y dataout[19:0] k28.5 k28.0 dx.y dx.y dataout[9:0] dx.y k28.5 k28.0 dx.y dx.y dx.y dx.y two pairs of skip patterns deleted figure 1?69. rate match insertion in basic double-width mode datain[19:10] rx_rmfifodatainserted k28.0 k28.0 k28.0 dx.y k28.5 k28.0 first skip cluster second skip cluster dx.y datain[9:0] k28.0 k28.5 k28.0 dx.y dx.y k28.0 dx.y dataout[19:0] k28.5 k28.0 dx.y k28.0 dataout[9:0] dx.y k28.5 dx.y k28.0 dx.y dx.y k28.0 k28.0 k28.0 k28.0 chapter 1: stratix iv transceiver architecture 1?85 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 two flags, rx_rmfifofull and rx_rmfifoempty , are forwarded to the fpga fabric to indicate rate match fifo full and empty conditions. the rate match fifo in basic double-width mode automatically deletes the pair of data byte that causes the fifo to go full and asserts the rx_rmfifofull flag synchronous to the subsequent pair of data bytes. figure 1?70 shows the rate match fifo full condition in basic double-width mode. the rate match fifo becomes full after receiving the 20-bit word d5d6. the rate match fifo automatically inserts a pair of /k30.7/ ({9'h1fe,9'h1fe}) after the data byte that causes the fifo to go empty and asserts the rx_fifoempty flag synchronous to the inserted pair of /k30.7/ ({9'h1fe,9'h1fe}). figure 1?71 shows the rate match fifo empty condition in basic double-width mode. the rate match fifo becomes empty after reading out the 20-bit word d5d6. figure 1?70. rate match fifo full condition in basic double-width mode datain[19:10] datain[9:0] dataout[19:0] dataout[9:0] rx_rmfifofull d2 d4 d6 d8 d10 d12 d1 d3 d5 d7 d9 d11 d2 d4 d6 d10 d12 xx d1 d3 d5 d9 d11 xx figure 1?71. rate match fifo empty condition in basic double-width mode datain[19:10] datain[9:0] dataout[19:0] dataout[9:0] rx_rmfifoempty d2 d4 d6 d8 d10 d12 d2 d4 d6 d8 d10 /k30.7/ /k30.7/ d1 d3 d5 d7 d9 d11 d1 d3 d5 d7 d9 1?86 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation 8b/10b decoder protocols such as pci express (pipe), xaui, gige, and serial rapidio require the serial data sent over the link to be 8b/10b encoded to maintain the dc balance in the serial data transmitted. these protocols require the receiver pcs logic to implement an 8b/10b decoder to decode the data before forwarding it to the upper layers for packet processing. the stratix iv gx and gt receiver channel pcs datapaths implement the 8b/10b decoder after the rate matcher. in functional modes with rate matcher enabled, the 8b/10b decoder receives data from the rate matcher. in functional modes with rate matcher disabled, the 8b/10b decoder receives data from the word aligner. the 8b/10b decoder operates in two modes ( figure 1?72 ): single-width mode double-width mode 8b/10b decoder in single-width mode the left side of figure 1?72 shows the 8b/10b decoder in single-width mode. in this mode, the 8b/10b decoder receives 10-bit data from the rate matcher or word aligner (when rate matcher is disabled) and decodes it into an 8-bit data + 1-bit control identifier. the decoded data is fed to the byte deserializer or the receiver phase compensation fifo (if byte deserializer is disabled). 1 the 8b/10b decoder is compliant to clause 36 in the ieee802.3 specification. figure 1?72. 8b/10b decoder in single-width and double-width mode datain [19:10] recovered clock or tx_clkout[0] current running disparity rx_dataout [15:8] rx_ctrldetect[1] rx_errdetect[1] rx_disperr[1] datain[9:0] rx_dataout[7:0] rx_ctrldetect rx_errdetect rx_disperr recovered clock or tx_clkout[0] single-width mode current running disparity datain[19:10] rx_dataout[15:8] rx_ctrldetect[1] rx_errdetect[1] rx_disperr[1] recovered clock or tx_clkout[0] datain[9:0] rx_dataout[7:0] rx_ctrldetect rx_errdetect rx_disperr recovered clock or tx_clkout[0] double-width mode 8b/10b decoder (lsb byte) 8b/10b decoder (lsb byte) 8b/10b decoder (lsb byte) 8b/10b decoder (msb byte) chapter 1: stratix iv transceiver architecture 1?87 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 the 8b/10b decoder operates in single-width mode in the following functional modes: pci express (pipe) xaui gige serial rapidio basic single-width for pci express (pipe), xaui, gige, and serial rapidio functional modes, the altgx megawizard plug-in manager forces selection of the 8b/10b decoder in the receiver datapath. in basic single-width mode, it allows you to enable or disable the 8b/10b decoder depending on your pr oprietary protocol implementation. figure 1?73 shows a 10-bit code group decoded into an 8-bit data and a 1-bit control identifier by the 8b/10b decoder in single-width mode. control code group detection the 8b/10b decoder indicates whether the decoded 8-bit code group is a data or control code group on the rx_ctrldetect port. if the received 10-bit code group is one of the 12 control code groups (/kx.y/) specified in the ieee802.3 specification, the rx_ctrldetect signal is driven high. if the received 10-bit code group is a data code group (/dx.y/), the rx_ctrldetect signal is driven low. figure 1?74 shows the 8b/10b decoder decoding the received 10-bit /k28.5/ control code group into an 8-bit data code group (8'hbc) driven on the rx_dataout port. the rx_ctrldetect signal is asserted high synchronous with 8'hbc on the rx_dataout port, indicating that it is a control code group. the rest of the codes received are data code groups /dx.y/. figure 1?73. 8b/10b decoder in single-width mode 9876543210 8b/10b conversion jhgfiedcba msb received last lsb received first 76543210 hgfed cb a ctrl parallel data 1?88 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation 8b/10b decoder in double-width mode the left side of figure 1?72 on page 1?86 shows the 8b/10b decoder in double-width mode. in this mode, two 8b/10b decoders are cascaded for decoding the 20-bit encoded data, as shown in figure 1?75 . the 10-bit lsbyte of the received 20-bit encoded data is decoded first and the ending running disparity is forwarded to the 8b/10b decoder responsible for decoding the 10-bit msbyte. the cascaded 8b/10b decoder decodes the 20-bit encoded data into 16-bit data + 2-bit control identifier. the msb and lsb of the 2-bit control identifier corresponds to the msbyte and lsbyte of the 16-bit decoded data code group. the decoded data is fed to the byte deserializer or the receiver phase compensation fifo (if byte deserializer is disabled). 1 each of the two cascaded 8b/10b decoders is compliant to clause 36 in the ieee802.3 specification. the 8b/10b decoder operates in double-width mode only in basic double-width functional mode. you can enable or disable the 8b/10b decoder depending on your proprietary protocol implementation. figure 1?75 shows a 20-bit code group decoded into 16-bit data and 2-bit control identifier by the 8b/10b decoder in double-width mode. figure 1?74. 8b/10b decoder in control code group detection d3.4 d24.3 d28.5 k28.5 d15.0 d0.0 d31.5 clock rx_ctrldetect datain[9..0 ] rx_dataout[7..0] 83 78 bc bc 0f 00 bf figure 1?75. 8b/10 decoder in 20-bit double-width mode 19 18 17 16 15 14 13 12 11 10 cascaded 8b/10b conversion j 1 h 1 g 1 f 1 i 1 e 1 d 1 c 1 b 1 a 1 msb lsb 15 14 13 13 11 10 9 8 h 1 g 1 f 1 e 1 d 1 c 1 b 1 a 1 ctrl[1..0] 9876543210 jhgfiedcba 7 6543 21 0 hgfed cb a parallel data chapter 1: stratix iv transceiver architecture 1?89 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 control code group detection the cascaded 8b/10b decoder indicates whether the decoded 16-bit code group is a data or control code group on the 2-bit rx_ctrldetect[1:0] port. the rx_ctrldetect[0] signal is driven high or low depending on whether decoded data on the rx_dataout[7:0] port (lsbyte) is a control or data code group, respectively. the rx_ctrldetect[1] signals are driven high or low depending on whether decoded data on the rx_dataout[15:8] port (msbyte) is a control or data code group, respectively. figure 1?76 shows the 8b/10b decoding of the received 10-bit /k28.5/ control code group into 8-bit data code group (8'hbc) driven on the rx_dataout port. the rx_ctrldetect signal is asserted high synchronous with 8'hbc on the rx_dataout port, indicating that it is a control code group. the rest of the codes received are data code groups /dx.y/. byte deserializer the fpga fabric-transceiver interface frequency has an upper limit that is stated in the ?interface frequency? section in the dc and switching characteristics chapter. in functional modes that have a receiver pcs frequency greater than the upper limit stated in the dc and switching characteristics chapter, the parallel received data and status signals cannot be forwarded directly to the fpga fabric because it violates this upper limit for the fpga fabric-transceiver interface frequency. in such configurations, the byte deserializer is required to reduce the fpga fabric-transceiver interface frequency to half while doubling the parallel data width. for example, at 3.2 gbps data rate with a deserialization factor of 10, the receiver pcs datapath runs at 320 mhz. the 10-bit parallel received data and status signals at 320 mhz cannot be forwarded to the fpga fabric because it violates the upper limit for the fpga fabric-transceiver interface frequency. the byte serializer converts the 10-bit parallel received data at 320 mhz into 20-bit parallel data at 160 mhz before forwarding to the fpga fabric. 1 the byte deserializer is required in configurations that exceed the fpga fabric-transceiver interface clock upper frequency limit. it is optional in configurations that do not exceed the fpga fabric-transceiver interface clock upper frequency limit. the byte deserializer operates in two modes: single-width mode double-width mode figure 1?76. 8b/10b decoder 10-bit control code group 00 01 00 clock datain[19:10] datain[9:0] rx_ctrldetect[1:0] rx_dataout[15:0] d3.4 d28.5 d15.0 d3.4 d28.5 d15.0 d3.4 d24.3 16'h8378 16'hbcbc 16'h0f0f 16'h8383 1?90 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation byte deserializer in single-width mode in single-width mode, the byte deserializer receives 8-bit wide data from the 8b/10b decoder or 10-bit wide data from the word aligner (if the 8b/10b decoder is disabled) and deserializes it into 16-bit or 20-bit wide data at half the speed. figure 1?77 shows the byte deserializer in single-width mode. byte deserializer in double-width mode in double-width mode, the byte deserializer receives 16-bit wide data from the 8b/10b decoder or 20-bit wide data from the word aligner (if the 8b/10b decoder is disabled) and deserializes it into 32-bit or 40-bit wide data at half the speed. figure 1?78 shows the byte deserializer in double-width mode. byte ordering block in single-width modes with the 16-bit or 20-bit fpga fabric-transceiver interface, the byte deserializer receives one data byte (8 or 10 bits) and deserializes it into two data bytes (16 or 20 bits). depending on when the receiver pcs logic comes out of reset, the byte ordering at the output of the byte deserializer may or may not match the original byte ordering of the transmitted data. the byte misalignment resulting from byte deserialization is unpredictable because it depends on which byte is being received by the byte deserializer when it comes out of reset. figure 1?79 shows a scenario in which the msbyte and lsbyte of the two-byte transmitter data appears straddled across two word boundaries after getting byte deserialized at the receiver. figure 1?77. byte deserializer in single-width mode or /2 byte deserializer receiver pcs clock dataout[15:0] dataout[19:0] d1 d2 d3 d4 d1 d2 d3 d4 or datain[7:0] datain[9:0] figure 1?78. byte deserializer in double-width mode or /2 receiver pcs clock byte deserializer dataout[31:0] dataout[39:0] d3d4 d7d8 d1d2 d5d6 d3d4 d1d2 d5d6 d7d8 or dataout[15:0] dataout[19:0] chapter 1: stratix iv transceiver architecture 1?91 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 in double-width modes with the 32-bit or 40-bit fpga fabric-transceiver interface, the byte deserializer receives two data bytes (16 or 20 bits) and deserializes it into four data bytes (32 or 40 bits). figure 1?80 shows a scenario in which the two msbytes and lsbytes of the four-byte transmitter data appears straddled across two word boundaries after getting byte deserialized at the receiver. stratix iv gx and gt transceivers have an optional byte ordering block in the receiver datapath that you can use to restore proper byte ordering before forwarding the data to the fpga fabric. the byte ordering block looks for the user-programmed byte ordering pattern in the byte-deserialized data. you must select a byte ordering pattern that you know appears at the lsbyte(s) position of the parallel transmitter data. if the byte ordering block finds the programmed byte ordering pattern in the msbyte(s) position of the byte-deserialized data, it inserts the appropriate number of user-programmed pad bytes to push the byte ordering pattern to the lsbyte(s) position, thereby restoring proper byte ordering. figure 1?79. msbyte and lsbyte of the two-bit transmitter data straddled across two word boundaries transmitter receiver tx_datain[15:8] (msbyte) tx_datain[7:0] (lsbyte) d2 d4 d6 d5 d3 d1 byte serializer xx d1 d2 d3 d4 d5 d6 xx byte deserializer d1 d3 d5 xx xx d2 d4 d6 rx_dataout[15:8] (msbyte) rx_dataout[7:0] (lsbyte) figure 1?80. msbyte and lsbyte of the four-bit transmitter data straddled across two word boundaries transmitter receiver tx_datain[31:16] (msbytes) tx_datain[15:0] (lsbytes) d3d4 d1d2 d7d8 d5d6 byte serializer xx d1d2 d2d4 d5d6 d7d8 xx byte deserializer rx_dataout[31:16] (msbytes) rx_dataout[15:0] (lsbytes) d1d2 d5d6 xx xx d3d4 d7d8 1?92 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation byte ordering block in single-width modes table 1?33 lists the single-width byte ordering block functional modes. 1 for more information about configurations that allow the byte ordering block in the receiver datapath, refer to ?basic single-width mode configurations? on page 1?110 . the quartus ii software automatically configures the byte ordering pattern and byte ordering pad pattern for sonet/sdh oc-48 functional mode. for more information, refer to ?oc-48 byte ordering? on page 1?174 . in basic single-width mode, you can program a custom byte ordering pattern and byte ordering pad pattern in the altgx megawizard plug-in manager. table 1?34 shows the byte ordering pattern length allowed in basic single-width mode. table 1?33. single width functional modes for the byte ordering block functional modes descriptions sonet/sdh oc-48 ? basic single-width mode with: 16-bit fpga fabric-transceiver interface no 8b/10b decoder (8-bit pma-pcs interface) word aligner in manual alignment mode basic single-width mode with: 16-bit fpga fabric-transceiver interface 8b/10b decoder word aligner in automatic synchronization state machine mode table 1?34. byte ordering pattern length in basic single-width mode functional mode byte ordering pattern length byte ordering pad pattern length basic single-width mode with: 16-bit fpga fabric-transceiver interface no 8b/10b decoder word aligner in manual alignment mode 8 bits 8 bits basic single-width mode with: 16-bit fpga fabric-transceiver interface 8b/10b decoder word aligner in automatic synchronization state machine mode 9 bits (1) 9 bits note to tab l e 1 ?3 4 : (1) if a /kx.y/ control code group is selected as the byte ordering pattern, the msb of the 9-bit byte ordering pattern must be 1'b1. if a /dx.y/ data code group is selected as the byte ordering pattern, the msb of the 9-bit byte ordering pattern must be 1'b0. the least significant 8 bits must be the 8b/10b decoded version of the code group used for byte ordering. chapter 1: stratix iv transceiver architecture 1?93 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 byte ordering block in double-width modes table 1?35 lists the double-width byte ordering block functional modes. 1 for more information about configurations that allow the byte ordering block in the receiver datapath, refer to ?basic double-width mode configurations? on page 1?114 . in basic double-width modes, you can program a custom byte ordering pattern and byte ordering pad pattern in the altgx megawizard plug-in manager. table 1?36 shows the byte ordering pattern length allowed in basic double-width mode. table 1?35. double width functional modes for the byte ordering block functional modes descriptions basic double-width mode with: 32-bit fpga fabric-transceiver interface no 8b/10b decoder (16-bit pma-pcs interface) word aligner in manual alignment mode basic double-width mode with: 32-bit fpga fabric-transceiver interface 8b/10b decoder (20-bit pma-pcs interface) word aligner in manual alignment mode basic double-width mode with: 40-bit fpga fabric-transceiver interface no 8b/10b decoder (20-bit pma-pcs interface) word aligner in manual alignment mode table 1?36. byte ordering pattern length in basic double-width mode functional mode byte ordering pattern length byte ordering pad pattern length basic double-width mode with: 32-bit fpga fabric-transceiver interface no 8b/10b decoder (16-bit pma-pcs interface) word aligner in manual alignment mode 16 bits, 8 bits 8 bits basic double-width mode with: 32-bit fpga fabric-transceiver interface 8b/10b decoder (20-bit pma-pcs interface) word aligner in manual alignment mode 18 bits, 9 bits (1) 9 bits basic double-width mode with: 40-bit fpga fabric-transceiver interface no 8b/10b decoder (20-bit pma-pcs interface) word aligner in manual alignment mode 20 bits, 10 bits 10 bits note to tab l e 1 ?3 6 : (1) the 18-bit byte ordering pattern d[17:0] consists of msbyte d[17:9] and lsbyte d[8:0] ; d[17] corresponds to rx_ctrldetect[1] and d[16:9] corresponds to rx_dataout[15:8] . similarly, d[9] corresponds to rx_ctrldetect[0] and d[7:0] corresponds to rx_dataout[7:0] . 1?94 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the byte ordering block modes of operation in both single-width and double-width modes are: word-alignment-based byte ordering user-controlled byte ordering word-alignment-based byte ordering in word-alignment-based byte ordering, the byte ordering block starts looking for the byte ordering pattern in the byte-deserialized data every time it sees a rising edge on the rx_syncstatus signal. after a rising edge on the rx_syncstatus signal, if the byte ordering block finds the first data byte that matches the programmed byte ordering pattern in the msbyte position of the byte-deserialized data, it inserts one programmed pad pattern to push the byte ordering pattern in the lsbyte position. if the byte ordering block finds the first data byte that matches the programmed byte ordering pattern in the lsbyte position of the byte-deserialized data, it considers the data to be byte ordered and does not insert any pad pattern. in either case, the byte ordering block asserts the rx_byteorderalignstatus signal. 1 you can choose word-alignment-based byte ordering by selecting the sync status signal from the word aligner tab in the what do you want the byte ordering to be based on? field in the altgx megawizard plug-in manager. figure 1?81 shows an example of the byte ordering operation in single-width modes. in this example, a is the programmed byte ordering pattern and pad is the programmed pad pattern. the byte deserialized data places the byte ordering pattern a in the msbyte position, resulting in incorrect byte ordering. assuming that a rising edge on the rx_syncstatus signal had occurred before the byte ordering block sees the byte ordering pattern a in the msbyte position, the byte ordering block inserts a pad byte and pushes the byte ordering pattern a in the lsbyte position. the data at the output of the byte ordering block has correct byte ordering as reflected on the rx_byteorderalignstatus signal. if the byte ordering block sees another rising edge on the rx_syncstatus signal from the word aligner, it de-asserts the rx_byteorderalignstatus signal and repeats the byte ordering operation as previously described. figure 1?81. byte ordering in single-width modes a transmitter receiver xx a xx pad a channel tx_datain[15:8] tx_datain[7:0] d2 d3 d5 d4 d1 byte serializer byte deserializer d1 d4 d3 d2 byte ordering rx_byteorderalignstatus d1 d3 d5 d4 d2 rx_dataout[15:8] rx_dataout[7:0] chapter 1: stratix iv transceiver architecture 1?95 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 user-controlled byte ordering unlike word-alignment-based byte ordering, user-controlled byte ordering provides control to the user logic to restore correct byte ordering at the receiver. when enabled, an rx_enabyteord port is available that you can use to trigger the byte ordering operation. a rising edge on the rx_enabyteord port triggers the byte ordering block. after a rising edge on the rx_enabyteord signal, if the byte ordering block finds the first data byte that matches the programmed byte ordering pattern in the msbyte position of the byte-deserialized data, it inserts one programmed pad pattern to push the byte ordering pattern in the lsbyte position. if the byte ordering block finds the first data byte that matches the programmed byte ordering pattern in the lsbyte position of the byte-deserialized data, it considers the data to be byte ordered and does not insert any pad byte. in either case, the byte ordering block asserts the rx_byteorderalignstatus signal. figure 1?82 shows user-controlled byte ordering in basic double-width mode. receiver phase compensation fifo the receiver phase compensation fifo in each channel ensures reliable transfer of data and status signals between the receiver channel and the fpga fabric. the receiver phase compensation fifo compensates for the phase difference between the parallel receiver pcs clock (fifo write clock) and the fpga fabric clock (fifo read clock). the receiver phase compensation fifo operates in one of the following two modes: low latency mode?the quartus ii software automatically configures the receiver phase compensation fifo in low latency mode in all functional modes. in this mode, the fifo is four words deep and the latency through the fifo is two to three parallel clock cycles (pending characterization). high latency mode?in this mode, the fifo is eight words deep and the latency through the fifo is four to five parallel clock cycles (pending characterization). figure 1?82. user-controlled byte ordering in basic double-width mode transmitter receiver channel byte serializer byte deserializer byte ordering rx_enabyteord rx_byteorderalignstatus xxxx tx_datain[31:16] (msbyte) tx_datain[15:0] (lsbyte) d2d3 d4d5 d8d9 d0d1 b1b2 d6d7 b1b2 d8d9 d0d1 d2d3 d4d5 xxxx b1b2 d6d7 b1b2 d8d9 d0d1 p1p2 d4d5 xxxx d2d3 b1b2 d6d7 xxxx b1b2 rx_dataout [31:16] (msbyte) rx_dataout[15:0] (lsbyte) 1?96 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the receiver phase compensation fifo write clock source varies with the receiver channel configuration. table 1?37 shows the receiver phase compensation fifo write clock source in different configurations. the receiver phase compensation fifo read clock source varies depending on whether or not you instantiate the rx_coreclk port in the altgx megawizard plug-in manager. table 1?38 shows the receiver phase compensation fifo read clock source in different configurations. table 1?37. receiver phase compensation fifo write clock source configuration receiver phase compensation fifo write clock without byte serializer with byte serializer non-bonded channel configuration with rate matcher parallel transmitter pcs clock from the local clock divider in the associated channel ( tx_clkout ) divide-by-two version of the parallel transmitter pcs clock from the local clock divider in the associated channel ( tx_clkout ) non-bonded channel configuration without rate matcher parallel recovered clock from the receiver pma in the associated channel ( rx_clkout ) divide-by-two version of the parallel recovered clock from the receiver pma in the associated channel ( rx_clkout ) 4 bonded channel configuration parallel transmitter pcs clock from the central clock divider in the cmu0 of the associated transceiver block ( coreclkout ) divide-by-two version of the parallel transmitter pcs clock from the central clock divider in cmu0 of the associated transceiver block ( coreclkout ) 8 bonded channel configuration parallel transmitter pcs clock from the central clock divider in cmu0 of the master transceiver block ( coreclkout from master transceiver block) divide-by-two version of the parallel transmitter pcs clock from the central clock divider in cmu0 of the master transceiver block ( coreclkout from master transceiver block) table 1?38. receiver phase compensation fifo read clock source configuration receiver phase compensation fifo read clock rx_coreclk port not instantiated rx_coreclk port instantiated (1) non-bonded channel configuration with rate matcher fpga fabric clock driven by the clock signal on the tx_clkout port fpga fabric clock driven by the clock signal on the rx_coreclk port non-bonded channel configuration without rate matcher fpga fabric clock driven by the clock signal on the rx_clkout port fpga fabric clock driven by the clock signal on the rx_coreclk port 4 bonded channel configuration fpga fabric clock driven by the clock signal on the coreclkout port fpga fabric clock driven by the clock signal on the rx_coreclk port 8 bonded channel configuration fpga fabric clock driven by the clock signal on the coreclkout port fpga fabric clock driven by the clock signal on the rx_coreclk port note to tab l e 1 ?3 8 : (1) the clock signal driven on the rx_coreclk port must have 0 ppm frequency difference with respect to the receiver phase compensation fifo write clock. chapter 1: stratix iv transceiver architecture 1?97 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 receiver phase compensation fifo error flag an optional rx_phase_comp_fifo_error port is available in all functional modes to indicate a receiver phase compensation fifo under-run or overflow condition. the rx_phase_comp_fifo_error signal is asserted high when the phase compensation fifo gets either full or empty. this feature is useful to verify a phase compensation fifo under-run or overflow condition as a probable cause of link errors. cmu channel architecture stratix iv gx and gt devices contain two cmu channels? cmu0 and cmu1 ?within each transceiver block that you can configure as a transceiver channel or as a clock generation block. in addition, each cmu channel contains a cmu pll that provides clocks to the transmitter channels within the same transceiver block. figure 1?83 shows the two cmu channels in a transceiver block. figure 1?83. cmu channels in a transceiver block notes to figure 1?83 : (1) clocks are provided to suppor t bonded channel f unctional mode. (2) for more information, refer to the stratix iv transceiver clocking chapter. stratix iv gx transceiver block local clock divider block high-speed serial clock low-speed parallel clock transmitter channel 2 transmitter channel 3 to transmitter pma to transmitter pcs cmu1 pll high-speed clock cmu0 pll high-speed clock high-speed serial clock (1) low-speed parallel clock (1) local clock divider block high-speed serial clock low-speed parallel clock transmitter channel 0 transmitter channel 1 to transmitter pma to transmitter pcs cmu1 channel cmu0 channel input reference clocks (2) input reference clocks (2) high-speed serial clock from x n top high-speed serial clock from x n bottom high-speed serial clock from x n top high-speed serial clock from x n bottom low-speed parallel clock from x n top low-speed parallel clock from x n bottom low-speed parallel clock from x n top low-speed parallel clock from x n bottom 1?98 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the following sections describe the cmu channel building blocks. configuring cmu channels for clock generation each cmu channel has a cmu pll that generates high-speed serial transceiver clocks when the cmu channel is configured as a cmu. the cmu0 clock divider block also generates the low-speed parallel transceiver clock for 4, 8, and n bonded mode configurations such as xaui, basic 4, basic 8, and basic (pma-direct) n. the cmu0 channel has additional capabilities to support bonded protocol functional modes such as basic 4, xaui, and pci express (pipe). use the altgx megawizard plug-in manager to select these functional modes (to enable basic 4 functional mode, select the 4 option in basic mode). for more information, refer to ?functional modes? on page 1?107 . 1 for stratix iv gt devices, you can use the cmu pll to generate transceiver clocks at data rates between 2.488 gbps and 11.3 gbps. cmu0 channel the cmu0 channel, shown in figure 1?84 , contains the following blocks: cmu0 pll (refer to ?cmu0 clock divider? on page 1?100 ) cmu0 clock divider (refer to ?cmu clock divider? on page 1?105 ) figure 1?84. cmu0 channel with the cmu0 pll and cmu0 clock divider notes to figure 1?84 : (1) to provide clocks for its pma and pcs blo cks in non-bonded functional modes (for example, gige functional mode), the transmitter channel uses the transmitter local clock divider to divide this high-speed clock output. (2) used in xaui, basic 4, and pci express (pipe) 4 functiona l modes. in pci express (pipe) 8 functional mode, only the cmu0 channel of the master transceiver block provides clock output to all eight transceiver channels configured in pci express (pipe) functional mo de. 6 pll_powerdown pll cascade clock global clock line dedicated refclk0 dedicated refclk1 itb clock lines cmu0 pll input reference clock cmu0 pll cmu0 pll high-speed clock (1) cmu0 channel cmu1 pll high-speed clock cmu0 clock divider pcie_gen2switch (to pci express rate switch controller block in the ccu) pcie_gen2switch_done (to pci express rate switch controller block in the ccu) high-speed serial clock for bonded modes (2) low-speed parallel clock for bonded modes pll_powerdown pll_locked chapter 1: stratix iv transceiver architecture 1?99 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 cmu0 pll figure 1?85 shows the cmu0 pll. you can select the input reference clock to the cmu0 pll from multiple clock sources: pll cascade clock?the output from the general purpose plls in the fpga fabric global clock line?the input reference clock from the dedicated clk pins are connected to the global clock line refclk0 ?dedicated refclk in the transceiver block refclk1 ?dedicated refclk in the transceiver block inter transceiver block lines?the itb lines connect refclk0 and refclk1 of all other transceiver blocks on the same side of the device the cmu0 pll generates the high-speed clock from the input reference clock. the pfd tracks the vco output with the input reference clock. f for more information about transceiver input reference clocks, refer to the stratix iv transceiver clocking chapter. the vco in the cmu0 pll is half rate and runs at half the serial data rate. to generate the high-speed clock required to support a native data rate range of 600 mbps to 8.5 gbps, the cmu0 pll uses two multiplier blocks (/m and /l) in the feedback path (shown in figure 1?85 ). 1 the altgx megawizard plug-in manager provides the list of input reference clock frequencies based on the data rate you select. the quartus ii software automatically selects the /m and /l settings based on the input reference clock frequency and serial data rate. f the cmu0 and cmu1 plls have a dedicated pll_locked signal that is asserted to indicate that the cmu pll is locked to the input reference clock. you can use the pll_locked signal in your transceiver reset sequence, as described in the reset control and power down chapter. figure 1?85. cmu0 pll note to figure 1?85 : (1) the inter transceiver block (itb) clock lines are the maximum value. the actual number of itb lines in your device depends o n the number of transceiver blocks on one side of your device. pfd 6 cmu0 pll pll cascade clock global clock line dedicated refclk0 dedicated refclk1 itb clock lines (1) cmu0 pll input reference clock /m charge pump + loop filter v co /l cmu0 high-speed clock /1, /2, /4, /8 1?100 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation pll bandwidth setting the bandwidth of a pll is the measure of its ability to track input clock and jitter. it is determined by the ?3 db frequency of the closed-loop gain of the pll. there are three bandwidth settings: high, medium, and low. you can program the pll bandwidth setting using the altgx megawizard plug-in manager. the high bandwidth setting filters out internal noise from the vco because it tracks the input clock above the frequency of the internal vco noise. with the low bandwidth setting, if the noise on the input reference clock is greater than the internal noise of the vco, the pll filters out the noise above the ?3 db frequency of the closed-loop gain of the pll. the medium bandwidth setting is a compromise between the high and low bandwidth settings. the ?3 db frequencies for these settings can vary because of the non-linear nature and frequency dependencies of the circuit. power down cmu0 pll yo u c a n p o we r d o w n t he cmu0 pll by asserting the pll_powerdown signal. f for more information, refer to the reset control and power down chapter. cmu0 clock divider the high-speed clock output from the cmu0 pll is forwarded to two clock dividers: the cmu0 clock divider and the transmitter channel local clock divider. use the clock divider only in bonded channel functional modes. in non-bonded functional modes (such as gige functional mode), the local clock divider divides the high-speed clock to provide clocks for its pcs and pma blocks. this section only describes the cmu0 clock divider. f for more information about the local clock divider, refer to the ?transceiver channel datapath clocking? section in the stratix iv transceiver clocking chapter. you can configure the cmu0 clock divider shown in figure 1?86 to select the high-speed clock output from the cmu0 or cmu1 plls. the cmu1 pll is present in the cmu1 channel. figure 1?86. cmu0 clock divider pcie_gen2switch_done pcie_gen2switch cmu0 high-speed clock output cmu1 high-speed clock output cmu0 clock divider block /n (1, 2, 4) pcie rateswitch circuit /s (4, 5, 8, 10) coreclkout to fpga fabric (for bonded modes) high-speed serial clock (for bonded modes) low-speed parallel clock for transmitter channel pcs (for bonded modes) /2 1 0 chapter 1: stratix iv transceiver architecture 1?101 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 high-speed serial clock generation the /n divider receives the high-speed clock output from one of the cmu plls and produces a high-speed serial clock. use this clock for bonded functional modes such as basic 4/8, xaui, and pci express (pipe) 4/8 configurations. in xaui and basic 4/8 modes, the quartus ii software chooses the path (shown by ?1? in the mux) and provides the high-speed serial clock to all the transmitter channels within the transceiver block. in pci express (pipe) 4 mode, the clock path through the pci express (pipe) rateswitch circuit block is selected. this high-speed serial clock is provided to all the transmitter channels. in pci express (pipe) 8 mode and basic 8 mode, only the cmu0 clock divider of the master transceiver block provides the high-speed serial clock to all eight channels. in pci express (pipe) 1 mode, the cmu0 clock divider does not provide a high-speed serial clock. instead, the local clock divider block in the transmitter channel receives the cmu0 or cmu1 pll high-speed clock output and generates the high-speed serial clock to its serializer. f for more information about the clock from the master transceiver block, refer to the stratix iv transceiver clocking chapter. pcie rateswitch circuit the pcie rateswitch circuit is enabled only in pci express (pipe) 4 mode. in pci express (pipe) 8 mode, the pcie rateswitch circuit of the cmu0 clock divider of the master transceiver block is active. there are two paths in the pcie rateswitch circuit. one path divides the /n output by two. the other path forwards the /n divider output. when you set the rateswitch port to 0 , the pci express (pipe) rateswitch controller (in the ccu) signals the pcie rateswitch circuit to select the divide by /2 to provide a high-speed serial clock for the gen1 (2.5 gbps) data rate. when you set the rateswitch port to 1 , the /n divider output is forwarded, providing a high-speed serial clock for the gen2 (5 gbps) data rate to the transmitter channels. 1 the pcie rateswitch circuit performs the rateswitch operation only for the transmitter channels. for the receiver channels, the rateswitch circuit within the receiver cdr performs the rateswitch operation. the pcie rateswitch circuit is controlled by the pci express (pipe) rateswitch controller in the ccu. the pci express (pipe) rateswitch controller asserts the pipephydonestatus signal for one clock cycle after the rateswitch operation is completed for both the transmit and receive channels. figure 1?87 shows the timing diagram for the rateswitch operation. for more information about pci express (pipe) functional mode rate switching, refer to ?pci express (pipe) gen2 (5 gbps) support? on page 1?138 . 1?102 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation 1 when creating a pci express (pipe) gen2 configuration, configure the cmu pll to 5 gbps. this helps to generate the 2.5 gbps and 5 gbps high-speed serial clock using the rateswitch circuit. low-speed parallel clock generation the /s divider receives the clock output from the /n divider or pcie rateswitch circuit (only in pci express [pipe] mode) and generates the low-speed parallel clock for the pcs block of all transmitter channels and coreclkout for the fpga fabric. if the byte serializer block is enabled in bonded channel modes, the /s divider output is divided by the /2 divider and sent out as coreclkout to the fpga fabric. the quartus ii software automatically selects the /s values based on the deserialization width setting (single-width or double-width mode) that you select in the altgx megawizard plug-in manager. for more information about single-width or double-width mode, refer to ?transceiver channel architecture? on page 1?12 . 1 the quartus ii software automatically selects all the divider settings based on the input clock frequency, data rate, deserialization width, and channel width settings. figure 1?87. rateswitch in pci express (pipe) mode (note 1) note to figure 1?87 : (1) time t1 is pending characterization. rateswitch pipephydonestatus t1 t1 low-speed parallel clock 250 mhz (gen 1) 500 mhz (gen 2) 250 mhz (gen 1) chapter 1: stratix iv transceiver architecture 1?103 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 cmu1 channel the cmu1 channel, shown in figure 1?88 , contains the cmu1 pll that provides the high-speed clock to the transmitter channels within the transceiver block. the cmu1 pll is similar to the cmu0 pll (refer to ?cmu0 pll? on page 1?99 ). the cmu1 pll generates the high-speed clock that is only used in non-bonded functional modes. the transmitter channels within the transceiver block can receive a high-speed clock from either of the two cmu plls and uses local dividers to provide clocks to its pcs and pma blocks. f for more information about using two cmu plls to configure transmitter channels, refer to the configuring multiple protocols and data rates in a transceiver block chapter. power down cmu1 pll yo u c a n p o we r d o w n t he cmu1 pll by asserting the pll_powerdown signal. f for more information, refer to the reset control and power down chapter. configuring cmu channels as transceiver channels you can configure the two cmu channels in the transceiver block of stratix iv gx and gt devices as full-duplex pma-only channels to run between 600 mbps and 6.5 gbps. for stratix iv gt devices, you can configure both cmu0 and cmu1 channels in each transceiver block as full-duplex pma-only channels supporting data rates between 2.488 gbps and 6.5 gbps. figure 1?88. cmu1 channel (grayed area shows the inactive block) 6 pll cascade clock global clock line dedicated refclk0 dedicated refclk1 itb clock lines cmu1 pll input reference clock cmu1 pll cmu1 channel cmu1 pll high-speed clock cmu1 clock divider pll_powerdown pll_locked 1?104 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?89 shows the functional blocks that are enabled to support the transceiver channel functionality. 1 the cmu pll is configured as a cdr to recover data. the dedicated input reference clock pin is configured to receive serial data. when configured as a full-duplex or receiver-only channel, the cmu pll performs the functionality of the receiver cdr and recovers clock from the incoming serial data. the high-speed serial and low-speed parallel recovered clocks are used by the deserializer in the cmu channel and the deserialized data is forwarded directly to the fpga fabric. when configured as a full-duplex or transmitter-only channel, the serializer in the cmu channel serializes the parallel data from the fpga fabric and drives the serial data to the transmitter buffer. table 1?39 shows the pins that are used as transmit and receive serial pins. figure 1?89. functional blocks enabled to support transceiver channel functionality cmu pll configured as rx cdr serializer deserializer high-speed clock from the adjacent cmu channel x4 clock line from xn top clock line from xn bottom clock line from the fpga fa b ric to the fpga fa b ric cmu channel cmu clock divider b lock (/1, /2, /4) tx_data_out rx_data_in table 1?39. transmit and receive serial pins (part 1 of 2) pins (1) when a cmu channel is configured as a transceiver channel when a cmu channel is configured for clock generation refclk_[l,r][0,2,4,6]p, gxb_cmurx_[l_r][0,2,4,6]p (2) receive serial input for cmu channel0 input reference clocks gxb_tx_[l,r][0,2,4,6] (2) transmit serial output for cmu channel0 not available for use refclk_[l,r][1,3,5,7]p, gxb_cmurx_[l_r][1,3,5,7]p (3) receive serial input for cmu channel1 input reference clocks chapter 1: stratix iv transceiver architecture 1?105 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 interpret the pins column as follows: for pins refclk_[l,r][0,2,4,6]p and gxb_cmurx_[l_r][0,2,4,6] , the ?l, r? indicates the left and right side and the ?0, 2, 4, 6? indicates the different pins. for example, a pin on the left side with index 0 is named: refclk_l0p, gxb_cmurx_l0p. 1 the receiver serial input pins are hardwired to their corresponding cmu channels. for more information, refer to the notes to table 1?39 . serializer and deserializer the serializer and deserializer convert the serial-to-parallel data on the transmitter and receiver side, respectively. the altgx megawizard plug-in manager provides the basic (pma direct) functional mode (with a none and n option) to configure a transceiver channel to enable the transmitter serializer and receiver deserializer. to configure a cmu channel as a transceiver channel, you must use this functional mode. the input data width options to serializer/from deserializer for a channel configured in this mode are 8, 10, 16, and 20. f to understand the maximum fpga fabric-transceiver interface clock frequency limits, refer to the ?transmitter channel datapath clocking? section in the stratix iv transceiver clocking chapter. cmu clock divider when you configure a cmu channel in basic (pma direct) 1 mode, the cmu clock divider divides the high-speed clock from the other cmu channel (used as a clock generation unit) within the same transceiver block and provides the high-speed serial clock and low-speed parallel clocks to the transmitter side of the cmu channel. the cmu clock divider can divide the high-speed clock by /1, /2, and /4. gxb_tx_[l,r][1,3,5,7]p (3) transmit serial output for cmu channel1 not available for use notes to ta bl e 1? 39 : (1) these indexes are for the stratix iv gx and gt device with the maximum number of transceiver blocks. for exact information a bout how many of these pins are available for a specific device family, refer to the stratix iv device family overview chapter. (2) pins 0,2,4,6 are hardwired to cmu channel0 in the corresponding transceiver blocks. (3) pins 1,3,5,7 are hardwired to cmu channel1 in the corresponding transceiver blocks. table 1?39. transmit and receive serial pins (part 2 of 2) pins (1) when a cmu channel is configured as a transceiver channel when a cmu channel is configured for clock generation 1?106 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation clocks for the transmitter serializer when you configure the cmu channel as a transceiver channel, the clocks for the transmitter side is provided by one of these sources: the other cmu channel in the same transceiver block that is configured as a clock multiplication unit from cmu channel0 on the other transceiver block on the same side of the device through the n clock line (the n_top or n_bottom clock line). if you configure a cmu channel in basic (pma direct) n mode, you can use this clocking option from one of the atx pll blocks on the same side of the device through the n clock line (the n_top or n_bottom clock line) input reference clocks for the receiver cdr when you configure a cmu channel as a transceiver channel, there are multiple sources of input reference clocks for the receiver cdr: from adjacent refclks within the same transceiver block, if the adjacent cmu channel is not used as a transceiver channel from the refclk of adjacent transceiver blocks on the same side of the device, if the corresponding cmu channels are not used as transceiver channels. for refclk connections to the cmu channel from the global clock lines and pll cascade network, refer to table 1?6 on page 1?14 . f for more information, refer to the ?input reference clocking? section of the stratix iv transceiver clocking chapter. clocks for the receiver deserializer the cdr provides high-speed serial and low-speed parallel clocks to the receiver deserializer from the recovered data. other cmu channel features the cmu channels provide the following features: analog control options?differential output voltage ( v od ), pre-emphasis, equalization, and dc gain settings present in the regular channels are also available in the cmu channels. oct?cmu channels can have an oct feature. the allowed termination values are the same as regular channels (85, 100, 120, and 150 ). loopback?the available loopback options are serial, reverse serial (pre-cdr), and reverse serial (cdr) loopback. for more information about analog controls and oct, refer to ?transmitter output buffer? on page 1?30 and ?receiver input buffer? on page 1?36 . for information about loopback, refer to ?loopback modes? on page 1?188 . chapter 1: stratix iv transceiver architecture 1?107 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 dynamic reconfiguration of the cmu channel analog controls f for the dynamic reconfiguration capabilities of the cmu channels in basic (pma direct) 1/n configurations, refer to the stratix iv dynamic reconfiguration chapter. functional modes table 1?40 list the transceiver functional modes you can use to configure the stratix iv gx and gt devices using the altgx megawizard plug-in manager. table 1?41 list the transceiver functional modes you can use to configure the stratix iv gt devices using the altgx megawizard plug-in manager. table 1?40. functional modes for the stratix iv gx and gt devices functional mode data rate refer to basic single width 600 mbps to 3.75 gbps ?basic single-width mode configurations? on page 1?110 basic double width 1 gbps to 8.5 gbps ?basic double-width mode configurations? on page 1?114 pci express (pipe) gen1 at 2.5 gbps gen2 at 5 gbps ?pci express (pipe) mode configurations? on page 1?125 xaui 3.125 gbps up to higig at 3.75 gbps ?xaui mode datapath? on page 1?154 gige 1.25 gbps ?gige mode datapath? on page 1?164 serial rapidio 1.25 gbps 2.5 gbps 3.125 gbps ?serial rapidio mode? on page 1?180 sonet/sdh oc-12 oc-48 ?sonet/sdh frame structure? on page 1?169 sdi hd at 1.485/1.4835 gbps 3g at 2.97/2.967 gbps ?sdi mode datapath? on page 1?178 (oif) cei phy interface >4.976 gbps to 6.375 gbps ?(oif) cei phy interface mode datapath? on page 1?180 table 1?41. functional modes for the stratix iv gt devices (part 1 of 2) functional mode data rate refer to basic single width 2.488 gbps to 3.75 gbps ?basic single-width mode configurations? on page 1?110 basic double width 2.488 gbps to 11.3 gbps ?basic double-width mode configurations? on page 1?114 basic (pma-direct) single-width 2.488 gbps to 3.25 gbps ?basic (pma direct) 1 configuration? on page 1?187 basic (pma-direct) double-width 2.488 gbps to 6.5 gbps ?basic (pma direct) n configuration? on page 1?187 xaui 3.125 gbps up to higig at 3.75 gbps ?xaui mode datapath? on page 1?154 1?108 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation basic functional mode the stratix iv gx and gt transceiver datapaths are extremely flexible in basic functional mode. to configure the transceivers in basic functional mode, you must select basic in the which protocol will you be using? option of the altgx megawizard plug-in manager. basic functional mode can be further sub-divided into the following two functional modes: basic single-width mode basic double-width mode you can configure the transceiver in basic single-width mode by selecting single in the what is the deserializer block width? option in the altgx megawizard plug-in manager. you can configure the transceiver in basic double-width mode by selecting double in the what is the deserializer block width? option in the altgx megawizard plug-in manager. table 1?42 shows the stratix iv gx and gt pcs-pma interface widths and data rates supported in basic single-width and double-width modes. serial rapidio 2.5 gbps 3.125 gbps ?serial rapidio mode? on page 1?180 sonet/sdh oc-48 oc-96 ?sonet/sdh frame structure? on page 1?169 sdi 3g at 2.97/2.967 gbps ?sdi mode datapath? on page 1?178 (oif) cei phy interface > 4.976 gbps to 6.375 gbps ?(oif) cei phy interface mode datapath? on page 1?180 table 1?41. functional modes for the stratix iv gt devices (part 2 of 2) functional mode data rate refer to table 1?42. pcs-pma interface widths and data rates in basic single-width and double-width modes for stratix iv gx and gt devices basic functional mode supported data rate range (1) pma-pcs interface width basic single-width mode 600 mbps to 3.75 gbps 8 bit, 10 bit basic double-width mode 1 gbps to 8.5 gbps 16 bit, 20 bit note to tab l e 1 ?4 2 : (1) the data rate range supported in basic single-width and double-width modes varies depending on whether or not you use the byte serializer/deserializer. for more information, refer to ?basic single-width mode configurations? on page 1?110 and ?basic double-width mode configurations? on page 1?114 . chapter 1: stratix iv transceiver architecture 1?109 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 table 1?43 shows the stratix iv gt pcs-pma interface widths and data rates supported in basic single-width and double-width modes. low latency pcs datapath the altgx megawizard plug-in manager provides an enable low latency pcs mode option when configured in basic single-width or basic double-width mode. if you select this option, the following transmitter and receiver channel pcs blocks are bypassed to yield a low latency pcs datapath: 8b/10b encoder and decoder word aligner deskew fifo rate match (clock rate compensation) fifo byte ordering in low latency pcs modes, the transmitter and receiver phase compensation fifos are always enabled. depending on the targeted data rate, you can optionally bypass the byte serializer and deserializer blocks. for more information, refer to ?basic single- width mode configurations? on page 1?110 and ?basic double-width mode configurations? on page 1?114 . 1 the pcs latency in basic single-width and basic double-width modes with and without the low latency pcs mode option is pending characterization. 1 basic double-width mode configurations at data rates of > 6.5 gbps are only allowed in low-latency pcs bypass mode. table 1?43. pcs-pma interface widths and data rates supported in basic single-width and double-width modes for stratix iv gt devices (note 1) basic functional mode supported data rate range pma-pcs interface width basic single-width mode 2.488 gbps to 3.75 gbps 8-bit, 10-bit basic double-width mode 2.488 gbps to 11.3 gbps 16-bit, 20-bit note to tab l e 1 ?4 3 : (1) the data rate range supported in basic single-width and double-width modes varies depending on whether or not you use the byte serializer/deserializer. for more information, refer to ?basic single-width mode configurations? on page 1?110 and ?basic double-width mode configurations? on page 1?114 . 1?110 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation basic single-width mode configurations figure 1?90 shows stratix iv gx transceiver configurations allowed in basic single-width functional mode with an 8-bit pma-pcs interface. figure 1?91 shows stratix iv gt transceiver configurations allowed in basic single-width functional mode with an 8-bit pma-pcs interface. figure 1?90. transceiver configurations in basic single-width mode with an 8-bit pma-pcs interface for stratix iv gx devices note to figure 1?90 : (1) the maximum data rate specification shown in figure 1?90 is valid only for the -2 (fastest) speed grade devices. for data rate specifications for other speed grades offered, refer to the dc and switching characteristics chapter. disabled disabled disabled rate match fifo byte serdes byte ordering stratix iv gx configurations basic (1) (1) single width double width protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit enabled disabled disabled disabled enabled disabled enabled disabled disabled disabled disabled disabled enabled disabled enabled disabled disabled fpga fabric - transceiver interface frequency disabled disabled functional modes pma-pcs interface width pma-pcs interface width data rate (gbps) channel bonding low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder data rate (gbps) fpga fabric-transceiver interface width fpga fabric-transceiver interface frequency (mhz) 75 - 250 37.5 - 195.3125 37.5 - 195.3125 75 - 250 37.5 - 195.3125 8-bit 8-bit 16-bit 16-bit 16-bit 0.6 - 2.0 0.6 - 3.125 0.6 - 2.0 0.6 - 3.125 manual alignment (16-bit) bit-slip (16-bit) basic single-width 8-bit pma-pcs interface width 0.6 - 3.2 x1, x4, x8 0.6 - 2.0 0.6 - 3.2 8-bit 16-bit 75 - 250 37.5 - 200 deterministic latency -bit 20-bit 10 fpga fabric transceiver interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 5 -6 4 - 5.5 4 - 5.5 5 -6 4 - 5.5 4 - 5 4 - 5.5 11-13 7 - 9 7 - 9 11 - 13 7 - 9 3 - 4 3 - 4.5 chapter 1: stratix iv transceiver architecture 1?111 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?91. transceiver configurations in basic single-width mode with an 8-bit pma-pcs interface for stratix iv gt devices note to figure 1?91 : (1) the maximum data rate specification shown in figure 1?91 is valid only for the -2 (fastest) speed grade devices. for data rate specifications for other speed grades offered, refer to the dc and switching characteristics chapter. word aligner (pattern length) basic single width 8-bit pma-pcs interface width disabled manual alignment (16-bit) disabled 8b/10b encoder /decoder rate match fifo byte serdes byte ordering stratix iv gt configurations basic single width double width functional modes protocol xaui srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 8-bit 16-bit 10-bit pma-pcs/fabric interface width pma-pcs/fabric interface width low-latency pcs enabled bit-slip (16-bit) disabled disabled disabled enabled enabled disabled disabled disabled enabled data rate (gbps) 2.488 ? 3.2 channel bonding x1, x4, x8 disabled enabled disabled fpga fabric- transceiver interface width 16-bit 16-bit 16-bit data rate (gbps) 2.488 ? 3.125 2.488 ? 3.125 fpga fabric- transceiver interface frequency 155.5 ? 195.3125 fpga fabric- transceiver interface frequency (mhz) 155.5 ? 195 .3125 2.488 ? 3.2 disabled 16-bit 155.5 - 200 155.5 ? 195.3125 (1) (1) pipe 10-bit deterministic latency 10-bit 20-bit fpga fabric interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 4 - 5.5 4 - 5.5 4 - 5.5 4 - 5.5 7 - 9 7 - 9 7 - 9 3 - 4.5 1?112 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?92 shows stratix iv gx transceiver configurations allowed in basic single-width functional mode with a 10-bit pma-pcs interface. figure 1?93 shows stratix iv gt transceiver configurations allowed in basic single-width functional mode with a 10-bit pma-pcs interface. figure 1?92. transceiver configurations in basic single-width mode with a 10-bit pma-pcs interface for stratix iv gx devices note to figure 1?92 : (1) the maximum data rate specification shown in figure 1?92 is valid only for the -2 (fastest) speed grade devices. for data rate specifications for other speed grades offered, refer to the dc and switching characteristics chapter. disabled disabled disabled rate match fifo byte serdes byte ordering stratix iv gx configurations basic single width double width protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit enabled disabled disabled disabled disabled disabled channel bonding fpga fabric - transceiver interface frequency enabled disabled enabled disabled enabled disabled disabled disabled disabled disabled enabled enabled disabled enabled disabled enabled disabled enabled disabled disabled disabled disabled disabled disabled disabled disabled enabled disabled enabled disabled enabled disabled disabled disabled disabled enabled disabled disabled disabled enabled disabled disabled functional modes pma-pcs interface width pma-pcs interface width data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder data rate (gbps) fpga fabric-transceiver interface width fpga fabric-transceiver interface frequency (mhz) 30 - 187.5 30 - 187.5 30 - 187.5 30 - 187.5 30 - 187.5 30 - 187.5 30 - 187.5 30 - 187.5 60 - 250 60 - 250 60 - 250 60 - 250 60 - 250 60 - 250 60 - 250 10-bit 10-bit 10-bit 16-bit 16-bit 16-bit 16-bit 16-bit 8-bit 8-bit 8-bit 8-bit 20-bit 20-bit 20-bit 0.6 - 2.5 0.6 - 2.5 0.6 - 2.5 0.6 - 2.5 0.6 - 2.5 0.6 - 2.5 0.6 - 2.5 0.6 - 3.75 0.6 - 3.75 0.6 - 3.75 0.6 - 3.75 0.6 - 3.75 0.6 - 3.75 0.6 - 3.75 automatic synchronization state machine (7-bit, 10-bit) bit-slip (7-bit, 10-bit) (1) (1) manual alignment (7-bit, 10-bit) x1, x4, x8 0.6 - 3.75 basic single-width 10-bit pma-pcs interface width 0.6 - 2.5 0.6 - 3.75 10-bit 20-bit 60 - 250 30 - 187.5 deterministic latency 10-bit 20-bit fpga fabric interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 4 - 5.5 5 - 6 11.5 - 14.5 6 - 8 20 - 24 3 - 4. 5 3 - 4 5 - 6 5 - 6 5 - 6 4 - 5.5 4 - 5.5 4 - 5 5 - 6 4 - 5.5 5 - 6 4 - 5.5 4 - 5.5 4 - 5.5 5 - 6 4 - 5 4 - 5.5 6 - 8 9 - 11 6 - 8 9 - 11 6 - 8 9 - 11 6 - 8 9 - 11 6 - 8 9 - 11 6 - 8 9 - 11 chapter 1: stratix iv transceiver architecture 1?113 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?93. transceiver configurations in basic single-width mode with a 10-bit pma-pcs interface for stratix iv gt devices note to figure 1?93 : (1) the maximum data rate specification shown in figure 1?93 is valid only for the -2 (fastest) speed grade devices. for data rate specifications for other speed grades offered, refer to the dc and switching characteristics chapter. word aligner (pattern length) basic single width 10-bit pma-pcs interface width disabled manual alignment (7-bit, 10-bit) disabled disabled 8b/10b encoder /decoder rate match fifo byte serdes byte ordering stratix iv gt configurations basic single width double width functional modes 8-bit 10-bit 16-bit 20-bit pma-pcs/fabric interface width pma-pcs interface width low-latency pcs enabled bit-slip (7-bit, 10-bit) disabled disabled disabled disabled disabled data rate (gbps) 2.488 ? 3.75 channel bonding x1, x4, x8 fpga fabric- transceiver interface width 10-bit data rate (gbps) 2.488 ? 2.5 fpga fabric- transceiver interface frequency fpga fabric- transceiver interface frequency (mhz) 2.488 ? 2.5 automatic synchronization state machine (7-bit, 10-bit) enabled disabled enabled disabled enabled disabled disabled disabled disabled disabled enabled enabled disabled enabled disabled enabled disabled enabled 2.488 ? 3.75 2.488 ? 2.5 2.488 ? 3.75 2.488 ? 2.5 2.488 ? 3.75 2.488 ? 2.5 2.488 ? 3.75 disabled disabled disabled disabled disabled disabled disabled 20-bit 8-bit 16-bit 10-bit 20-bit 8-bit 16-bit 248 .8 - 250 124.4 ? 187.5 248 .8 - 250 124 .4 ? 187.5 248.8 - 250 124.4 ? 187.5 248.8 - 250 124.4 ? 187.5 disabled enabled disabled enabled disabled enabled 2.488 ? 2.5 2.488 ? 3.75 2.488 ? 2.5 2.488 ? 3.75 2.488 ? 2.5 2.488 ? 3.75 disabled disabled disabled disabled enabled disabled disabled 10-bit 20-bit 8-bit 16-bit 16-bit 8-bit 16-bit 248.8 - 250 124 .4 ? 187.5 248.8 - 250 124.4 ? 187 .5 124.4 ? 187.5 248.8 - 250 124.4 ? 187 .5 disabled enabled 2.488 ? 3.75 disabled disabled 10-bit 20-bit 248.8 - 250 124.4 ? 187.5 protocol xaui srio sonet /sdh (oif) cei sdi 10-bit 10-bit 8-bit 16-bit 10-bit 8 (1) (1) deterministic latency 10-bit 20-bit pipe 10-bit fpga fabric interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 4 - 5 4 - 5.5 4 - 5 4 - 5.5 4 - 5 4 - 5.5 4 - 5.5 5 - 6 5 - 6 5 - 6 4 - 5.5 9 - 11 6 - 8 9 - 11 6 - 8 9 - 11 5 - 6 4 - 5.5 4 - 5 5 - 6 4 - 5.5 6 - 8 9 - 11 6 - 8 9 - 11 6 - 8 11.5 - 14.5 6 - 8 20 - 24 3 - 4. 5 3 - 4 5 - 6 4 - 5.5 4 - 5.5 4 - 5.5 5 - 6 4 - 5 4 - 5.5 6 - 8 9 - 11 1?114 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation basic double-width mode configurations figure 1?94 shows stratix iv gx transceiver configurations allowed in basic double-width functional mode with a 16-bit pma-pcs interface. figure 1?95 shows stratix iv gt transceiver configurations allowed in basic double-width functional mode with a 16-bit pma-pcs interface. figure 1?94. transceiver configurations in basic double-width mode with a 16-bit pma-pcs interface for stratix iv gx devices notes to figure 1?94 : (1) the maximum data rate specification shown in figure 1?94 is valid only for the -2 (fastest) speed grade devices. for data rate specifications for other speed grades offered, refer to the dc and switching characteristics chapter. (2) the byte ordering block is available only if you select the word alignment pattern length of 16 or 32 bits. disabled disabled (1) (1) disabled rate match fifo byte serdes byte ordering stratix iv gx configurations basic single- width double- width protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit enabled disabled disabled disabled enabled disabled enabled disabled disabled disabled disabled disabled enabled channel bonding disabled enabled disabled disabled fpga fabric - transceiver interface frequency disabled disabled functional modes pma-pcs interface width pma-pcs interface width data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder data rate (gbps) fpga fabric-transceiver interface width fpga fabric-transceiver interface frequency (mhz) 62.5 - 250 62.5 - 250 31.25 - 203.125 31.25 - 203.125 31.25 - 203.125 16-bit 16-bit 32-bit 32-bit 32-bit 1.0 - 4.0 1.0 - 4.0 1.0 - 6.5 1.0 - 6.5 manual alignment (8-, 16-, 32-bit) bit-slip (8-, 16-, 32-bit) x1, x4, x8 1.0 - 8.5 basic double-width 16-bit pma-pcs interface width 1.0 - 4.0 1.0 - 8.5 32-bit 16-bit 31.25 - 265.625 62.5 - 250 (2) deterministic latency 10-bit 20-bit interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 5 - 6 4 - 5.5 11 - 13 6.5 - 8.5 6.5 - 8.5 4 - 5.5 5 - 6 4 - 5.5 11 - 13 6.5 - 8.5 4 - 5 4 - 5.5 3 - 4 3 - 4.5 chapter 1: stratix iv transceiver architecture 1?115 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?95. transceiver configurations in basic double-width mode with a 16-bit pma-pcs interface for stratix iv gt devices note to figure 1?95 : (1) the maximum data rate specification shown in figure 1?95 is valid only for the -2 (fastest) speed grade devices. for data rate specifications for other speed grades offered, refer to the dc and switching characteristics chapter. word aligner (pattern length) basic double width 16-bit pma-pcs interface width disabled manual alignment (8-, 16-, 32-bit) disabled disabled 8b/10b encoder /decoder rate match fifo byte serdes byte ordering stratix iv gt configurations basic single width double width functional modes 8-bit 10-bit 16-bit 20-bit pma-pcs/fabric interface width pma-pcs interface width low-latency pcs enabled bit-slip (8-, 16-, 32-bit) disabled disabled disabled enabled disabled enabled disabled disabled disabled disabled disabled enabled data rate (gbps) 1.0 ? 8.5 channel bonding x1, x4, x8 disabled enabled (note 1) disabled disabled fpga fabric- transceiver interface width 16-bit 32-bit 32-bit 16-bit 32-bit data rate (gbps) 2.488 ? 4.0 2.488 ? 6.5 2.488 ? 4.0 2.488 ? 6.5 fpga fabric- transceiver interface frequency fpga fabric- transceiver interface frequency (mhz) 155 .5 - 250 77.75 ? 203.125 2.488 ? 4.0 2.488 ? 8.5 disabled disabled 32-bit 16-bit 77.75 ? 203.125 155 .5 - 250 77.75 ? 203.125 155.5 - 250 77.75 ? 265.625 protocol xaui srio sonet /sdh (oif) cei sdi 10-bit 10-bit 8-bit 16-bit 10-bit (1) (1) deterministic latency 10-bit 20-bit pipe 10-bit interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 5 - 6 4 - 5.5 11 - 13 6.5 - 8 .5 6.5 - 8.5 4 - 5.5 5 - 6 4 - 5.5 11 - 13 6.5 - 8.5 4 - 5 4 - 5.5 3 - 4 3 - 4.5 1?116 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?96 shows stratix iv gx transceiver configurations allowed in basic double-width functional mode with a 20-bit pma-pcs interface. figure 1?97 shows stratix iv gt transceiver configurations allowed in basic double-width functional mode with a 20-bit pma-pcs interface. figure 1?96. transceiver configurations in basic double-width mode with a 20-bit pma-pcs interface for stratix iv gx devices notes to figure 1?96 : (1) the maximum data rate specification shown in figure 1?96 is valid only for the -2 (fastest) speed grade devices. for data rate specifications for other speed grades offered, refer to the dc and switching characteristics chapter. (2) the byte ordering block is available only if you select the word alignment pattern length of 20 bits. word aligner (pattern length ) basic double width 20-bit pma-pcs interface width disabled manual alignment (7-, 10-, 20-bit) disabled disabled 8b/10b encoder /decoder rate match fifo byte serdes byte ordering stratix iv gx configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit pma-pcs interface width pma-pcs interface width low-latency pcs enabled bit-slip (7-, 10-, 20-bit) disabled disabled disabled disabled disabled data rate (gbps (1) (1) ) 1.0 ? 8.5 channel bonding x1, x4, x8 fpga fabric - transceiver interface width 20-bit data rate (gbps) 1.0 ? 5.0 fpga fabric - transceiver interface frequency fpga fabric - transceiver interface frequency ( mhz ) 1.0 ? 5.0 enabled disabled enabled disabled disabled disabled enabled disabled enabled disabled enabled disabled enabled 1.0 ? 8.5 1.0 ? 5.0 1.0 ? 8.5 1.0 ? 5.0 1.0 ? 8.5 1.0 ? 5.0 1.0 ? 8.5 disabled disabled disabled disabled disabled disabled disabled 40-bit 16-bit 32-bit 20-bit 40-bit 16-bit 32-bit disabled enabled 1.0 ? 8.5 disabled disabled 20-bit 40-bit enabled disabled enabled 1.0 ? 5.0 1.0 ? 8.5 enabled (2) enabled (2) 40-bit 32-bit disabled disabled 16-bit 32-bit 50 - 250 50 - 250 50 - 250 50 - 250 50 - 250 50 - 250 25 - 212.5 25 - 212.5 25 - 212.5 25 - 212.5 25 - 212.5 25 - 212.5 25 - 212.5 25 - 212.5 deterministic latency 10-bit 20-bit interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 5 - 6 4 - 5.5 10 - 12 10 - 12 13 - 16 6.5 - 8. 5 6.5 - 8.5 4 - 5.5 5 - 6 4 - 5.5 4 - 5.5 5 - 6 4 - 5.5 6.5 - 8.5 6.5 - 8. 5 22 - 26 4 - 5.5 5 - 6 4 - 5.5 6.5 - 8. 5 5 - 6 10 - 12 10 - 12 6.5 - 8. 5 4 - 5 4 - 5.5 3 - 4 3 - 4.5 chapter 1: stratix iv transceiver architecture 1?117 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 f for more information about 40g/100g transceivers, refer to: enabling 40g/100g solutions with fpgas with 11.3-gbps transceivers web cast stratix iv fpga 40g/100g ip solutions website an 570: implementing the 40g/100g ethernet protocol in stratix iv devices figure 1?97. transceiver configurations in basic double-width mode with a 20-bit pma-pcs interface for stratix iv gt devices notes to figure 1?97 : (1) the maximum data rate specification shown in figure 1?97 is valid only for the -2 (fastest) speed grade devices. for data rate specifications for other speed grades offered, refer to the dc and switching characteristics chapter. (2) the circled configuration supports data rates up to 11.3 gbps per channel to implement 40g/100g links. word aligner (pattern length ) basic double width 20-bit pma-pcs interface width disabled manual alignment (7-, 10-, 20-bit) disabled disabled 8b/10b encoder /decoder rate match fifo byte serdes byte ordering stratix iv gt configurations basic single width double width functional modes protocol xaui srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 8-bit 16-bit 10-bit pma - pcs/fabric interface width pma-pcs interface width low-latency pcs enabled bit-slip (7-, 10-, 20-bit) disabled disabled disabled disabled disabled data rate (gbps) channel bonding x1, x4, x8 fpga fabric - transceiver interface width 20-bit data rate (gbps) fpga fabric - transceiver interface frequency fpga fabric - transceiver interface frequency ( mhz ) enabled disabled enabled disabled disabled disabled enabled disabled enabled disabled enabled disabled enabled disabled disabled disabled disabled disabled disabled disabled 40-bit 16-bit 32-bit 20-bit 40-bit 16-bit 32-bit disabled enabled disabled disabled 20-bit 40-bit enabled disabled enabled enabled enabled 40-bit 32-bit disabled disabled 16-bit 32-bit 124.4 - 250 124.4 - 250 124.4 - 250 124.4 - 250 124.4 - 250 124.4 - 250 62.2 - 282.5 62.2 - 212.5 62.2 - 212.5 62.2 - 212.5 62.2 - 212.5 62.2 - 212.5 62.2 - 212.5 62.2 - 212.5 2.488 - 5.0 2.488 - 5.0 2.488 - 8.5 2.488 - 8.5 2.488 - 5.0 2.488 - 8.5 2.488 - 5.0 2.488 - 8.5 2.488 - 5.0 2.488 - 8.5 2.488 - 5.0 2.488 - 11.3 2.488 - 11.3 (2) (1) (1) pipe 10-bit deterministic latency 10-bit 20-bit interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 5 - 6 4 - 5.5 10 - 12 10 - 12 13 - 16 6.5 - 8. 5 6.5 - 8.5 4 - 5.5 5 - 6 4 - 5.5 4 - 5.5 5 - 6 4 - 5.5 6.5 - 8.5 6.5 - 8. 5 22 - 26 4 - 5.5 5 - 6 4 - 5.5 6.5 - 8. 5 5 - 6 10 - 12 10 - 12 6.5 - 8. 5 4 - 5 4 - 5.5 3 - 4 3 - 4.5 1?118 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation sata and sas options serial advanced technology attachment (sata) and serial attached scsi (sas) are computer bus standards used in computers to transfer data between a mother board and mass storage devices. stratix iv gx and gt devices offer options to implement a transceiver that satisfies sata and sas protocols. these options are: transmitter in electrical idle mode receiver signal detect functionality these options and their selections are described in the following sections. transmitter buffer electrical idle in basic functional mode, you can enable the optional input signal tx_forceelecidle . when this input signal of a channel is asserted high, the transmitter buffer in that channel is placed in the electrical idle state. during electrical idle, the output of the transmitter buffer is tri-stated. this signal is used in applications like sata and sas for generating out of band (oob) signals. an oob signal is a pattern of idle times and burst times. different oob signals are distinguished by their different idle times. 1 for more information about the transmitter buffer in the electrical idle state, refer to the ?transmitter buffer electrical idle? section in ?pci express (pipe) mode? on page 1?124 . receiver input signal detect in basic functional mode, you can enable the optional rx_signaldetect signal (used for protocols such as sata and sas) only if you select the 8b/10b block. when you select the optional rx_signaldetect signal, an option is available to set the desired threshold level of the signal being received at the receiver?s input buffer. if the signal threshold detection circuitry senses the signal level present at the receiver input buffer to be higher than the chosen signal detect threshold, it asserts the rx_signaldetect signal high. otherwise, the signal threshold detection circuitry de-asserts the rx_signaldetect signal low. this signal is useful in applications such as sata and sas for detecting out of band (oob) signals. f for more information on the signal threshold detection circuitry, refer to the ?signal threshold detection circuitry? section in stratix iv transceiver architecture chapter. f for information about other protocols supported using basic functional mode, refer to an 577: recommended protocol configurations for stratix iv fpgas . chapter 1: stratix iv transceiver architecture 1?119 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 deterministic latency mode stratix iv gx and gt devices have a deterministic latency option available for use in high-speed serial interfaces such as cpri (common public radio interface) and open base station architecture initiative reference point3 (obsai rp3). both cpri and obsai rp3 protocols place stringent requirements on the amount of latency variation that is permissible through a link implementing these protocols. figure 1?98 shows the transceiver datapath when using deterministic latency mode. to implement this mode, select the deterministic latency option under the which protocol will you be using? section in the altgx megawizard plug-in manager. when you select this option, the transmitter channel is automatically placed in bit-slip mode and enable tx phase comp fifo in register mode is automatically selected as well. the receiver ?s phase compensation fifo is automatically placed in the register mode. in addition, an output port ( rx_bitslipboundaryselectout[4:0] ) from the receiver?s word aligner and an input port ( tx_bitslipboundaryselect[4:0] ) for the transmitter bit-slip circuitry are instantiated. the option for placing the transmitter phase compensation fifo in register mode is also available. transmitter bit slipping the transmitter is bit slipped to achieve deterministic latency. use the tx_bitslipboundaryselect[4:0] port to set the number of bits that the transmitter block needs to slip. table 1?44 lists the number of bits that are allowed to be slipped under different channel widths. figure 1?98. transceiver datapath when in deterministic latency mode byte deserializer byte serializer 8b10 decoder 8b/10b encoder rate match fifo receiver channel pcs receiver channel pma deskew fifo word aligner rx_datain deserializer cdr transmitter channel pcs transmitter channel pma tx_dataout serializer wrclk wrclk rdclk rdclk pci express hard ip fpga fabric pipe interface transmitter channel datapath receiver channel datapath tx phase compensation fifo byte ordering rx phase compensation fifo table 1?44. number of transmitter bits allowed to be slipped in deterministic latency mode channel width slip zero 8/10 bit 9 bits 16/20 bit 19 bits 1?120 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation receiver bit slipping the number of bits slipped in the receiver?s word aligner is given out on the rx_bitslipboundaryselectout[4:0] output port. the information on this output depends on your deserializer block width. in single-width mode with 8/10-bit channel width, the number of bits slipped in the receiver path is given out sequentially on this output. for example, if zero bits are slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 0(00000); if two bits are slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 2 (00010). in double-width mode with 16/20-bit channel width, the output is 19 minus the number of bits slipped. for example, if zero bits are slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 19 (10011); if two bits are slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 17 (10001). the information about the rx_bitslipboundaryselectout[4:0] output port helps in calculating the latency through the receiver datapath. you can use the information on rx_bitslipboundaryselectout[4:0] to set up the tx_bitslipboundaryselect[4:0] appropriately to cancel out the latency uncertainty. receiver phase comp fifo in register mode to remove the latency uncertainty through the receiver?s phase compensation fifo, select the enable the rx phase comp fifo in register mode option in the altgx megawizard plug-in manager. in register mode, the phase compensation fifo acts as a register and thereby removes the uncertainty in latency. the latency through the phase compensation fifo in register mode is one clock cycle. this mode is available in: basic single-width mode with 8-bit channel width and 8b/10b encoder enabled or 10-bit channel width with 8b/10b disabled. basic double-width mode with 16-bit channel width and 8b/10b encoder enabled or 20-bit channel width with 8b/10b disabled. transmitter phase compensation fifo in register mode in register mode, the phase compensation fifo acts as a register and thereby removes the uncertainty in latency. the latency through the transmitter and receiver phase compensation fifo in register mode is one clock cycle. cmu pll feedback to implement deterministic latency functional mode, the phase relationship between the low-speed parallel clock and cmu pll input reference clock must be deterministic. you can achieve this by selecting the enable pll phase frequency detector (pfd) feedback to compensate latency uncertainty in tx dataout and tx clkout paths relative to the reference clock option in the altgx megawizard plug-in manager. by selecting this option, a feedback path is enabled that ensures a deterministic relationship between the low-speed parallel clock and cmu pll input reference clock. chapter 1: stratix iv transceiver architecture 1?121 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 in order to achieve deterministic latency through the transceiver, the reference clock to the cmu pll must be the same as the low-speed parallel clock. for example, if you need a data rate of 1.2288 gbps to be implemented for the cpri protocol that places stringent requirements on the amount of latency variation, you must choose a reference clock of 122.88 mhz to allow for a feedback path from the cmu pll to be used. this feedback path reduces the variations in latency. when selecting this option, you must provide an input reference clock to the cmu pll that is of the same frequency as the low-speed parallel clock. 1 in a cpri implementation, the input reference clock to the cmu pll must be the same as the low-speed parallel clock. each cpri channel uses one cmu pll; therefore, each transceiver block can implement two cpri 1 channels only. atx plls do not have the feedback path enabled; therefore, they cannot be used for implementing the cpri configuration. in the deterministic latency 4 option, up to four cpri tx channels can be bundled in an 4 group so that they all have the same tx uncertainty and just require one tx pll to compensate for it. this is allowed in cases where the data rates are multiples of a single pll output frequency; for example, 0.6144 gbps, 1.228 gbps, 2.4576 gbps, and 4.9152 gbps. for 4 bundled channels to maintain pll lock during auto-negotiation, the ip must use over-sampling (sending the same bit multiple times) to output lower auto-negotiated line rates. do not use the hard 8b/10b for oversampled channels. cpri and obsai you can use deterministic latency functional mode to implement protocols such as cpri and obsai. the cpri interface defines a digital point-to-point interface between the radio equipment control (rec) and the radio equipment (re) allowing flexibility in either co-locating the rec and the re or remote location of the re. figure 1?99 shows various cpri topologies. in most cases, cpri links are between rec and re modules or between two re modules in a chain configuration. figure 1?99. cpri topologies rec radio equipment control re re re ring re re re chain re piont-to-point re re re tree and branch 1?122 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation if the destination for high-speed serial data leaving the rec is the first re, it is a single-hop connection. if serial data from the rec has to traverse through multiple res before reaching the destination re, it is a multi-hop connection. remotely locating the rf transceiver from the main base station introduces a complexity with overall system delay. cpri specification requires that the accuracy of measurement of round-trip delay on single-hop and multi-hop connections be within 16.276 ns in order to properly estimate the cable delay. for a single-hop system, this allows a variation in round-trip delay of up to 16.276 ns. for multi-hop systems however, the allowed delay variation is divided among number of hops in the connection? typically equal to 16.276 ns/ (# of hops), but not always equally divided among the hops. deterministic latency on a cpri link also enables highly accurate triangulation of a caller?s location. the obsai was established by several oem?s for developing a set of specifications that can be used for configuring and connecting common modules into base transceiver stations (bts). the bts has four main modules?radio frequency (rf), baseband, control and transport. figure 1?100 shows a typical bts. the radio frequency module (rfm) receives signals using portable devices and converts them to digital data. the baseband module processes the encoded signal and brings it back to baseband before transmitting it to the terrestrial network using the transport module. coordination between these three functions is maintained by a control module. figure 1?100. bts in osbal note to figure 1?100 : (1) ?rp? means reference point. transport mod ule baseband module rf module system softw are rp2 (1) rp3 (1) switch interface bb rfm control module rp1 (1) control & clock proprietary module(s) po w er system clock and sync chapter 1: stratix iv transceiver architecture 1?123 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 under the deterministic latency option, cpri data rates can be implemented in single-width mode with 8/10-bit channel width and double-width mode with 16/20-bit channel width options only. figure 1?101 shows the block diagram of the deterministic latency option. 1 to implement cpri/obsai using deterministic latency mode, altera recommends using configurations with the byte serializer/deserializer disabled. figure 1?101. block diagram of the deterministic latency option disabled rate match fifo byte serdes byte ordering stratix iv gx and gt configurations basic single width double width protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit disabled disabled fpga fabric - transceiver interface frequency disabled disabled functional modes pma-pcs interface width functional mode data rate (gbps) channel bonding low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder data rate (gbps) fpga fabric-transceiver interface width fpga fabric-transceiver interface frequency (mhz) manual alignment (10-bit) deterministic latency 0.6 - 3.75 gbps - gx 2.488 -3.75 gbps - gt x1, x4 0.6 - 2.5 gx 2.488 -2.5 gt 0.6 - 3.75 gx 2.488 - 3.75 gt 10-bit 20-bit deterministic latency -bit 20-bit 10 deterministic latency 0.6 - 8.5 gbps - gx 2.488 - 8.5 gbps - gt x1, x4 disabled manual alignment (10-bit, 20-bit) disabled enabled enabled disabled disabled disabled disabled enabled disabled enabled disabled enabled disabled enabled 1.0 - 5.0 gx 2.488 - 5.0 gt 1.0 - 8.5 gx 2.488 - 8.5 gt disabled disabled disabled disabled disabled disabled 8-bit 16-bit 20-bit 40-bit 16-bit 32-bit 50 - 250 - gx 124.4 - 250 - gt 0.6 - 2.5 gx 2.488 -2.5 gt 0.6 - 3.75 gx 2.488 - 3.75 gt 1.0 - 5.0 gx 2.488 - 5.0 gt 1.0 - 8.5 gx 2.488 - 8.5 gt 25 - 212.5 - gx 62.2 - 212.5 - gt 60 - 250 - gx 248.8 - 250 - gt 30 - 187.5 - gx 124.4 - 187.5 - gt 25 - 212.5 - gx 62.2 - 212.5 - gt 30 - 187.5 - gx 124.4 - 187.5 - gt 60 - 250 - gx 248.8 - 250 - gt 50 - 250 - gx 124.4 - 250 - gt interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 4 4 4 4 8 8 7 7 1?124 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation table 1?45 lists the pma-pcs interface widths, cpri and osbai data rates in deterministic latency mode. pci express (pipe) mode intel corporation has developed a phy interface for the pci express (pipe) architecture specification to enable implementation of a pci express (pipe)-compliant physical layer device. the pci express (pipe) specification also defines a standard interface between the physical layer device and the media access control layer (mac). version 2.0 of the pci express (pipe) specification provides implementation details for a pci express (pipe)-compliant physical layer device at both gen1 (2.5 gt/s) and gen2 (5 gt/s) signaling rates. to implement a version 2.0 pci express (pipe)-compliant phy, you must configure the stratix iv gx and gt transceivers in pci express (pipe) functional mode. stratix iv gx and gt devices have built-in pci express (pipe) hard ip blocks that you can use to implement the phy-mac layer, data link layer, and transaction layer of the pci express (pipe) protocol stack. you can also bypass the pci express (pipe) hard ip blocks and implement the phy-mac layer, data link layer, and transaction layer in the fgpa fabric using a soft ip. if you enable the pci express (pipe) hard ip blocks, the stratix iv transceivers interface with these hard ip blocks. otherwise, the stratix iv transceivers interface with the fpga fabric. you can configure the stratix iv gx and gt transceivers in pci express (pipe) functional mode using one of the following two methods: altgx megawizard plug-in manager?if you do not use the pci express (pipe) hard ip block pci express (pipe) compiler?if you use the pci express (pipe) hard ip block 1 description of pci express (pipe) hard ip architecture and pci express (pipe) mode configurations allowed when using the pci express (pipe) hard ip block are beyond the scope of this chapter. for more information about the pci express (pipe) hard ip block, refer to the pci express compiler user guide. table 1?45. pma-pcs interface widths, cpri and osbai data rates in deterministic latency mode deterministic latency mode supported data rate range pma-pcs interface width for cpri & obsai cpri data rate (gbps) pcs clock frequency (mhz) obsai data rate (gbps) pcs clock frequency (mhz) single-width mode 600 mbps to 3.75 gbps 8 bit/10 bit 0.6144 61.44 768 76.8 1.2288 122.88 1.536 153.6 2.4576 (1) 245.76 ? ? double-width mode > 1 gbps 16 bit/20 bit 3072 153.6 1.536 76.8 16 bit/20 bit 4915.2 (2) , (3) 245.76 3072 (3) 153.6 32 bit/40 bit 6144 (2) , (3) , (4) 307.2 6144 (3) , (4) 307.2 notes to ta bl e 1? 45 : (1) when configured in double-width mode for the same data rate, the core clock frequency is halved. (2) requires double-width mode. (3) when configured for 32/40-bit channel width requiring byte serializer/deserializer, the core clock is halved. (4) requires the byte serializer/deserializer. chapter 1: stratix iv transceiver architecture 1?125 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 pci express (pipe) mode configurations stratix iv gx and gt transceivers support both gen1 (2.5 gbps) and gen2 (5 gbps) data rates in pci express (pipe) functional mode. when configured for the gen2 (5 gbps) data rate, the stratix iv gx and gt transceivers allow dynamic switching between gen2 (5 gbps) and gen1 (2.5 gbps) signaling rates. dynamic switch capability between the two pci express (pipe) signaling rates is critical for speed negotiation during link training. stratix iv gx and gt transceivers support 1, 4, and 8 lane configurations in pci express (pipe) functional mode at both 2.5 gbps and 5 gbps data rates. in pci express (pipe) 1 configuration, the pcs and pma blocks of each channel are clocked and reset independently. pci express (pipe) 4 and 8 configurations support channel bonding for four-lane and eight-lane pci express (pipe) links. in these bonded channel configurations, the pcs and pma blocks of all bonded channels share common clock and reset signals. 1?126 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?102 shows the stratix iv gx and gt transceiver configurations allowed in pci express (pipe) functional mode. figure 1?102. stratix iv gx and gt transceivers in pci express (pipe) functional mode channel bonding rate match fifo functional mode data rate disabled byte serdes disabled disabled enabled enabled enabled disabled disabled enabled pipe 2.5 gbps (gen1) x1, x4, x8 10-bit automatic synchronization state machine (/k28.5+/,/k28.5-/) enabled enabled enabled 8-bit 8-bit 16-bit 250 mhz 250 mhz 125 mhz pma-pcs interface width word aligner (pattern) 8b/10b encoder/ decoder pci express hardip pcs-hardip or pcs-fpga fabric interface width pcs-hardip or pcs-fpga fabric interface frequency 500 mhz 250 mhz 8-bit 16-bit enabled automatic synchronization state machine (/k28.5+/,/k28.5-/) 10-bit x1, x4, x8 5 gbps (gen2) stratix iv gx and gt configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 10-bit 20-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit pma-pcs interface width deterministic latency 10-bit 20-bit interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 5 - 6 5 - 6 4 - 5.5 5 - 6 4 - 5.5 20 - 24 20 - 24 11.5 - 14.5 20 - 24 11.5 - 14.5 chapter 1: stratix iv transceiver architecture 1?127 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 pci express (pipe) mode datapath figure 1?103 shows the stratix iv gx and gt transceiver datapath when configured in pci express (pipe) functional mode. for more information, refer to ?rate match (clock rate compensation) fifo? on page 1?74 . table 1?46 lists the transceiver datapath clock frequencies in pci express (pipe) functional mode configured using the altgx megawizard plug-in manager. figure 1?103. stratix iv gx and gt transceiver datapath in pci express (pipe) 1 mode tx_coreclk[0] fpga fabric transceiver interface clock rx phase compensation fifo byte ordering byte deserializer byte serializer 8b/10b8b/10b8b/10b 8b/10b decoder 8b/10b encoder rate match fifo receiver channel pcs receiver channel pma deskew fifo word aligner deserializer cdr transmitter channel pcs transmitter channel pma serializer wrclk wrclk rdclk rdclk high-speed serial clock tx_clkout[0] low-speed parallel clock pci express hard ip fpga fabric /2 pipe interface /2 low -speed parallel clock parallel recovery clock rx_coreclk[0] transmitter channel datapath receiver channel datapath fpga fabric tx phase compensation fifo table 1?46. stratix iv gx and gt transceiver datapath clock frequencies in pci express (pipe) mode functional mode data rate high-speed serial clock frequency parallel recovered clock and low-speed parallel clock frequency fpga fabric-transceiver interface clock frequency without byte serializer/ deserializer (8 bit wide) with byte serializer/ deserializer (16 bit wide) pci express (pipe) 1, 4, and 8 (gen1) 2.5 gbps 1.25 ghz 250 mhz 250 mhz 125 mhz pci express (pipe) 1, 4, and 8 (gen2) 5 gbps 2.5 ghz 500 mhz n/a (1) 250 mhz note to tab l e 1 ?4 6 : (1) in pci express (pipe) functional mode at gen2 (5 gbps) data rate, the byte serializer/deserializer cannot be bypassed. 1?128 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation transceiver datapath clocking varies between non-bonded (1) and bonded (4 and 8) configurations in pci express (pipe) mode. f for more information about transceiver datapath clocking in different pci express (pipe) configurations, refer to the stratix iv transceiver clocking chapter. table 1?47 lists the transmitter and receiver datapaths in pci express (pipe) mode. table 1?48 lists the features supported in pci express (pipe) functional mode for 2.5 gbps and 5 gbps data rate configurations. for more information, refer to ?rate match fifo in pci express (pipe) mode? on page 1?75 . table 1?47. datapaths in pci express (pipe) mode transmitter datapath receiver datapath pci express (pipe) interface vv transmitter phase compensation fifo v ? optional byte serializer (enabled for 16-bit and disabled for 8-bit fpga fabric-transceiver interface v ? 8b/10b encoder v ? 10:1 serializer v ? transmitter buffer with receiver detect circuitry v ? receiver buffer with signal detect circuitry ? v 1:10 deserializer ? v word aligner that implements pci express (pipe)-compliant synchronization state machine ? v optional rate match fifo (clock rate compensation) that can tolerate up to 600 ppm frequency difference ? v 8b/10b decoder ? v optional byte deserializer (enabled for 16-bit and disabled for 8-bit fpga fabric-transceiver interface) ? v receiver phase compensation fifo ? v table 1?48. supported features in pci express (pipe) mode (part 1 of 2) feature 2.5 gbps (gen1) 5gbps (gen2) 1, 4, 8 link configurations vv pci express (pipe)-compliant synchronization state machine vv 300 ppm (total 600 ppm) clock rate compensation vv 8-bit fpga fabric-transceiver interface v ? 16-bit fpga fabric-transceiver interface vv transmitter buffer electrical idle vv receiver detection vv 8b/10b encoder disparity control when transmitting compliance pattern vv chapter 1: stratix iv transceiver architecture 1?129 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 pci express (pipe) interface in pci express (pipe) mode, each channel has a pci express (pipe) interface block that transfers data, control, and status signals between the phy-mac layer and the transceiver channel pcs and pma blocks. the pci express (pipe) interface block is compliant to version 2.0 of the pci express (pipe) specification. if you use the pci express (pipe) hard ip block, the phy-mac layer is implemented in the hard ip block. otherwise, the phy-mac layer can be implemented using soft ip in the fpga fabric. 1 the pci express (pipe) interface block is only used in pci express (pipe) mode and cannot be bypassed. besides transferring data, control, and status signals between the phy-mac layer and the transceiver, the pci express (pipe) interface block implements the following functions required in a pci express (pipe)-compliant physical layer device: forces the transmitter buffer in electrical idle state initiates the receiver detect sequence 8b/10b encoder disparity control when transmitting compliance pattern manages the pci express (pipe) power states indicates the completion of various phy functions; for example, receiver detection and power state transitions on the pipephydonestatus signal encodes the receiver status and error conditions on the pipestatus[2:0] signal as specified in the pci express (pipe) specification transmitter buffer electrical idle when the input signal tx_forceelecidle is asserted high, the pci express (pipe) interface block puts the transmitter buffer in that channel in the electrical idle state. during electrical idle, the transmitter buffer differential and common mode output voltage levels are compliant to the pci express (pipe) base specification 2.0 for both pci express (pipe) gen1 and gen2 data rates. power state management vv receiver status encoding vv dynamic switch between 2.5 gbps and 5 gbps signaling rate ? v dynamically selectable transmitter margining for differential output voltage control ? v dynamically selectable transmitter buffer de-emphasis of -3.5 db and -6 db ? v table 1?48. supported features in pci express (pipe) mode (part 2 of 2) feature 2.5 gbps (gen1) 5gbps (gen2) 1?130 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?104 shows the relationship between the assertion of the tx_forceelecidle signal and the transmitter buffer output on the tx_dataout port. time t1 taken from the assertion of the tx_forceelecidle signal to the transmitter buffer reaching electrical idle voltage levels is pending characterization. once in the electrical idle state, the pci express (pipe) protocol requires the transmitter buffer to stay in electrical idle for a minimum of 20 ns for both gen1 and gen2 data rates. 1 the minimum period of time for which the tx_forceelecidle signal must be asserted high such that the transmitter buffer stays in electrical idle state for at least 20 ns is pending characterization. the pci express (pipe) specification requires the transmitter buffer to be in electrical idle in certain power states. for more information about the tx_forceelecidle signal levels required in different pci express (pipe) power states, refer to table 1?50 on page 1?134 . receiver detection during the detect substate of the link training and status state machine (ltssm), the pci express (pipe) protocol requires the transmitter channel to perform a receiver detect sequence to detect if a receiver is present at the far end of each lane. the pci express (pipe) specification requires the receiver detect operation to be performed during the p1 power state. the pci express (pipe) interface block in stratix iv gx and gt transceivers provide an input signal tx_detectrxloopback for the receiver detect operation. when the input signal tx_detectrxloopback is asserted high in the p1 power state, the pci express (pipe) interface block sends a command signal to the transmitter buffer in that channel to initiate a receiver detect sequence. in the p1 power state, the transmitter buffer must always be in the electrical idle state. after receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. if an active receiver (that complies with the pci express [pipe] input impedance requirements) is present at the far end, the time constant of the step voltage on the trace is higher when compared with the time constant of the step voltage when the receiver is not present. the receiver detect circuitry monitors the time constant of the step signal seen on the trace to determine if a receiver was detected. the receiver detect circuitry monitor requires a 125-mhz clock for operation that you must drive on the fixedclk port. figure 1?104. transmitter buffer electrical idle state tx_forcelecidle tx_dataout t1 >20 ns chapter 1: stratix iv transceiver architecture 1?131 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 1 for the receiver detect circuitry to function reliably, the ac-coupling capacitor on the serial link and the receiver termination values used in your system must be compliant to the pci express (pipe) base specification 2.0. receiver detect circuitry communicates the status of the receiver detect operation to the pci express (pipe) interface block. if a far-end receiver is successfully detected, the pci express (pipe) interface block asserts pipephydonestatus for one clock cycle and synchronously drives the pipestatus[2:0] signal to 3'b011. if a far-end receiver is not detected, the pci express (pipe) interface block asserts pipephydonestatus for one clock cycle and synchronously drives the pipestatus[2:0] signal to 3'b000. figure 1?105 and figure 1?106 show the receiver detect operation where a receiver was successfully detected and where a receiver was not detected, respectively. figure 1?105. receiver detect, successfully detected figure 1?106. receiver detect, unsuccessfully detected powerdown[1:0] tx_detectrxloopback pipephydonestatus pipestatus[2:0] 3'b000 2'b10(p1) 3'b011 powerdown[1:0] tx_detectrxloopback pipephydonestatus pipestatus[2:0] 3'b000 2'b10 (p1) 1?132 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation compliance pattern transmission support the ltssm state machine can enter the polling.compliance substate where the transmitter is required to transmit a compliance pattern as specified in the pci express (pipe) base specification 2.0. the po lling.compliance substate is intended to assess if the transmitter is electrically compliant with the pci express (pipe) voltage and timing specifications. the compliance pattern is a repeating sequence of the following four code groups: /k28.5/ /d21.5/ /k28.5/ /d10.2/ the pci express (pipe) protocol requires the first /k28.5/ code group of the compliance pattern to be encoded with negative current disparity. to satisfy this requirement, the pci express (pipe) interface block provides the input signal tx_forcedispcompliance. a high level on tx_forcedispcompliance forces the associated parallel transmitter data on the tx_datain port to transmit with negative current running disparity. for 8-bit transceiver channel width configurations, you must drive tx_forcedispcompliance high in the same parallel clock cycle as the first /k28.5/ of the compliance pattern on the tx_datain port. for 16-bit transceiver channel width configurations, you must drive only the lsb of tx_forcedispcompliance[1:0] high in the same parallel clock cycle as /k28.5/d21.5/ of the compliance pattern on the tx_datain port. figure 1?107 and figure 1?108 show the required level on the tx_forcedispcompliance signal while transmitting the compliance pattern in 8-bit and 16-bit channel width configurations, respectively. figure 1?107. compliance pattern transmission support, 8-bit channel width configurations bc bc bc bc tx_datain[7:0] tx_ctrldetect tx_forcedispcompliance b5 4a b5 4a k28.5 d21.5 k28.5 d10.2 k28.5 d21.5 k28.5 d10.2 chapter 1: stratix iv transceiver architecture 1?133 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 power state management the pci express (pipe) specification defines four power states?p0, p0s, p1, and p2? that the physical layer device must support to minimize power consumption. p0 is the normal operating state during which packet data is transferred on the pci express (pipe) link. p0s, p1, and p2 are low-power states into which the physical layer must transition as directed by the phy-mac layer to minimize power consumption. the pci express (pipe) specification provides the mapping of these power states to the ltssm states specified in the pci express (pipe) base specification 2.0. the phy-mac layer is responsible for implementing the mapping logic between the ltssm states and the four power states in the pci express (pipe)-compliant phy. the pci express (pipe) interface in stratix iv gx and gt transceivers provides an input port, powerdn[1:0] , for each transceiver channel configured in pci express (pipe) mode. table 1?49 lists mapping between the logic levels driven on the powerdn[1:0] port and the resulting power state that the pci express (pipe) interface block puts the transceiver channel into. 1 when transitioning from the p0 power state to lower power states (p0s, p1, and p2), the pci express (pipe) specification requires the physical layer device to implement power saving measures. stratix iv gx and gt transceivers do not implement these power saving measures except putting the transmitter buffer in electrical idle in the lower power states. figure 1?108. compliance pattern transmission support, 16-bit wide channel configurations 01 00 01 tx_datain[15:0] tx_ctrldetect[1:0] tx_forcedispcompliance[1:0] b5bc /k28.5/d21.5/ /k28.5/d10.2/ bc4a b5bc /k28.5/d21.5/ bc4a /k28.5/d10.2/ table 1?49. power state functions and descriptions power state powerdn function description p0 2?b00 transmits normal data, transmits electrical idle, or enters into loopback mode normal operation mode p0s 2?b01 only transmits electrical idle low recovery time saving state p1 2?b10 transmitter buffer is powered down and can do a receiver detect while in this state high recovery time power saving state p2 2?b11 transmits electrical idle or a beacon to wake up the downstream receiver lowest power saving state 1?134 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the pci express (pipe) interface block indicates successful power state transition by asserting the pipephydonestatus signal for one parallel clock cycle as specified in the pci express (pipe) specification. the phy-mac layer must not request any further power state transition until the pipephydonestatus signal has indicated the completion of the current power state transition request. figure 1?109 shows an example waveform for a transition from the p0 to p2 power state. the pci express (pipe) specification allows the pci express (pipe) interface to perform protocol functions; for example, receiver detect, loopback, and beacon transmission, in specified power states only. this requires the phy-mac layer to drive the tx_detectrxloopback and tx_forceelecidle signals appropriately in each power state to perform these functions. table 1?50 lists the logic levels that the phy-mac layer must drive on the tx_detectrxloopback and tx_forceelecidle signals in each power state. receiver status the pci express (pipe) specification requires the phy to encode the receiver status on a 3-bit rxstatus[2:0] signal. this status signal is used by the phy-mac layer for its operation. the pci express (pipe) interface block receives status signals from the transceiver channel pcs and pma blocks and encodes the status on the 3-bit output signal pipestatus[2:0] to the fpga fabric. the encoding of the status signals on pipestatus[2:0] is compliant with the pci express (pipe) specification and is listed in table 1?51 . figure 1?109. power state transition from the p0 to p2 power state parallel clock powerdn[1:0] pipephydonestatus 2'b00 (p0) 2'b11 (p2) table 1?50. logic levels for tx_detectrxloopback and tx_forceelecidle in different power states power state tx_detectrxloopback tx_forceelecidle p0 0: normal mode 1: datapath in loopback mode 0: must be de-asserted 1: illegal mode p0s don?t care 0: illegal mode 1: must be asserted in this state p1 0: electrical idle 1: receiver detect 0: illegal mode 1: must be asserted in this state p2 don?t care de-asserted in this state for sending beacon. otherwise asserted. chapter 1: stratix iv transceiver architecture 1?135 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 two or more of the error conditions (for example, 8b/10b decode error [code group violation], rate match fifo overflow or underflow, and receiver disparity error), can occur simultaneously. the pci express (pipe) interface follows the priority listed in table 1?51 while encoding the receiver status on the pipestatus[2:0] port. for example, if the pci express (pipe) interface receives an 8b/10b decode error and disparity error for the same symbol, it drives 3'b100 on the pipestatus[2:0] signal. fast recovery mode the pci express (pipe) base specification fast training sequences (fts) are used for bit and byte synchronization to transition from l0s to l0 (pci express [pipe] p0s to p0) power states. when transitioning from the l0s to l0 power state, the pci express (pipe) base specification requires the physical layer device to acquire bit and byte synchronization after receiving a maximum of 255 fts (~4 us at gen1 data rate and ~2 us at gen2 data rate). if you have configured the stratix iv gx and gt receiver cdr in automatic lock mode, the receiver cannot meet the pci express (pipe) specification of acquiring bit and byte synchronization within 4 s (gen1 data rate) or 2 s (gen2 data rate) due to the signal detect and ppm detector time. to meet this specification, each stratix iv gx and gt transceiver has a built-in fast recovery circuitry that you can optionally enable. 1 to enable the fast recovery circuitry, select the enable fast recovery mode option in the altgx megawizard plug-in manager. if you enable the fast recovery mode option, the fast recovery circuitry controls the receiver cdr rx_locktorefclk and rx_locktodata signals to force the receiver cdr in ltr or ltd mode. it relies on the electrical idle ordered sets (eios), n_fts sequences received in the l0 power state, and the signal detect signal from the receiver input buffer to control the receiver cdr lock mode. 1 the fast recovery circuitry is self-operational and does not require control inputs from you. when enabled, the rx_locktorefclk and rx_locktodata ports are not available in the altgx megawizard plug-in manager. table 1?51. encoding of the status signals on pipestatus[2:0] pipestatus[2:0] description error condition priority 3'b000 received data ok n/a 3'b001 one skp symbol added 5 3'b010 one skp symbol deleted 6 3'b011 receiver detected n/a 3'b100 8b/10b decode error 1 3'b101 elastic buffer (rate match fifo) overflow 2 3'b110 elastic buffer (rate match fifo) underflow 3 3'b111 received disparity error 4 1?136 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation electrical idle inference the pci express (pipe) protocol allows inferring the electrical idle condition at the receiver instead of detecting the electrical idle condition using analog circuitry. clause 4.2.4.3 in the pci express (pipe) base specification 2.0 specifies conditions to infer electrical idle at the receiver in various substates of the ltssm state machine. in all pci express (pipe) modes (1, 4, and 8), each receiver channel pcs has an optional electrical idle inference module designed to implement the electrical idle inference conditions specified in the pci express (pipe) base specification 2.0. you can enable the electrical idle inference module by selecting the enable electrical idle inference functionality option in the altgx megawizard plug-in manager. if enabled, this module infers electrical idle depending on the logic level driven on the rx_elecidleinfersel[2:0] input signal. the electrical idle inference module in each receiver channel indicates whether the electrical idle condition is inferred or not on the pipeelecidle signal of that channel. the electrical idle interface module drives the pipeelecidle signal high if it infers an electrical idle condition; otherwise, it drives it low. table 1?52 shows electrical idle inference conditions specified in the pci express (pipe) base specification 2.0 and implemented in the electrical idle inference module to infer electrical idle in various substates of the ltssm state machine. for the electrical idle inference module to correctly infer an electrical idle condition in each ltssm substate, you must drive the rx_elecidleinfersel[2:0] signal appropriately, as shown in table 1?52 . in the recovery.speed substate of the ltssm state machine with unsuccessful speed negotiation ( rx_elecidleinfersel[2:0] = 3'b110 ), the pci express (pipe) base specification requires the receiver to infer an electrical idle condition ( pipeelecidle = high) if absence of an exit from electrical idle is detected in a 2000 ui interval for gen1 data rate and 16000 ui interval for gen2 data rate. the electrical idle inference module detects an absence of exit from electrical idle if four /k28.5/ com code groups are not received in the specified interval. table 1?52. electrical idle inference conditions ltssm state gen1 (2.5 gbps) gen2 (5 gbps) rx_elecidleinfersel[2:0] l0 absence of skip ordered set in 128 s window absence of skip ordered set in 128 s window 3'b100 recovery.rcvrcfg absence of ts1 or ts2 ordered set in 1280 ui interval absence of ts1 or ts2 ordered set in 1280 ui interval 3'b101 recovery.speed when successful speed negotiation = 1'b1 absence of ts1 or ts2 ordered set in 1280 ui interval absence of ts1 or ts2 ordered set in 1280 ui window 3'b101 recovery.speed when successful speed negotiation = 1'b0 absence of an exit from electrical idle in 2000 ui interval absence of an exit from electrical idle in 16000 ui interval 3'b110 loopback.active (as slave) absence of an exit from electrical idle in 128 s window n/a 3'b111 chapter 1: stratix iv transceiver architecture 1?137 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 in other words, when configured for gen1 data rate and rx_elecidleinfersel[2:0] = 3'b110, the electrical idle inference module asserts pipeelecidle high if it does not receive four /k28.5/ com code groups in a 2000 ui interval. when configured for gen1 data rate and rx_elecidleinfersel[2:0] = 3'b111 in the loopback.active substate of the ltssm state machine, the electrical idle inference module asserts pipeelecidle high if it does not receive four /k28.5/ com code groups in a 128 s interval. when configured for gen2 data rate and rx_elecidleinfersel[2:0] = 3'b110, the electrical idle inference module asserts pipeelecidle high if it does not receive four /k28.5/ com code groups in a 16000 ui interval. 1 the electrical idle inference module does not have the capability to detect the electrical idle exit condition based on reception of the electrical idle exit ordered set (eieos), as specified in the pci express (pipe) base specification. if you select the enable electrical idle inference functionality option in the altgx megawizard plug-in manager and drive rx_elecidleinfersel[2:0] = 3'b0xx , the electrical idle inference block uses the eios detection from the fast recovery circuitry to drive the pipeelecidle signal. if you do not select the enable electrical idle inference functionality option in the altgx megawizard plug-in manager, the electrical idle inference module is disabled. in this case, the rx_signaldetect signal from the signal detect circuitry in the receiver buffer is inverted and driven as the pipeelecidle signal. recommendation when using the electrical idle inference block in a pci express (pipe) link, when operating at gen2 data rate, the downstream device can go into the disable state after instruction from the upper layer. once in the disable state, the downstream device must detect an electrical idle exit condition to go into the detect state. at this same time, the upstream device can be directed by the upper layer to go into the detect state and start transmitting the com symbols to the downstream device at gen 1 data rate. 1 the disable and detect states are different states of the link training and status state machine as described by the pci express (pipe) base specification rev 2.0. 1 the com symbol is an 8b/10b encoded value of k28.5 and is part of the training sequences ts1 and ts2 as described by the pci express (pipe) base specification rev 2.0. when the stratix iv gx and gt device is operating as a downstream device at pci express (pipe) gen 2 data rates and if it goes into the disable state, the stratix iv gx and gt receiver must receive an electrical idle exit condition in order to move out of the disable state. for the stratix iv gx and gt receiver, the electrical idle exit condition is achieved when com symbols are received from the upstream device. however, after the disable state is achieved by the stratix iv gx and gt receiver (the downstream device) during gen 2 data rate operation, and if at the same time the upstream device is directed to transition to the detect state, the upstream device starts to send com symbols at gen 1 data rate. consequently, the stratix iv gx and gt receiver (the downstream device) does not recognize the com symbols as it is operating at gen 2 1?138 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation data rate. to avoid this scenario, the link training status state machine (ltssm) in the fpga fabric of stratix iv gx and gt receiver (the downstream device) must be implemented in such a way that whenever the downstream device goes into the disable state and the upstream device is directed to go into the detect state, the rateswitch signal must be transitioned from high to low. this allows the stratix iv gx and gt receiver (the downstream device) to move from gen 2 to gen 1 data rate. subsequently, the stratix iv gx and gt receiver (the downstream device) recognizes the com symbols being sent by the upstream device at gen 1 data rates and moves from the disable state to the detect state. pci express (pipe) gen2 (5 gbps) support the pci express (pipe) functional mode supports the following additional features when configured for 5 gbps data rate: dynamic switch between 2.5 gbps and 5 gbps signaling rate dynamically selectable transmitter margining for differential output voltage control dynamically selectable transmitter buffer de-emphasis of -3.5 db and -6 db dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rate during link training, the upstream and downstream pci express (pipe) ports negotiate the speed (2.5 gbps or 5 gbps) at which the link operates. because the upstream and downstream pci express (pipe) ports do not know the speed capabilities of their link partner, the pci express (pipe) protocol requires each port to start with a gen1 (2.5 gbps) signaling rate. one of the ports capable of supporting the gen2 (5 gbps) signaling rate might initiate a speed change request by entering the recovery state of the ltssm. in the recovery state, each port advertises its speed capabilities by transmitting training sequences as specified in the pci express (pipe) base specification 2.0. if both ports are capable of operating at the gen2 (5 gbps) signaling rate, the phy-mac layer instructs the physical layer device to operate at the gen2 (5 gbps) signaling rate. to support speed negotiation during link training, the pci express (pipe) specification requires a pci express (pipe)-compliant physical layer device to provide an input signal ( rate) to the phy-mac layer. when this input signal is driven low, the physical layer device must operate at the gen1 (2.5 gbps) signaling rate; when driven high, this input signal must operate at the gen2 (5 gbps) signaling rate. the pci express (pipe) specification allows the phy-mac layer to initiate a signaling rateswitch only in power states p0 and p1 with the transmitter buffer in the electrical idle state. the pci express (pipe) specification allows the physical layer device to implement the signaling rateswitch using either of the following approaches: change the transceiver datapath clock frequency, keeping the transceiver interface width constant change the transceiver interface width between 8 bit and 16 bit, keeping the transceiver clock frequency constant when configured in pci express (pipe) functional mode at gen2 (5 gbps) data rate, the altgx megawizard plug-in manager provides the input signal rateswitch . the rateswitch signal is functionally equivalent to the rate signal specified in the pci express (pipe) specification. the phy-mac layer can use the rateswitch signal to instruct the stratix iv gx and gt device to operate at either gen1 (2.5 gbps) chapter 1: stratix iv transceiver architecture 1?139 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 or gen2 (5 gbps) data rate, depending on the negotiated speed between the upstream and downstream ports. a low-to-high transition on the rateswitch signal initiates a data rateswitch from gen1 (2.5 gbps) to gen2 (5 gbps). a high-to-low transition on the rateswitch signal initiates a data rateswitch from gen2 (5 gbps) to gen1 (2.5 gbps). the signaling rateswitch between gen1 (2.5 gbps) and gen2 (5 gbps) is achieved by changing the transceiver datapath clock frequency between 250 mhz and 500 mhz, while maintaining a constant transceiver interface width of 16-bit. the dedicated pci express (pipe) rateswitch circuitry performs the dynamic switch between the gen1 (2.5 gbps) and gen2 (5 gbps) signaling rate. the pci express (pipe) rateswitch circuitry consists of: pci express (pipe) rateswitch controller pci express (pipe) clock switch circuitry pci express (pipe) rateswitch controller the rateswitch signal serves as the input signal to the pci express (pipe) rateswitch controller. after seeing a transition on the rateswitch signal from the phy-mac layer, the pci express (pipe) rateswitch controller performs the following operations: controls the pci express (pipe) clock switch circuitry to switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rate depending on the rateswitch signal level disables and resets the transmitter and receiver phase compensation fifo pointers until the pci express (pipe) clock switchover circuitry indicates successful rateswitch completion communicates completion of rateswitch to the pci express (pipe) interface module, which in turn communicates completion of the rateswitch to the phy-mac layer on the pipephydonestatus signal pci express (pipe) rateswitch controller location: in pci express (pipe) 1 mode, the pci express (pipe) rateswitch controller is located in the transceiver pcs of each channel. in pci express (pipe) 4 mode, the pci express (pipe) rateswitch controller is located in cmu0_channel within the transceiver block. in pci express (pipe) 8 mode, the pci express (pipe) rateswitch controller is located in cmu0_channel within the master transceiver block. 1 when operating at the gen 2 data rate, asserting the rx_digitalreset signal causes the pci express (pipe) rateswitch circuitry to switch the transceiver to gen 1 data rate. 1 when switching from gen1 to gen2 using the dynamic reconfiguration controller, you must set the two ports of the dynamic reconfiguration controller, tx_preemp_0t and tx_preemp_2t , to zero to meet the gen2 de-emphasis specifications. when switching from gen2 to gen1, if your system requires specific settings on tx_preemp_01 and tx_preemp_2t , those values must be set at the respective two ports of the dynamic reconfiguration controller to meet your system requirements. 1?140 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation pci express (pipe) clock switch circuitry when the phy-mac layer instructs a rateswitch between the gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates, both the transmitter high-speed serial and low-speed parallel clock and the cdr recovered clock must switch to support the instructed data rate. stratix iv gx and gt transceivers have dedicated pci express (pipe) clock switch circuitry located in the following blocks: local clock divider in transmitter pma of each transceiver channel cmu0 clock divider in cmu0_channel of each transceiver block receiver cdr in receiver pma of each transceiver channel pci express (pipe) transmitter high-speed serial and low-speed parallel clock switch occurs: in pci express (pipe) 1 mode, the cmu_pll clock switch occurs in the local clock divider in each transceiver channel. in pci express (pipe) 4 mode, the cmu_pll clock switch occurs in the cmu0 clock divider in the cmu0_channel within the transceiver block. in pci express (pipe) 8 mode, the cmu_pll clock switch occurs in the cmu0 clock divider in the cmu0_channel within the master transceiver block. in pci express (pipe) 1, 4, and 8 modes, the recovered clock switch happens in the receiver cdr of each transceiver channel. table 1?53 lists the locations of the pci express (pipe) rateswitch controller and the pci express (pipe) clock switch circuitry in pci express (pipe) 1, 4, and 8 modes. table 1?53. pci express (pipe) rateswitch controller and clock switch circuitry channel bonding option location of pci express (pipe) rateswitch controller module location of pci express (pipe) clock switch circuitry transmitter high-speed serial and low-speed parallel clock switch circuitry recovered clock switch circuitry 1 individual channel pcs block local clock divider in transmitter pma of each channel cdr block in receiver pma of each channel 4 cmu0 _ channel cmu0 clock divider in cmu0_channel cdr block in receiver pma of each channel 8 cmu0_channel of the master transceiver block cmu0 clock divider in cmu0_channel of the master transceiver block cdr block in receiver pma of each channel chapter 1: stratix iv transceiver architecture 1?141 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates in pci express (pipe) x1 mode figure 1?110 shows the pci express (pipe) rateswitch circuitry in pci express (pipe) 1 mode configured at gen2 (5 gbps) data rate. in pci express (pipe) 1 mode configured at gen2 (5 gbps) data rate, when the pci express (pipe) rateswitch controller sees a transition on the rateswitch signal, it sends control signal pcie_gen2switch to the pci express (pipe) clock switch circuitry in the local clock divider block and the receiver cdr to switch to the instructed signaling rate. a low-to-high transition on the rateswitch signal initiates a gen1 (2.5 gbps) to gen2 (5 gbps) signaling rateswitch. a high-to-low transition on the rateswitch signal initiates a gen2 (5 gbps) to gen1 (2.5 gbps) signaling rateswitch. table 1?54 lists the transceiver clock frequencies when switching between 2.5 gbps and 5 gbps signaling rates. figure 1?110. dynamic switch signaling in pipe 1 mode rx_datain rx_cruclk rx_locktorefclk rx_lockt odata signal detect rx_freqlocked serial recovered clock parallel recovered clock high-speed serial clock low-speed parallel clock rateswitch pipephydonestatus reset_int reset_int pci express clock switch circuitry pcie_gen2switch pcie_gen2switch_done cmu0_pll output clock cmu1_pll output clock receiver phase compensation fifo transmitter phase compensation fifo charge pump + loop filter ltr/ltd controller phase detector (pd) pipe interface fpga fabric phase frequency detector (pd) v co /l pcie_gen2switch clock and data recovery (cdr) unit transceiver channel transceiver pcs local clock divider /m /2 1 0 pci express rate switch controller pci express clock switch circuitry /2 /1, /2, /4 /1, /2, /4 /4, /5, /8, /10 table 1?54. transceiver clock frequencies signaling rates in pci express (pipe) 1 mode transceiver clocks gen1 (2.5 gbps) to gen2 (5 gbps) switch (low-to-high transition on the rateswitch signal) gen2 (5 gbps) to gen1 (2.5 gbps) switch (high-to-low transition on the rateswitch signal) high-speed serial clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz low-speed parallel clock 250 mhz to 500 mhz 500 mhz to 250 mhz serial recovered clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz parallel recovered clock 250 mhz to 500 mhz 500 mhz to 250 mhz fpga fabric-transceiver interface clock 125 mhz to 250 mhz 250 mhz to 125 mhz 1?142 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the pci express (pipe) clock switch circuitry in the local clock divider block performs the clock switch between 250 mhz and 500 mhz on the low-speed parallel clock when switching between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates. it indicates successful completion of clock switch on the pcie_gen2switchdone signal to the pci express (pipe) rateswitch controller. the pci express (pipe) rateswitch controller forwards the clock switch completion status to the pci express (pipe) interface block. the pci express (pipe) interface block communicates the clock switch completion status to the phy-mac layer by asserting the pipephydonestatus signal for one parallel clock cycle. figure 1?111 shows the low-speed parallel clock switch between gen1 (250 mhz) and gen2 (500 mhz) in response to the change in the logic level on the rateswitch signal. the rateswitch completion is shown marked with a one clock cycle assertion of the pipephydonestatus signal. 1 time t1 from a transition on the rateswitch signal to the assertion of pipephydonestatus is pending characterization. as a result of the signaling rateswitch between gen1 (2.5 gbps) and gen2 (5 gbps), the fpga fabric-transceiver interface clock switches between 125 mhz and 250 mhz. the fpga fabric-transceiver interface clock clocks the read side and write side of the transmitter phase compensation fifo and the receiver phase compensation fifo, respectively. it is also routed to the fpga fabric on a global or regional clock resource and looped back to clock the write port and read port of the transmitter phase compensation fifo and the receiver phase compensation fifo, respectively. due to the routing delay between the write and read clock of the transmitter and receiver phase compensation fifos, the write pointers and read pointers might collide during a rateswitch between 125 mhz and 250 mhz. to avoid collision of the phase compensation fifo pointers, the pci express (pipe) rateswitch controller automatically disables and resets the pointers during clock switch. when the pci express (pipe) clock switch circuitry in the local clock divider indicates successful clock switch completion, the pci express (pipe) rateswitch controller releases the phase compensation fifo pointer resets. figure 1?111. low-speed parallel clock switching in pci express (pipe) 1 mode pipephydonestatus low-speed parallel clock rateswitch 250 mhz (gen1) 500 mhz (gen2) 250 mhz (gen1) t1 t1 chapter 1: stratix iv transceiver architecture 1?143 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates in pci express (pipe) 4 mode figure 1?112 shows the pci express (pipe) rateswitch circuitry in pci express (pipe) 4 mode configured at gen2 (5 gbps) data rate. in pci express (pipe) 4 mode configured at gen2 (5 gbps) data rate, when the pci express (pipe) rateswitch controller sees a transition on the rateswitch signal, it sends the pcie_gen2switch control signal to the pci express (pipe) clock switch circuitry in the cmu0 clock divider block and the receiver cdr to switch to the instructed signaling rate. a low-to-high transition on the rateswitch signal initiates a gen1 (2.5 gbps) to gen2 (5 gbps) signaling rateswitch. a high-to-low transition on the rateswitch signal initiates a gen2 (5 gbps) to gen1 (2.5 gbps) signaling rateswitch. table 1?55 lists the transceiver clock frequencies when switching between the 2.5 gbps and 5 gbps signaling rates. figure 1?112. dynamic switch signaling in pci express (pipe) 4 mode pipephydonestatu s[3:0] high-speed serial clock to the four (pipe x4) bonded channels low-speed parallel clock to the four (pipe x4) bonded channels rx_datain rx_cruclk rx_locktorefclk rx_lockt odata signal detect rx_freqlocked serial recovered clock parallel recovered clock rateswitch reset_int reset_int pci express clock switch circuitry pcie_gen2switch pcie_gen2switch_done receiver phase compensation fifo transmitter phase compensation fifo charge pump + loop filter ltr/ltd controller phase detector (pd) pipe interface fpga fabric phase frequency detector (pd) v co /l pcie_gen2switch clock and data recovery (cdr) unit transceiver block transceiver pcs ccu cmu0_channel cmu1_channel /m cmu0 pll /2 1 0 pci express rate switch controller pci express clock switch circuitry /2 /1, /2, /4 /1, /2, /4 /4, /5, /8, /10 cmu1 clock divider cmu0 clock divider cmu1 pll /1, /2, /4 /4, /5, /8, /10 table 1?55. transceiver clock frequencies signaling rates in pci express (pipe) 4 mode (part 1 of 2) transceiver clocks gen1 (2.5 gbps) to gen2 (5 gbps) switch (low-to-high transition on the rateswitch signal) gen2 (5 gbps) to gen1 (2.5 gbps) switch (high-to-low transition on the rateswitch signal) high-speed serial clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz low-speed parallel clock 250 mhz to 500 mhz 500 mhz to 250 mhz serial recovered clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz 1?144 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the pci express (pipe) clock switch circuitry in the cmu0 clock divider block performs the clock switch between 250 mhz and 500 mhz on the low-speed parallel clock when switching between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates. it indicates successful completion of clock switch on the pcie_gen2switchdone signal to the pci express (pipe) rateswitch controller. the pci express (pipe) rateswitch controller forwards the clock switch completion status to the pci express (pipe) interface block. the pci express (pipe) interface block communicates the clock switch completion status to the phy-mac layer by asserting the pipephydonestatus signal of all bonded channels for one parallel clock cycle. figure 1?113 shows the low-speed parallel clock switch between gen1 (250 mhz) and gen2 (500 mhz) in response to the change in the logic level on the rateswitch signal. the rateswitch completion is shown marked with a one clock cycle assertion of the pipephydonestatus signal of all bonded channels. 1 time t1 from a transition on the rateswitch signal to the assertion of pipephydonestatus is pending characterization. as a result of the signaling rateswitch between gen1 (2.5 gbps) and gen2 (5 gbps), the fpga fabric-transceiver interface clock switches between 125 mhz and 250 mhz. the fpga fabric-transceiver interface clock clocks the read side and write side of the transmitter phase compensation fifo and the receiver phase compensation fifo of all bonded channels, respectively. it is also routed to the fpga fabric on a global or regional clock resource and looped back to clock the write port and read port of the transmitter phase compensation fifo and the receiver phase compensation fifo, respectively. due to the routing delay between the write and read clock of the transmitter and receiver phase compensation fifos, the write pointers and read pointers might collide during a rateswitch between 125 mhz and 250 mhz. to avoid collision of the phase compensation fifo pointers, the pci express (pipe) rateswitch parallel recovered clock 250 mhz to 500 mhz 500 mhz to 250 mhz fpga fabric-transceiver interface clock 125mhz to 250mhz 250mhz to 125mhz table 1?55. transceiver clock frequencies signaling rates in pci express (pipe) 4 mode (part 2 of 2) transceiver clocks gen1 (2.5 gbps) to gen2 (5 gbps) switch (low-to-high transition on the rateswitch signal) gen2 (5 gbps) to gen1 (2.5 gbps) switch (high-to-low transition on the rateswitch signal) figure 1?113. low-speed parallel clock switching in pci express (pipe) 4 mode low-speed parallel clock rateswitch pipephydonestatus[3] pipephydonestatus[0] t1 t1 250 mhz (gen1) 500 mhz (gen2) 250 mhz (gen1) chapter 1: stratix iv transceiver architecture 1?145 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 controller automatically disables and resets the phase compensation fifo pointers of all bonded channels during clock switch. when the pci express (pipe) clock switch circuitry in the local clock divider indicates successful clock switch completion, the pci express (pipe) rateswitch controller releases the phase compensation fifo pointer resets. dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates in pci express (pipe) 8 mode figure 1?114 shows the pci express (pipe) rateswitch circuitry in pci express (pipe) 8 mode configured at gen2 (5 gbps) data rate. figure 1?114. dynamic switch signaling in pci express (pipe) 8 mode high-speed serial clock to the eight bonded channels in the master and slave transceiver blocks low-speed parallel clock to the eight bonded channels in the master and slave transceiver blocks pipephydonestatu s[3:0] rx_datain rx_cruclk rx_locktorefclk rx_lockt odata signal detect rx_freqlocked serial recovered clock parallel recovered clock rateswitch reset_int reset_int pci express clock switch circuitry pcie_gen2switch pcie_gen2switch_done receiver phase compensation fifo transmitter phase compensation fifo charge pump + loop filter ltr/ltd controller phase detector (pd) pipe interface fpga fabric phase frequency detector (pd) v co /l pcie_gen2switch pcie_gen2switch clock and data recovery (cdr) unit master transceiver block transceiver pcs ccu cmu0_channel cmu1_channel /m cmu0 pll /2 1 0 pci express rate switch controller /2 /1, /2, /4 /1, /2, /4 /4, /5, /8, /10 cmu1 clock divider cmu0 clock divider cmu1 pll /1, /2, /4 /4, /5, /8, /10 rx_datain rx_cruclk rx_locktorefclk rx_lockt odata signal detect rx_freqlocked serial recovered clock parallel recovered clock reset_int reset_int receiver phase compensation fifo transmitter phase compensation fifo charge pump + loop filter ltr/ltd controller phase detector (pd) pipe interface phase frequency detector (pd) v co /l rateswitch_asn clock and data recovery (cdr) unit slave transceiver block transceiver pcs /m /2 1 0 /2 /1, /2, /4 rateswitch_asn pipephydonestatu s[7:4] pci express clock switch circuitry 1?146 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation in pci express (pipe) 8 mode configured at 5 gbps data rate, when the pci express (pipe) rateswitch controller sees a transition on the rateswitch signal, it sends the pcie_gen2switch control signal to the pci express (pipe) clock switch circuitry in the cmu0 clock divider of the master transceiver block and the receiver cdr in all eight bonded channels to switch to the instructed signaling rate. a low-to-high transition on the rateswitch signal initiates a gen1 (2.5 gbps) to gen2 (5 gbps) signaling rateswitch. a high-to-low transition on the rateswitch signal initiates a gen2 (5 gbps) to gen1 (2.5 gbps) signaling rateswitch. table 1?56 lists the transceiver clock frequencies when switching between the 2.5 gbps and 5 gbps signaling rates. the pci express (pipe) clock switch circuitry in the cmu0 clock divider of the master transceiver block performs the clock switch between 250 mhz and 500 mhz on the low-speed parallel clock when switching between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates. it indicates successful completion of clock switch on the pcie_gen2switchdone signal to the pci express (pipe) rateswitch controller. the pci express (pipe) rateswitch controller forwards the clock switch completion status to the pci express (pipe) interface block. the pci express (pipe) interface block communicates the clock switch completion status to the phy-mac layer by asserting the pipephydonestatus signal of all eight bonded channels for one parallel clock cycle. table 1?56. transceiver clock frequencies signaling rates in pci express (pipe) 8 mode transceiver clocks gen1 (2.5 gbps) to gen 2 (5 gbps) switch (low-to-high transition on the rateswitch signal) gen2 (5 gbps) to gen1 (2.5 gbps) switch (high-to-low transition on the rateswitch signal) high-speed serial clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz low-speed parallel clock 250 mhz to 500 mhz 500 mhz to 250 mhz serial recovered clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz parallel recovered clock 250 mhz to 500 mhz 500 mhz to 250 mhz fpga fabric-transceiver interface clock 125 mhz to 250 mhz 250 mhz to 125 mhz chapter 1: stratix iv transceiver architecture 1?147 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?115 shows the low-speed parallel clock switch between gen1 (250 mhz) and gen2 (500 mhz) in response to the change in the logic level on the rateswitch signal. the rateswitch completion is shown marked with a one clock cycle assertion of the pipephydonestatus signal of all eight bonded channels. 1 time t1 from a transition on the rateswitch signal to the assertion of pipephydonestatus is pending characterization. as a result of the signaling rateswitch between gen1 (2.5 gbps) and gen2 (5 gbps), the fpga fabric-transceiver interface clock switches between 125 mhz and 250 mhz. the fpga fabric-transceiver interface clock clocks the read side and write side of the transmitter phase compensation fifo and the receiver phase compensation fifo of all eight bonded channels, respectively. it is also routed to the fpga fabric on a global or regional clock resource and looped back to clock the write port and read port of the transmitter phase compensation fifo and the receiver phase compensation fifo, respectively. due to the routing delay between the write and read clock of the transmitter and receiver phase compensation fifos, the write pointers and read pointers might collide during a rateswitch between 125 mhz and 250 mhz. to avoid collision of the phase compensation fifo pointers, the pci express (pipe) rateswitch controller automatically disables and resets the phase compensation fifo pointers of all eight bonded channels during clock switch. when the pci express (pipe) clock switch circuitry in the local clock divider indicates successful clock switch completion, the pci express (pipe) rateswitch controller releases the phase compensation fifo pointer resets. pci express (pipe) cold reset requirements the pci express (pipe) base specification 2.0 defines the following three types of conventional resets to the pci express (pipe) system components: cold reset?fundamental reset after power up warm reset?fundamental reset without removal and re-application of power hot reset?in-band conventional reset initiated by the higher layer by setting the hot reset bit in the ts1 or ts2 training sequences figure 1?115. low-speed parallel clock switching in pci express (pipe) 8 mode t1 low-speed parallel clock rateswitch pipephydonestatus[7] pipephydonestatus[0] 250 mhz (gen1) 500 mhz (gen2) 250 mhz (gen1) t1 1?148 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation fundamental reset is provided by the system to the component or adapter card using the auxiliary signal perst# . the pci express (pipe) base specification 2.0 specifies that perst# must be kept asserted for a minimum of 100 ms ( tpvperl ) after the system power becomes stable in a cold reset situation. additionally, all system components must enter the ltssm detect state within 20 ms and the link must become active within 100 ms after de-assertion of the perst# signal. this implies that each pci express (pipe) system component must become active within 200 ms after the power becomes stable. 1 the link being active is interpreted as the physical layer device coming out of electrical idle in the l0 state of the ltssm state machine. figure 1?116 lists the pci express (pipe) cold reset timing requirements. the time taken by a pci express (pipe) port implemented using the stratix iv gx and gt device to go from power up to link active state is described below: power on reset (por)?begins after power rails become stable. typically takes 12 ms fpga configuration/programming?begins after por. configuration time depends on the fpga density time taken from de-assertion of perst# to link active?typically takes 40 ms (pending characterization and verification of pci express [pipe] soft ip and hard ip) to meet the pci express (pipe) specification of 200 ms from power on to link active, the stratix iv gx and gt device configuration time must be less than 148 ms (200 ms ?12 ms for power on reset and -40 ms for the link to become active after perst# de-assertion). figure 1?116. pci express (pipe) cold reset requirements 12 4 3 power rail perst# t pvperl 100 ms t 2-3 d" 20 ms t 2-4 d" 100 ms marker 1: power becomes stable marker 2: perst# gets de-asserted marker 3: maximum time for marker 2 fo r the ltssm to enter the detect state marker 4: maximum time for marker 2 fo r the link to become active chapter 1: stratix iv transceiver architecture 1?149 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 table 1?57 shows the typical configuration times for stratix iv gx devices when configured using the fast passive parallel (fpp) configuration scheme at 125 mhz. f for more information about the fpp configuration scheme, refer to the configuration, design security, remote system upgrades in stratix iv devices chapter . 1 most flash memories available can run up to 100 mhz. to configure the stratix iv gx and gt device at 125 mhz, altera recommends using a max ii device to convert the 16-bit flash memory output at 62.5 mhz to 8-bit configuration data input to the stratix iv gx and gt device at 125 mhz. pci express electrical gold test with compliance base board (cbb) the pci express electrical gold test requires the v2.0 cbb to be connected to the device under test (dut). the cbb sends out a 100 mhz signal for 1 ms to indicate the link training and status state machine (ltssm) of the downstream device under test (dut) to transition to several polling compliance states. under these states, the dut sends out data at gen1, gen2 (with -3.5db de-emphasis), and gen2 (with -6 db de-emphasis) rates, which can be observed in the scope to confirm electrical signal compliance. the cbb is dc-coupled to the downstream receiver. when you use the stratix iv gx and gt device as dut, because of being dc-coupled to cbb with a different common mode level, the stratix iv gx and gt receiver does not receive the required v cm (0.85 v) to detect the signal. the logic in the fpga fabric that implements ltssm cannot transition to the multiple polling compliance states to complete the test. therefore, when testing with the cbb, force the ltssm implemented in the fpga fabric to transfer to different polling compliance states using an external push button or user logic. if you use the stratix iv gx and gt pci express hard ip block, assert the testin[5] port of the pci express compiler-generated wrapper file in your design. asserting this port forces the ltssm within the hard ip block to transition to these states. the testin[5] port must be asserted for a minimum of 16 ns and less than 24 ms. f for more information about the pci express (pipe) hard ip block, refer to the pci express compiler user guide . table 1?57. typical configuration times for stratix iv gx devices configured with fast passive parallel stratix iv gx stratix iv gt configuration time (ms) ep4sgx70 ? 48 ep4sgx110 ? 48 ep4sgx230 ep4s(40/100)g2 95 ep4sgx290 ep4s100g3 128 ep4sgx360 ep4s100g4 128 ep4sgx530 ep4s(40/100)g5 172 1?150 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation xaui mode xaui is an optional, self-managed interface that you can insert between the reconciliation sublayer and the phy layer to transparently extend the physical reach of the xgmii. xaui addresses several physical limitations of the xgmii. xgmii signaling is based on the hstl class 1 single-ended i/o standard, which has an electrical distance limitation of approximately 7 cm. because xaui uses a low-voltage differential signaling method, the electrical limitation is increased to approximately 50 cm. another advantage of xaui is simplification of backplane and board trace routing. xgmii is composed of 32 transmit channels, 32 receive channels, 1 transmit clock, 1 receive clock, 4 transmitter control characters, and 4 receive control characters for a 74-pin wide interface. xaui, on the other hand, only consists of 4 differential transmitter channels and 4 differential receiver channels for a 16-pin wide interface. this reduction in pin count significantly simplifies the routing process in the layout design. figure 1?117 shows the relationships between the xgmii and xaui layers. figure 1?117. xaui and xgmii layers osi reference model layers application presentation session transport network data link physical pma pmd medium 10 gb/s optional xgmii extender physical layer device mac control (optional) logical link control (llc) lan carrier sense multiple access/collision detect (csma/cd) layers higher layers reconciliation media access control (mac) pcs 10 gigabit media independent interface xgmii extender sublayer xgmii extender sublayer 10 gigabit attachment unit interface 10 gigabit media independent interface medium dependent interface chapter 1: stratix iv transceiver architecture 1?151 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 the xgmii interface consists of four lanes of 8 bits. at the transmit side of the xaui interface, the data and control characters are converted within the xgxs into an 8b/10b encoded data stream. each data stream is then transmitted across a single differential pair running at 3.125 gbps (3.75 gbps for higig). at the xaui receiver, the incoming data is decoded and mapped back to the 32-bit xgmii format. this provides a transparent extension of the physical reach of the xgmii and also reduces the interface pin count. in stratix iv gx and gt xaui functional mode, the interface between the transceiver and fpga fabric is 64 bits wide (four channels of 16 bits each) at single data rate. xaui functions as a self-managed interface because code group synchronization, channel deskew, and clock domain decoupling is handled with no upper layer support requirements. this functionality is based on the pcs code groups that are used during the ipg time and idle periods. pcs code groups are mapped by the xgxs to xgmii characters, as specified in table 1?58 . figure 1?118 shows an example of mapping between xgmii characters and the pcs code groups that are used in xaui. the idle characters are mapped to a pseudo-random sequence of /a/, /r/, and /k/ code groups. table 1?58. xgmii character to pcs code-group mapping xgmii txc xgmii txd (1) pcd code group description 0 00 through ff dxx,y normal data transmission 1 07 k28.0 or k28.3 or k28.5 idle in ||i|| 1 07 k28.5 idle in ||t|| 1 9c k28.4 sequence 1f b k 2 7 . 7 s t a r t 1f d k 2 9 . 7 t e r m i n a t e 1 fe k30.7 error 1 any other value k30.7 invalid xgmii character note to tab l e 1 ?5 8 : (1) the values in the xgmii txd column are in hexadecimal. figure 1?118. example of mapping xgmii characters to pcs code groups dp t/rxd<7..0> |s ddd - - - - - - - - - - - - d dp t/rxd<15..8> |dp ddd t dp t/rxd<23..16> |dp ddd | dp t/rxd<31..24> | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dp ddd ddd ddd ddd ddd | lane 0 k r s ak rr lane 1 k r dp ak rr lane 2 k r k a k rr lane 3 k r k a k k k k k r r r r rr dp ddd - - - - - - - - - - - - d dp ddd t dpdp dd dpdp d d dd ddd ddd ddd ddd xgmii pcs 1?152 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation pcs code groups are sent via pcs ordered sets. pcs ordered sets consist of combinations of special and data code groups defined as a column of code groups. these ordered sets are composed of four code groups beginning in lane 0. table 1?59 lists the defined idle ordered sets (||i||) that are used for the self-managed properties of xaui. stratix iv gx and gt transceivers configured in xaui mode provide the following protocol features: xgmii-to-pcs code conversion at the transmitter pcs-to-xgmii code conversion at the receiver 8b/10b encoding and decoding ieee p802.3ae-compliant synchronization state machine 100 ppm clock rate compensation channel deskew of four lanes of the xaui link table 1?59. defined idle ordered set code ordered set number of code groups encoding ||i|| idle substitute for xgmii idle ||k|| synchronization column 4 /k28.5/k28.5/k28.5/k28.5/ ||r|| skip column 4 /k28.0/k28.0/k28.0/k28.0/ ||a|| align column 4 /k28.3/k28.3/k28.3/k28.3/ chapter 1: stratix iv transceiver architecture 1?153 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?119 shows the xaui mode configuration supported in stratix iv gx and gt devices. figure 1?119. stratix iv gx and gt xaui mode configuration xaui disabled enabled rate match fifo byte serdes byte ordering stratix iv gx and gt configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit enabled enabled channel bonding disabled deskew fifo enabled pma-pcs interface width functional mode data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder fpga fabric-transceiver interface width fpga fabric-transceiver interface frequency (mhz) 156.25- 187.5 16-bit automatic synchronization state machine (10-bit/k28.5/) x4 3.125 - 3.75 deterministic latency 10-bit 20-bit interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 4.5 - 6 14.5 - 18 1?154 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation xaui mode datapath figure 1?120 shows the altgx megafunction transceiver datapath when configured in xaui mode. figure 1?120. transceiver datapath in xaui mode rx phase compensation fifo byte de- serializer de- serializer cdr /2 ch0 parallel recovered clock low-speed parallel clock from cmu 0 clock divider receiver channel pma receiver channel pcs fpga fabric tx_coreclk[3:2] /2 ch0 parallel recovered clock ch2 parallel recovered clock low-speed parallel clock from cmu 0 clock divider rx_coreclk[3:2] rx_coreclk[1:0] /2 coreclkout cmu1_pll cmu0_pll cmu1_channel cmu0_channel cmu0 clock divider low-sp eed parallel clock input reference clock fpga fabric-transceiver interface clock receiver channel pma cmu1 clock divider serializer transmitter channel pcs transmitter channel pma /2 wrclk wrclk rdclk rdclk low-speed parallel clock from cmu 0 click divider receiver channel pcs tx_coreclk[1:0] tx phase compensation fifo byte serializer 8b/10b encoder serializer transmitter channel pcs transmitter channel pma /2 wrclk wrclk rdclk rdclk low-speed parallel clock from cmu 0 clock divider high-speed serial clock channel 0 channel 1 channel 2 channel 3 channel 2 channel 3 channel 0 channel 1 ch0 parallel recovered clock word aligner deskew fifo rate match fifo 8b/10b decoder input reference clock rx phase compensation fifo byte de- serializer 8b/10b decoder rate match fifo deskew fifo word aligner de- serializer cdr 8b/10b encoder byte serializer tx phase compensation fifo chapter 1: stratix iv transceiver architecture 1?155 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 xgmii-to-pcs code conversion at the transmitter in xaui mode, the 8b/10b encoder in the stratix iv gx and gt transmitter datapath is controlled by a transmitter state machine that maps various 8-bit xgmii codes to 10-bit pcs code groups. this state machine complies with the ieee p 802.3ae pcs transmit source state diagram shown in figure 1?121 . figure 1?121. xgmii-to-pcs code conversion in xaui mode (note 1) note to figure 1?121 : (1) this figure is from ieee p802.3ae. send_random_k tx_code_group<39:0> ? ||k|| send_random_r tx_code_group<39:0> ? ||r|| send_random_a tx_code_group<39:0> ? ||a|| a_cnt 0 * cod_sel=1 a_cnt 0 * cod_sel=1 a_cnt 0 * cod_sel=1 a_cnt=0 a_cnt=0 a_cnt 0 * cod_sel=1 !q_det * cod_sel=1 q_det q_det !q_det !q_det * cod_set=1 a b b b a a b a cod_set=1 cod_set=1 b a pudr send_k tx_code_group<39:0> ? ||k|| next_ifg ? a (next_ifg + a_c nt 0) next_ifg = a_c nt 0 pudr send_a tx_code_group<39:0> ? ||a|| next_ifg ? k send_q tx_code_group<39:0> ? tqmsg q_det ? k pudr pudr send_q if tx=||t|| the n cvtx_terminate tx_code_group<39:0> ? encode(tx) !reset !(tx=||idle|| + tx=||q|| pudr pudr send_random_q tx_code_group<39:0> ? tqmsg q_det ? false pudr reset uct uct 1?156 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation table 1?60 lists the xgmii-to-pcs code group conversion in xaui functional mode. the xgmii txc control signal is equivalent to the tx_ctrlenable signal; the xgmii txd control signal is equivalent to the tx_datain[7:0] signal. pcs-to-xgmii code conversion at the receiver in xaui mode, the 8b/10b decoder in the stratix iv gx and gt receiver datapath is controlled by a xaui receiver state machine that converts received pcs code groups into specific 8-bit xgmii codes. this state machine complies with the ieee p802.3ae specifications. table 1?61 lists the pcs-to-xgmii code group conversion in xaui functional mode. the xgmii rxc control signal is equivalent to the rx_ctrldetect signal; the xgmii rxd control signal is equivalent to the rx_dataout[7:0] signal. table 1?60. xgmii character to pcs code-group mapping xgmii txc xgmii txd (1) pcd code group description 0 00 through ff dxx,y normal data transmission 1 07 k28.0 or k28.3 or k28.5 idle in ||i|| 1 07 k28.5 idle in ||t|| 1 9c k28.4 sequence 1f b k 2 7 . 7 s t a r t 1f d k 2 9 . 7 t e r m i n a t e 1f e k 3 0 . 7 e r r o r 1 any other value k30.7 invalid xgmii character note to tab l e 1 ?5 8 : (1) the values in the xgmii txd column are in hexadecimal. table 1?61. pcs code group to xgmii character mapping xgmii rxc xgmii rxd (1) pcd code group description 0 00 through ff dxx,y normal data transmission 1 07 k28.0 or k28.3 or k28.5 idle in ||i|| 1 07 k28.5 idle in ||t|| 19 c k 2 8 . 4 s e q u e n c e 1f b k 2 7 . 7 s t a r t 1f d k 2 9 . 7 t e r m i n a t e 1 fe k30.7 error 1 fe invalid code group received code group note to tab l e 1 ?5 8 : (1) the values in the xgmii rxd column are in hexadecimal. chapter 1: stratix iv transceiver architecture 1?157 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 word aligner the word aligner in xaui functional mode is configured in automatic synchronization state machine mode. the quartus ii software automatically configures the synchronization state machine to indicate synchronization when the receiver receives four /k28.5/ comma code groups without intermediate invalid code groups. the synchronization state machine implemented in xaui mode is compliant to the pcs synchronization state diagram specified in clause 48 of the ieee p802.3ae specification and is shown in figure 1?122 . figure 1?122. ieee 802.3ae pcs synchronization state diagram (note 1) note to figure 1?122 : (1) this figure is from ieee p802.3ae. power_on=true+mr_main_rest=true + (signal_detectchan ge=true + mr_loopback=false +pudi) (signal_detect=ok+mr_loopback=true)* * pudi([/comma/] pudi([/|dv|/] rx_even=false+pudi([/comma/] pudi(![/comma/] *?[/in valid/] pudi([/|dv|/] cggood *good_cgs = 3 cggood *good_cgs = 3 cggood *good_cgs = 3 cggood *good_cgs = 3 cggood cggood pudi(![/|dv|/] pudi(![/|dv|/] [pudi * signal_detect=fail + mr_loopback=false] + pudi(![/comma/]) loss_of_sync sync_status ? fail rx_even ? ! rx_even sudi comma_detect_1 rx_even ? true sudi syn c_acquired_2 rx_even ? ! rx_even sudi good_cgs ? 0 syn c_acquired_3 syn c_acquired_4 cgbad cgbad cggood cgbad cgbad cggood cgbad cgbad cgbad syn c_acquired_2a syn c_acquired_3a syn c_acquired_4a acquire_sy nc_1 sudi comma_detect_2 sudi 2 cggood *good_cgs = 3 cggood *good_cgs = 3 3 3 2 pudi(![/comma/] *?[/in valid/] rx_even ? true rx_even=false+pudi([/comma/] cgbad cgbad acquire_sy nc_2 sudi rx_even ? ! rx_even pudi(![/|dv|/] comma_detect_3 sudi rx_even ? true pudi([/|dv|/] syn c_acquired_1 sudi sync_status ? ok rx_even ? ! rx_even rx_even ? ! rx_even rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 rx_even ? ! rx_even sudi good_cgs ? 0 rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 rx_even ? ! rx_even sudi good_cgs ? 0 rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 1?158 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation receiver synchronization is indicated on the rx_syncstatus port of each channel. a high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that it has fallen out of synchronization. the receiver loses synchronization when it detects four invalid code groups separated by less than four valid code groups or when it is reset. deskew fifo code groups received across four lanes in a xaui link can be misaligned with respect to one another because of skew in the physical medium or differences between the independent clock recoveries per lane. the xaui protocol allows a maximum skew of 40 ui (12.8 ns) as seen at the receiver of the four lanes. the xaui protocol requires the physical layer device to implement a deskew circuitry to align all four channels. to enable the deskew circuitry at the receiver to align the four channels, the transmitter sends a /a/ (/k28.3/) code group simultaneously on all four channels during inter-packet gap. the skew introduced in the physical medium and the receiver channels can be /a/ code groups to be received misaligned with respect to each other. the deskew operation is performed by the deskew fifo in xaui functional mode. the deskew fifo in each channel receives data from its word aligner. the deskew operation begins only after link synchronization is achieved on all four channels as indicated by a high on the rx_syncstatus signal from the word aligner in each channel. until the first /a/ code group is received, the deskew fifo read and write pointers in each channel are not incremented. after the first /a/ code group is received, the write pointer starts incrementing for each word received but the read pointer is frozen. if the /a/ code group is received on each of the four channels within 10 recovered clock cycles of each other, the read pointer of all four deskew fifos is released simultaneously, aligning all four channels. figure 1?123 shows lane skew at the receiver input and how the deskew fifo uses the /a/ code group to align the channels. figure 1?123. receiver input lane skew in xaui mode lanes are deskewed by lining up the "align"/a/, code groups lane skew at receiver input a lane 0 k k r a k r r k k k rr lane 1 k k r a k r r k k k rr lane 0 k k r k r r k k k rr lane 1 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr chapter 1: stratix iv transceiver architecture 1?159 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 after alignment of the first ||a|| column, if three additional aligned ||a|| columns are observed at the output of the deskew fifos of the four channels, the rx_channelaligned signal is asserted high, indicating channel alignment is acquired. after acquiring channel alignment, if four misaligned ||a|| columns are seen at the output of the deskew fifos in all four channels with no aligned ||a|| columns in between, the rx_channelaligned signal is de-asserted low, indicating loss-of-channel alignment. the deskew fifo operation in xaui functional mode is compliant with the pcs deskew state machine diagram specified in clause 48 of the ieee p 802.3ae, as shown in figure 1?124 . figure 1?124. deskew fifo in xaui mode (note 1) note to figure 1?124 : (1) this figure is from ieee p802.3ae. reset + (sync_status=fail * sudi) sync_status ok * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi sudi(![/||a||/]) loss_of_alignment align_status ? fail enable_deskew ? true audi align_detect_1 enable_deskew ? false audi align_detect_2 audi align_detect_3 audi c !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) align _acquired_1 enable_deskew ? false audi align _acquired_2 audi align _acquired_3 audi a b c !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) align _acquired_4 audi b sudi(![/||a||/]) a sudi(![/||a||/]) 1?160 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation rate match fifo in xaui mode, the rate match fifo is capable of compensating for up to 100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. the xaui protocol requires the transmitter to send /r/ (/k28.0/) code groups simultaneously on all four lanes (denoted as ||r|| column) during inter-packet gaps, adhering to rules listed in the ieee p802.3ae specification. the rate match fifo operation in xaui mode is compliant to the ieee p 802.3ae specification. the rate match operation begins after: the synchronization state machine in the word aligner of all four channels indicates synchronization has been acquired by driving the rx_syncstatus signal high the deskew fifo indicates alignment has been acquired by driving the rx_channelaligned signal high the rate match fifo looks for the ||r|| column (simultaneous /r/ code group on all four channels) and deletes or inserts ||r|| column to prevent the rate match fifo from overflowing or under-running. the rate match fifo can insert or delete as many ||r|| columns as necessary to perform the rate match operation. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , indicating rate match fifo deletion and insertion events, respectively, are forwarded to the fpga fabric. if an ||r|| column is deleted, the rx_rmfifodeleted flag from each of the four channels goes high for one clock cycle per deleted ||r|| column. if an ||r|| column is inserted, the rx_rmfifoinserted flag from each of the four channels goes high for one clock cycle per inserted ||r|| column. figure 1?125 shows an example of rate match deletion in the case where three ||r|| columns are required to be deleted. for more information, refer to ?rate match fifo in xaui mode? on page 1?77 . figure 1?125. rate match deletion in xaui mode datain[3] rx_rmfifodatadeleted k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 first ||r|| column second ||r|| column third ||r|| column fourth ||r|| column k28.5 datain[2] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 datain[1] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 datain[0] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 dataout[3] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[2] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[1] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[0] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 chapter 1: stratix iv transceiver architecture 1?161 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?126 shows an example of rate match insertion in the case where two ||r|| columns are required to be inserted. for more information, refer to ?rate match (clock rate compensation) fifo? on page 1?74 . gige mode ieee 802.3 defines the 1000 base-x phy as an intermediate, or transition, layer that interfaces various physical media with the media access control (mac) in a gigabit ethernet system. it shields the mac layer from the specific nature of the underlying medium. the 1000 base-x phy is divided into three sub-layers: physical coding sublayer physical media attachment physical medium dependent (pmd) the pcs sublayer interfaces with the mac through the gigabit medium independent interface (gmii). the 1000 base-x phy defines a physical interface data rate of 1gbps. figure 1?126. rate match insertion in xaui mode datain[3] rx_rmfifodatainserted k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 first ||r|| column second ||r|| column k28.5 datain[2] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 datain[1] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 datain[0] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 dataout[3] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 dataout[2] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 dataout[1] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 dataout[0] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 1?162 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?127 shows the 1000 base-x phy position in a gigabit ethernet osi reference model. stratix iv gx and gt transceivers, when configured in gige functional mode, have built-in circuitry to support the following pcs and pma functions defined in the ieee 802.3 specification: 8b/10b encoding and decoding synchronization upstream transmitter and local receiver clock frequency compensation (rate matching) clock recovery from the encoded data forwarded by the receiver pmd serialization and deserialization 1 stratix iv gx and gt transceivers do not have built-in support for other pcs functions; for example, auto-negotiation state machine, collision-detect, and carrier-sense. if required, you must implement these functions in a pld logic array or external circuits. figure 1?127. 1000 base-x phy in a gigabit ethernet osi reference model osi reference model layers application presentation session transport network data link physical medium gmii 1000 base-x phy mac (optional) llc lan csma/cd layers higher layers reconciliation mac pmd pcs pma chapter 1: stratix iv transceiver architecture 1?163 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?128 shows the gige mode configuration supported in stratix iv gx devices. figure 1?128. gige mode for stratix iv gx devices gige disabled enabled rate match fifo byte serdes byte ordering stratix iv gx configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit functional mode enabled disabled channel bonding disabled 125 pma-pcs interface width data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder fpga fabric-transceiver interface width fpga fabric-transceiver interface frequency (mhz) 8-bit 1.25 x1 automatic synchronization state machine (7-bit comma, 10-bit /k28.5/) deterministic latency 10-bit 20-bit interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 5 - 6 20 - 24 1?164 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation gige mode datapath figure 1?129 shows the transceiver datapath when configured in gige functional mode. table 1?62 shows the transceiver datapath clock frequencies in gige functional mode. 8b/10b encoder in gige mode, the 8b/10b encoder clocks in 8-bit data and 1-bit control identifiers from the transmitter phase compensation fifo and generates 10-bit encoded data. the 10-bit encoded data is fed to the serializer. for more information about 8b/10b encoder functionality, refer to ?8b/10b encoder? on page 1?19 . gige protocol?ordered sets and special code groups table 1?63 lists ordered sets and special code groups specified in the ieee 802.3 specification. figure 1?129. gige mode datapath tx phase compensation fifo 8b/10b encoder 8b/10b decoder serializer de- serializer transmitter channel pcs transmitter channel pma wrclk rdclk low-speed parallel clock high-sp eed serial cloc k tx_coreclk[0] rx phase compensation fifo rate match fifo word aligner cdr tx_clkout[0] parallel recovered clock low-speed parallel clock rx_coreclk[0] receiver channel pcs receiver channel pma fpga fabric-transceiver interface clock fpga fabric local clock divider 8b/10b decoder de- serializer table 1?62. transceiver datapath clock frequencies in gige mode functional mode data rate high-speed serial clock frequency parallel recovered clock and low-speed parallel clock frequency fpga fabric-transceiver interface clock frequency gige 1.25 gbps 625 mhz 125 mhz 125 mhz table 1?63. gige ordered sets (part 1 of 2) code ordered set number of code groups encoding /c/ configuration ? alternating /c1/ and /c2/ /c1/ configuration 1 4 /k28.5/d21.5/ config_reg (1) /c2/ configuration 2 4 /k28.5/d2.2/ config_reg (1) chapter 1: stratix iv transceiver architecture 1?165 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 idle ordered-set generation the ieee 802.3 specification requires the gige phy to transmit idle ordered sets (/i/) continuously and repetitively whenever the gmii is idle. this ensures that the receiver maintains bit and word synchronization whenever there is no active data to be transmitted. in gige functional mode, any /dx.y/ following a /k28.5/ comma is replaced by the transmitter with either a /d5.6/ (/i1/ ordered set) or a /d16.2/ (/i2/ ordered set), depending on the current running disparity. the exception is when the data following the /k28.5/ is /d21.5/ (/c1/ ordered set) or /d2.2/ (/c2/) ordered set. if the running disparity before the /k28.5/ is positive, an /i1/ ordered set is generated. if the running disparity is negative, a /i2/ ordered set is generated. the disparity at the end of a /i1/ is the opposite of that at the beginning of the /i1/. the disparity at the end of a /i2/ is the same as the beginning running disparity (right before the idle code). this ensures a negative running disparity at the end of an idle ordered set. a /kx.y/ following a /k28.5/ is not replaced. 1 note that /d14.3/, /d24.0/, and /d15.8/ are replaced by /d5.6/ or /d16.2/ (for /i1/, /i2/ ordered sets). /d21.5/ (part of the /c1/ order set) is not replaced. figure 1?130 shows the automatic idle ordered set generation. /i/ idle ? correcting /i1/, preserving /i2/ /i1/ idle 1 2 /k28.5/d5.6 /i2/ idle 2 2 /k28.5/d16.2 encapsulation ? ? /r/ carrier_extend 1 /k23.7/ /s/ start_of_packet 1 /k27.7/ /t/ end_of_packet 1 /k29.7/ /v/ error_propagation 1 /k30.7/ note to tab l e 1 ?6 3 : (1) two data code groups representing the config_reg value. table 1?63. gige ordered sets (part 2 of 2) code ordered set number of code groups encoding figure 1?130. automatic ordered set generation k28.5 d14.3 k28.5 d24.0 k28.5 d15.8 k28.5 d21.5 tx_datain [ ] clock dx.y dx.y k28.5 d5.6 k28.5 d16.2 k28.5 d16.2 k28.5 tx_dataout ordered set d21.5 /i1/ /i2/ /i2/ /c2/ 1?166 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation reset condition after de-assertion of tx_digitalreset , the gige transmitter automatically transmits three /k28.5/ comma code groups before transmitting user data on the tx_datain port. this could affect the synchronization state machine behavior at the receiver. depending on when you start transmitting the synchronization sequence, there could be an even or odd number of /dx.y/ code groups transmitted between the last of the three automatically sent /k28.5/ code groups and the first /k28.5/ code group of the synchronization sequence. if there is an even number of /dx.y/ code groups received between these two /k28.5/ code groups, the first /k28.5/ code group of the synchronization sequence begins at an odd code group boundary ( rx_even = false). an ieee802.3-compliant gige synchronization state machine treats this as an error condition and goes into the loss of sync state. figure 1?131 shows an example of even numbers of /dx.y/ between the last automatically sent /k28.5/ and the first user-sent /k28.5/. the first user-sent /k28.5/ code group received at an odd code group boundary in cycle n + 3 takes the receiver synchronization state machine in the loss of sync state. the first synchronization ordered set /k28.5/dx.y/ in cycles n + 3 and n + 4 is discounted and three additional ordered sets are required for successful synchronization. wor d a l ign e r the word aligner in gige functional mode is configured in automatic synchronization state machine mode. the quartus ii software automatically configures the synchronization state machine to indicate synchronization when the receiver receives three consecutive synchronization ordered sets. a synchronization ordered set is a /k28.5/ code group followed by an odd number of valid /dx.y/ code groups. the fastest way for the receiver to achieve synchronization is to receive three continuous {/k28.5/, /dx.y/} ordered sets. receiver synchronization is indicated on the rx_syncstatus port of each channel. a high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that the lane has fallen out of synchronization. the receiver loses synchronization when it detects four invalid code groups separated by less than three valid code groups or when it is reset. figure 1?131. reset condition in gige mode clock tx_dataout tx_digitalreset k28.5 k28.5 k28.5 k28.5 xxx dx.y dx.y k28.5 k28.5 k28.5 dx.y dx.y dx.y n n + 1 n + 2 n + 3 n + 4 chapter 1: stratix iv transceiver architecture 1?167 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 table 1?64 lists the synchronization state machine parameters when configured in gige mode. figure 1?132 shows the synchronization state machine implemented in gige mode. table 1?64. synchronization state machine parameters in gige functional mode synchronization state machine parameters setting number of valid {/k28.5/, /dx,y/} ordered sets received to achieve synchronization 3 number of errors received to lose synchronization 4 number of continuous good code groups received to reduce the error count by 1 4 figure 1?132. synchronization state machine in gige mode (note 1) note to figure 1?132 : (1) this figure is from ieee p802.3ae. power_on=true+mr_main_rest=true + (signal_detectchan ge=true + mr_loopback=false +pudi) (signal_detect=ok+mr_loopback=true)* * pudi([/comma/] pudi([/|dv|/] rx_even=false+pudi([/comma/] pudi(![/comma/] *?[/in valid/] pudi([/|dv|/] cggood *good_cgs = 3 cggood *good_cgs = 3 cggood *good_cgs = 3 cggood *good_cgs = 3 cggood cggood pudi(![/|dv|/] pudi(![/|dv|/] [pudi * signal_detect=fail + mr_loopback=false] + pudi(![/comma/]) loss_of_syn c sync_status ? fail rx_even ? ! rx_even sudi comma_detect_1 rx_even ? true sudi syn c_acquired_2 rx_even ? ! rx_even sudi good_cgs ? 0 syn c_acquired_3 syn c_acquired_4 cgbad cgbad cggood cgbad cgbad cggood cgbad cgbad cgbad syn c_acquired_2a syn c_acquired_3a syn c_acquired_4a acquire_sy n c_1 sudi comma_detect_2 sudi 2 cggood *good_cgs = 3 cggood *good_cgs = 3 3 3 2 pudi(![/comma/] *?[/in valid/] rx_even ? true rx_even=false+pudi([/comma/] cgbad cgbad acquire_sy n c_2 sudi rx_even ? ! rx_even pudi(![/|dv|/] comma_detect_3 sudi rx_even ? true pudi([/|dv|/] syn c_acquired_1 sudi sync_status ? ok rx_even ? ! rx_even rx_even ? ! rx_even rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 rx_even ? ! rx_even sudi good_cgs ? 0 rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 rx_even ? ! rx_even sudi good_cgs ? 0 rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 1?168 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation rate match fifo in gige mode, the rate match fifo is capable of compensating for up to 100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. the gige protocol requires the transmitter to send idle ordered sets /i1/ (/k28.5/d5.6/) and /i2/ (/k28.5/d16.2/) during inter-packet gaps adhering to the rules listed in the ieee 802.3 specification. the rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. the rate matcher deletes or inserts both symbols (/k28.5/ and /d16.2/) of the /i2/ ordered sets even if it requires deleting only one symbol to prevent the rate match fifo from overflowing or under-running. it can insert or delete as many /i2/ ordered sets as necessary to perform the rate match operation. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , indicating rate match fifo deletion and insertion events, respectively, are forwarded to the fpga fabric. both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are asserted for two clock cycles for each deleted and inserted /i2/ ordered set, respectively. figure 1?133 shows an example of rate match fifo deletion where three symbols are required to be deleted. because the rate match fifo can only delete /i2/ ordered set, it deletes two /i2/ ordered sets (four symbols deleted). figure 1?134 shows an example of rate match fifo insertion in the case where one symbol is required to be inserted. because the rate match fifo can only delete /i2/ ordered set, it inserts one /i2/ ordered set (two symbols inserted). for more information, refer to ?rate match (clock rate compensation) fifo? on page 1?74 . figure 1?133. rate match deletion in gige mode datain dataout rx_rmfifodatadeleted first /i2/ skip ordered set dx.y k28.5 k28.5 second /i2/ skip ordered set /i2/ skip symbol deleted d16.2 d16.2 k28.5 d16.2 dx.y third /i2/ skip ordered set dx.y k28.5 d16.2 dx.y figure 1?134. rate match insertion in gige mode datain dataout rx_rmfifodatainserted first /i2/ ordered set dx.y k28.5 k28.5 second /i2/ ordered set d16.2 d16.2 dx.y k28.5 d16.2 d16.2 dx.y k28.5 d16.2 k28.5 chapter 1: stratix iv transceiver architecture 1?169 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 sonet/sdh mode sonet/sdh is one of the most common serial-interconnect protocols used in backplanes deployed in communications and telecom applications. sonet/sdh defines various optical carrier (oc) sub-pr otocols for carrying signals of different capacities through a synchronous optical hierarchy. sonet/sdh frame structure base oc-1 frames are byte-interleaved to form sonet/sdh frames. for example, 12 oc-1 frames are byte-interleaved to form one oc-12 frame; 48 oc-1 frames are byte-interleaved to form one oc-48 frame, and so on. sonet/sdh frame sizes are constant, with a frame transfer rate of 125 s. figure 1?135 shows the sonet/sdh frame structure. transport overhead bytes a1 and a2 are used for restoring frame boundary from the serial data stream. frame sizes are fixed, so the a1 and a2 bytes appear within the serial data stream every 125 s. in an oc-12 system, 12 a1 bytes are followed by 12 a2 bytes. similarly, in an oc-48 system, 48 a1 bytes are followed by 48 a2 bytes. in sonet/sdh systems, byte values of a1 and a2 are fixed as follows: a1 = 11110110 or 8'hf6 a2 = 00101000 or 8'h28 you can employ stratix iv gx and gt transceivers as physical layer devices in a sonet/sdh system. these transceivers provide support for sonet/sdh protocol-specific functions and electrical features; for example, alignment to a1a2 or a1a1a2a2 pattern. figure 1?135. sonet/sdh mode nxa1 nxa2 nxj0/z0 9 rows nx3 bytes transport overhead nx3 bytes payload 1?170 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation stratix iv transceivers are designed to support the following three sonet/sdh sub-protocols: oc-12 at 622 mbps with 8-bit channel width (not supported in stratix iv gt devices) oc-48 at 2488.32 mbps with 16-bit channel width oc-96 at 4976 mbps with 32-bit channel width chapter 1: stratix iv transceiver architecture 1?171 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?136 shows sonet/sdh mode configurations supported in stratix iv gx and gt devices. figure 1?136. sonet/sdh mode configurations in stratix iv gx and gt devices note to figure 1?36 : (1) this is not supported in stratix iv gt devices. disabled disabled rate match fifo byte serdes byte ordering stratix iv gx and gt configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit functional mode disabled disabled disabled disabled disabled enabled disabled enabled pma-pcs interface width data rate (gbps) channel bonding low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder fpga fabric-transceiver interface width fpga fabric-transceiver interface frequency (mhz) 8-bit 16-bit 77.75 155.5 manual alignment (16-bit a1a2, 32-bit a1a1a2a2) manual alignment (16-bit a1a2, 32-bit a1a1a2a2) x1 x1 0.622 (oc-12) (1) 2.488 (oc-48) sonet/ sdh disabled disabled disabled enabled disabled 32-bit 155.5 manual alignment (32-bit a1a1a2a2) x1 4.976 (oc-96) deterministic latency 10-bit 20-bit interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 5 - 6 11 - 13 4 - 5.5 7 - 9 4 - 5.5 6.5 - 8.5 1?172 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation sonet/sdh oc-12 datapath figure 1?137 shows the transceiver datapath when configured in sonet/sdh oc-12 mode. sonet/sdh oc-48 datapath figure 1?138 shows the transceiver datapath when configured in sonet/sdh oc-48 mode. figure 1?137. sonet/sdh oc-12 datapath tx phase compensation fifo serializer transmitter channel pcs transmitter channel pma wrclk rdclk low-speed parallel clock high-speed serial clock tx_coreclk rx phase compensation fifo word aligner de- serializer cdr tx_clkout parallel recovered clock rx_coreclk receiver channel pcs receiver channel pma fpga fabric-transmitter interface clock fpga fabric local clock divider fpga fabric-receiver interface clock rx_clkout figure 1?138. sonet/sdh oc-48 datapath tx phase compensation fifo byte serializer serializer transmitter channel pcs transmitter channel pma /2 wrclk rdclk low-speed parallel clock high-speed serial clock tx_coreclk rx phase compensation fifo byte de- serializer word aligner de- serializer cdr wrclk rdclk /2 tx_clkout parallel recovered clock rx_coreclk byte ordering receiver channel pcs receiver channel pma fpga fabric-transmitter interface clock fpga fabric fpga fabric-receiver interface clock rx_clkout local clock divider chapter 1: stratix iv transceiver architecture 1?173 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 sonet/sdh oc-96 datapath figure 1?139 shows the transceiver datapath when configured in sonet/sdh oc-96 mode. sonet/sdh transmission bit order unlike ethernet, where the lsb of the parallel data byte is transferred first, sonet/sdh requires the msb to be transferred first and the lsb to be transferred last. to facilitate the msb-to-lsb transfer, you must enable the following options in the altgx megawizard plug-in manager: flip transmitter input data bits flip receiver output data bits depending on whether data bytes are transferred msb-to-lsb or lsb-to-msb, you must select the appropriate word aligner settings in the altgx megawizard plug-in manager. table 1?65 on page 1?174 lists the correct word aligner settings for each bit transmission order. word alignment the word aligner in sonet/sdh oc-12, oc-48, and oc-96 modes is configured in manual alignment mode, as described in ?word aligner in single-width mode with 8-bit pma-pcs interface modes? on page 1?57 . in oc-12 and oc-48 configurations, you can configure the word aligner to either align to a 16-bit a1a2 pattern or a 32-bit a1a1a2a2 pattern. this is controlled by the rx_a1a2size input port to the transceiver. a low level on the rx_a1a2size port configures the word aligner to align to a 16-bit a1a2 pattern; a high level on the rx_a1a2size port configures the word aligner to align to a 32-bit a1a1a2a2 pattern. figure 1?139. sonet/sdh oc-96 datapath tx phase compensation fifo byte serializer serializer transmitter channel pcs transmitter channel pma /2 wrclk rdclk low-speed parallel clock high-speed serial clock tx_coreclk rx phase compensation fifo byte de- serializer word aligner de- serializer cdr wrclk rdclk /2 tx_clkout parallel recovered clock rx_coreclk receiver channel pcs receiver channel pma fpga fabric-transmitter interface clock fpga fabric fpga fabric-receiver interface clock rx_clkout local clock divider 1?174 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation in oc-96 configuration, the word aligner is only allowed to align to a a1a1a2a2 pattern, so the input port rx_ala2size is unavailable. barring this difference, the oc-96 word alignment operation is similar to that of the oc-12 and oc-48 configurations. you can configure the word aligner to flip the alignment pattern bits programmed in the megawizard plug-in manager and compare them with the incoming data for alignment. this feature offers flexibility to the sonet backplane system for either a msb-to-lsb or lsb-to-msb data transfer. table 1?65 lists word alignment patterns that you must program in the altgx megawizard plug-in manager based on the bit-transmission order and the word aligner bit-flip option. the behavior of the sonet/sdh word aligner control and status signals, along with an operational timing diagram, are explained in ?word aligner in single-width mode with 8-bit pma-pcs interface modes? on page 1?57 . oc-48 and oc-96 byte serializer and deserializer the oc-48 and oc-96 transceiver datapath includes the byte serializer and deserializer to allow the pld interface to run at a lower speed. the oc-12 configuration does not use the byte serializer and deserializer blocks. the byte serializer and deserializer blocks are explained in ?byte serializer? on page 1?16 and ?byte deserializer? on page 1?89 , respectively. the oc-48 byte serializer converts 16-bit data words from the fpga fabric and translates the 16-bit data words into two 8-bit data bytes at twice the rate. the oc-48 byte deserializer takes in two consecutive 8-bit data bytes and translates them into a 16-bit data word to the fpga fabric at half the rate. the oc-96 byte serializer converts 32-bit data words from the fpga fabric and translates them into two 16-bit data words at twice the rate. the oc-96 byte deserializer takes in two consecutive 16-bit data words and translates them into a 32-bit data word to the fpga fabric at half the rate. oc-48 byte ordering because of byte deserialization, the msbyte of a word might appear at the rx_dataout port along with the lsbyte of the next word. in an oc-48 configuration, the byte ordering block is built into the datapath and can be leveraged to perform byte ordering. byte ordering in an oc-48 configuration is automatic, as explained in ?word-alignment-based byte ordering? on page 1?94 . table 1?65. word aligner settings serial bit transmission order word alignment bit flip word alignment pattern msb-to-lsb on 1111011000101000 (16'hf628) msb-to-lsb off 0001010001101111 (16'h146f) lsb-to-msb off 0010100011110110 (16'h28f6) chapter 1: stratix iv transceiver architecture 1?175 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 in automatic mode, the byte ordering block is triggered by the rising edge of the rx_syncstatus signal. as soon as the byte ordering block sees the rising edge of the rx_syncstatus signal, it compares the lsbyte coming out of the byte deserializer with the a2 byte of the a1a2 alignment pattern. if the lsbyte coming out of the byte deserializer does not match the a2 byte set in the altgx megawizard plug-in manager, the byte ordering block inserts a pad character, as seen in figure 1?140 . insertion of this pad character enables the byte ordering block to restore the correct byte order. 1 the pad character is defaulted to the a1 byte of the a1a2 alignment pattern. sdi mode the society of motion picture and television engineers (smpte) defines various sdi standards for transmission of uncompressed video. the following three smpte standards are popular in video broadcasting applications: smpte 259m standard?more popularly known as the standard-definition (sd) sdi, is defined to carry video data at 270 mbps smpte 292m standard?more popularly known as the high-definition (hd) sdi, is defined to carry video data at either 1485 mbps or 1483.5 mbps smpte 424m standard?more popularly known as the third-generation (3g) sdi, is defined to carry video data at either 2970 mbps or 2967 mbps you can configure stratix iv gx and gt transceivers in hd-sdi or 3g-sdi configuration using the altgx megawizard plug-in manager. figure 1?140. oc-48 byte ordering in automatic mode x x pad from byte deserializer rx_dataout (msb) rx_dataout (lsb) rx_clkout rx_syncstatus a1 a1 a1 a1 a2 a2 a2 a2 d0 d2 d1 byte ordering block rx_syncstatus rx_byteorderalignstatus to pld core a1 a1 a1 a2 a1 a2 d1 d2 d0 d3 1?176 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation table 1?66 lists the altgx configurations supported by stratix iv transceivers in sdi mode. table 1?66. altgx configurations in sdi mode configuration data rate (mbps) refclk frequencies (mhz) fpga fabric-transceiver interface width hd (1) 1485 74.25, 148.5 10 bit and 20 bit 1483.5 74.175, 148.35 10 bit and 20 bit 3g (2) 2970 148.5, 297 only 20-bit interface allowed in 3g 2967 148.35, 296.7 only 20-bit interface allowed in 3g notes to ta bl e 1? 66 : (1) not supported by stratix iv gt devices. (2) stratix iv gt devices only support the 3g configuration. chapter 1: stratix iv transceiver architecture 1?177 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?141 shows sdi mode configurations supported in stratix iv gx and gt devices. figure 1?141. sdi mode note to figure 1?41 : (1) not supported in stratix iv gt devices. sdi disabled disabled rate match fifo byte serdes byte ordering stratix iv gx and gt configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit functional mode disabled disabled disabled disabled disabled enabled channel bonding disabled disabled enabled disabled pma-pcs interface width data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder fpga fabric-transceiver interface width fpga fabric-transceiver interface frequency (mhz) 148.5/ 148.35 74.25/ 74.175 10-bit 20-bit bit-slip x1 hd-sdi (1.485/1.4835) (1) x1 3g-sdi (2.97/2.967) bit-slip 20-bit 148.5/ 148.35 deterministic latency 10-bit 20-bit 5 - 6 9 - 11 interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 4 - 5.5 6 - 8 4 - 5.5 6 - 8 1?178 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation sdi mode datapath figure 1?142 shows the transceiver datapath when configured in sdi mode. transmitter datapath the transmitter datapath, in hd-sdi configuration with 10-bit wide fpga fabric-transceiver interface, consists of the transmitter phase compensation fifo and the 10:1 serializer. the transmitter datapath, in hd-sdi and 3g-sdi configurations with 20-bit wide fpga fabric-transceiver interface, also includes the byte serializer. 1 in sdi mode, the transmitter is purely a parallel-to-serial converter. sdi transmitter functions, such as scrambling and cyclic redundancy check (crc) code generation, must be implemented in the fpga logic array. receiver datapath in the 10-bit channel width sdi configuration, the receiver datapath is comprised of the clock recovery unit (cru), 1:10 deserializer, word aligner in bit-slip mode, and receiver phase compensation fifo. in the 20-bit channel width sdi configuration, the receiver datapath also includes the byte deserializer. 1 sdi receiver functions, such as de-scrambling, framing, and crc checker, must be implemented in the fpga logic array. receiver word alignment and framing in sdi systems, the word aligner in the receiver datapath is not useful because word alignment and framing happens after de-scrambling. altera recommends driving the altgx megafunction rx_bitslip signal low to avoid having the word aligner insert bits in the received data stream. figure 1?142. sdi mode datapath tx phase compensation fifo byte serializer serializer transmitter channel pcs transmitter channel pma low-speed parallel clock high-speed serial clock tx_coreclk rx phase compensation fifo byte de- serializer word aligner de- serializer cdr tx_clkout wrclk rdclk wrclk rdclk parallel recovered clock rx_coreclk receiver channel pcs receiver channel pma fpga fabric-transmitter interface clock fpga fabric fpga fabric-receiver interface clock rx_clkout local clock divider /2 /2 chapter 1: stratix iv transceiver architecture 1?179 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 (oif) cei phy interf ace mode stratix iv gx and gt transceivers support a data rate between 4.976 gbps and 6.375 gbps in (oif) cei phy interface mode. figure 1?143 shows (oif) cei phy interface mode configurations supported in stratix iv gx and gt devices. figure 1?143. (oif) cei phy interface mode for stratix iv gx and gt devices rate match fifo byte serdes byte ordering stratix iv gx and gt configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit functional mode disabled disabled disabled enabled channel bonding disabled disabled pma-pcs interface width data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder fpga fabric-transceiver interface width fpga fabric-transceiver interface frequency (mhz) 97.65625- 199.21875 32-bit x1, x4 (transmitter pma-only bonding) 3.125-6.375 (oif) cei phy interface mode deterministic latency 10-bit 20-bit interface frequency tx pcs latency (fpga fabric-transceiver interface clock cycles) rx pcs latency (fpga fabric-transceiver interface clock cycles) 4 -5.5 6.5 - 8.5 1?180 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation (oif) cei phy interface mode datapath figure 1?144 shows the altgx megafunction transceiver datapath when configured in (oif) cei phy interface mode. figure 1?145 shows transceiver clocking in (oif) cei phy interface mode. serial rapidio mode the rapidio trade association defines a high-performance, packet-switched interconnect standard to pass data and control information between microprocessors, digital signal, communications, and network processors, system memories, and peripheral devices. serial rapidio physical layer specification defines three line rates: 1.25 gbps 2.5 gbps 3.125 gbps figure 1?144. (oif) cei phy interface mode datapath tx phase compensation fifo byte serializer transmitter channel pcs transmitter channel pma wrclk wrclk rdclk rdclk low-speed parallel clock high-speed serial cloc k tx_coreclk rx phase compensation fifo cdr /2 /2 tx_clkout parallel recovered clock rx_coreclk receiver channel pcs receiver channel pma fpga fabric-transmitter interface clock fpga fabric fpga fabric-receiver interface clock rx_clkout local clock divider serializer de- serializer byte de- serializer figure 1?145. transceiver clocking in (oif) cei phy interface mode transceiver block clocking with the use central clock divider to improve transmitter jitter option disabled cmu pll ch 3 local clock divider block ch 2 local clock divider block ch 1 local clock divider block ch 0 local clock divider block channel 3 channel 2 channel 1 channel 0 chapter 1: stratix iv transceiver architecture 1?181 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 it also defines two link widths?single-lane (1) and bonded four-lane (4) at each line rate. stratix iv gx and gt transceivers support only single-lane (1) configuration at all three line rates. four 1 channels configured in serial rapidio mode can be instantiated to achieve a 4 serial rapidio link. the four transmitter channels in this 4 serial rapidio link are not bonded. the four receiver channels in this 4 serial rapidio link do not have lane alignment or deskew capability. figure 1?146 shows the altgx transceiver datapath when configured in serial rapidio mode. stratix iv gx and gt transceivers, when configured in serial rapidio functional mode, provide the following pcs and pma functions: 8b/10b encoding/decoding word alignment lane synchronization state machine clock recovery from the encoded data serialization/deserialization 1 stratix iv gx and gt transceivers do not have built-in support for other pcs functions; for example, pseudo-random idle sequence generation and lane alignment in 4 mode. depending on your system requirements, you must implement these functions in the logic array or external circuits. figure 1?146. serial rapidio mode datapath tx phase compensation fifo 8b/10b encoder 8b/10b decoder serializer de- serializer transmitter channel pcs transmitter channel pma wrclk rdclk low-speed parallel clock high-sp eed serial cloc k tx_coreclk[0] rx phase compensation fifo rate match fifo word aligner cdr tx_clkout[0] parallel recovered clock low-speed parallel clock rx_coreclk[0] receiver channel pcs receiver channel pma fpga fabric-transceiver interface clock fpga fabric local clock divider byte serializer /2 /2 byte de- serializer /2 8b/10b decoder de- serializer 1?182 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation synchronization state machine in serial rapidio mode, the altgx megawizard plug-in manager defaults the word alignment pattern to k28.5. the word aligner has a synchronization state machine that handles the receiver lane synchronization. the altgx megawizard plug-in manager automatically defaults the synchronization state machine to indicate synchronization when the receiver receives 127 k28.5 (10'b010 1111 100 or 10'b1010000011) synchronization code groups without receiving an intermediate invalid code group. after synchronization, the state machine indicates loss of synchronization when it detects three invalid code groups separated by less than 255 valid code groups or when it is reset. receiver synchronization is indicated on the rx_syncstatus port of each channel. a high on the rx_syncstatus port indicates that the lane is synchronized and a low indicates that it has fallen out of synchronization. table 1?67 lists the altgx megafunction synchronization state machine parameters when configured in serial rapidio mode. table 1?67. synchronization state machine parameters in serial rapidio mode parameters number number of valid k28.5 code groups received to achieve synchronization. 127 number of errors received to lose synchronization. 3 number of continuous good code groups received to reduce the error count by one. 255 chapter 1: stratix iv transceiver architecture 1?183 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?147 shows a conceptual view of the synchronization state machine implemented in serial rapidio functional mode. rate match fifo in serial rapidio mode in serial rapidio mode, the rate match fifo is capable of compensating for up to 100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. 1 to enable the rate match fifo in serial rapidio mode, the transceiver channel must have both the transmitter and receiver channel instantiated. you must select the receiver and transmitter option in the what is the operation mode? field in the altgx megawizard plug-in manager. the 8b/10b encoder/decoder is always enabled in serial rapidio mode. 1 rate matcher is an optional block available for selection in srio functional mode. however, this block is not fully compliant to the srio specification. figure 1?147. synchronization state machine in serial rapidio mode loss of sync data = comma comma detect if data == comma kcntr++ else kcntr=kcntr synchronized data = valid; kcntr < 127 kcntr = 127 synchronized error detect if data == !valid ecntr++ gcntr=0 else if gcntr==255 ecntr-- gcntr=0 else gcntr++ data = !valid data=valid ecntr = 0 ecntr = 3 data = !valid 1?184 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation depending on your implementation, you can select two 20-bit rate match patterns in the altgx megawizard plug-in manager under the what is the rate match pattern1 and what is the rate match pattern2 fields. each of the two programmed 20-bit rate match patterns consists of a 10-bit skip pattern and a 10-bit control pattern. for serial rapidio mode in the altgx megawizard plug-in manager, the control pattern1 defaults to k28.5 with positive disparity and the skip pattern1 defaults to k29.7 with positive disparity. the control pattern2 defaults to k28.5 with negative disparity and the skip pattern2 defaults to k29.7 with negative disparity. the rate match fifo operation begins after the word aligner synchronization status rx_syncstatus goes high. when the rate matcher receives either of the two 10-bit control patterns followed by the respective 10-bit skip pattern, it inserts or deletes the 10-bit skip pattern as necessary to avoid the rate match fifo from overflowing or under-running. in serial rapidio mode, the rate match fifo can delete/insert a maximum of one skip pattern from a cluster. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , indicate that rate match fifo deletion and insertion events, respectively, are forwarded to the fpga fabric. figure 1?148 shows an example of rate match fifo deletion in the case where one skip pattern is required to be deleted. in this example, the first skip cluster has a /k28.5/ control pattern followed by two /k29.7/ skip patterns. the second skip cluster has a /k28.5/ control pattern followed by four /k29.7/ skip patterns. the rate match fifo deletes only one /k29.7/ skip pattern from the first skip cluster. one /k29.7/ skip pattern is deleted from the second cluster. figure 1?148. rate match fifo deletion with one skip pattern deleted k28.5 k29.7 k28.5 k29.7 k29.7 datain datao u t k29.7 first skip cl u ster second skip cl u ster k28.5 k29.7 k29.7 k29.7 k29.7 k29.7 k28.5 k29.7 rx_ rmfifodatadeleted one skip pattern deleted dx.y dx.y k29.7 chapter 1: stratix iv transceiver architecture 1?185 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?149 shows an example of rate match fifo insertion in the case where one skip pattern is required to be inserted. in this example, the first skip cluster has a /k28.5/ control pattern followed by three /k29.7/ skip patterns. the second skip cluster has a /k28.5/ control pattern followed by two /k29.7/ skip patterns. the rate match fifo inserts only one /k29.7/ skip pattern into the first skip cluster. one /k29.7/ skip pattern is inserted into the second cluster. two flags, rx_rmfifofull and rx_rmfifoempty , are forwarded to the fpga fabric to indicate rate match fifo full and empty conditions. for more information about the behavior of these two signals, refer to ?rate match fifo in basic single- width mode? on page 1?81 . basic (pma direct) functional mode in basic (pma direct) functional mode, the stratix iv gx and gt transceiver datapath contains only pma blocks. parallel data is transferred directly between the fpga fabric and the serializer/deserializer inside the transmitter/receiver pma. because all pcs blocks are bypassed in basic (pma direct) mode, you must implement the required pcs logic in the fpga fabric. you can configure four regular transceiver channels inside each transceiver block in basic (pma direct) functional mode. you can configure two cmu channels inside each transceiver block only in basic (pma direct) functional mode, as they do not support pcs circuitry. in pma direct mode, you must create your own logic to support pcs functionality. there are specific reset sequences to be followed in this mode. use dynamic reconfiguration to dynamically reconfigure the various pma controls to tailor the transceivers in pma direct drive mode for a particular application. f for more information, refer to the stratix iv dynamic reconfiguration chapter. for more information about the reset sequence to follow in pma-direct mode, refer to the stratix iv reset control and power down chapter. the term ?pma-direct? is used to describe various configurations in this mode. 1 in basic (pma direct) mode, all the pcs blocks are bypassed; therefore, any pcs-type features (for example, phase compensation fifos, byte serializer, 8b/10b encoder/decoder, word aligner, deskew fifo, rate match fifo, byte deserializer, and byte ordering), must be implemented in the fpga fabric. in basic (pma direct) mode, you must create your own logic to support pcs functionality. figure 1?149. rate match fifo deletion with one skip pattern inserted k28.5 k29.7 k28.5 k29.7 k29.7 datain datao u t k29.7 first skip cl u ster second skip cl u ste r k29.7 k28.5 k29.7 k29.7 dx.y k29.7 k29.7 k29.7 one skip pattern inserted k28.5 k29.7 k29.7 dx.y 1?186 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?150 shows the stratix iv gx and gt transceiver configured in basic (pma direct) functional mode. the grayed out blocks indicate areas that are not active in this mode. 1 the grayed out blocks shown in figure 1?150 are not available in the cmu channels. therefore, the cmu channels can be configured to operate as transceiver channels in pma direct mode only. in basic (pma direct) mode, you can configure the transceiver channel in two main configurations: basic (pma direct) 1 configuration basic (pma direct) n configuration you can configure the transceiver in basic (pma direct) 1/ n mode by setting the appropriate sub-protocol in the which sub protocol will you be using ? field. you can select single-width or double-width by selecting single/double in the what is the deserializer block width? field in the altgx megawizard plug-in manager. in single-width mode, the pma-pld interface is 8 bit/10 bit wide; whereas in double-width mode, the pma-pld interface is 16 bit/20 bit wide. figure 1?150. stratix iv gx and gt transceiver configured in basic (pma direct) mode note to figure 1?150 : (1) the grayed out blocks shown in figure 1?150 are not available in the cmu channels. therefore, the cmu channels can be configured to operate as transceiver channels in pma direct mode only. rx phase compensation fifo tx phase compensation fifo byte ordering byte deserializer byte serializer 8b/10b decoder 8b/10b encoder rate match fifo receiver channel pcs receiver channel pma deske w fifo w ord aligner deserializer cdr t ransmitter channel pcs t ransmitter channel pma serializer wrclk wrclk rdclk rdclk pci express hard ip fpga fabric pipe interface chapter 1: stratix iv transceiver architecture 1?187 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 table 1?68 lists the stratix iv gx and gt pld-pma interface widths and data rates supported in basic (pma direct) 1/n single-width and double-width modes. basic (pma direct) 1 configuration you can configure a transceiver channel in this mode by setting the which protocol will you be using? field to basic (pma direct) and the which sub protocol will you be using? field to none . in this configuration, the quartus ii software requires one of the two cmu plls within the same transceiver block to provide high-speed clocks to the transmitter side of the channel. if the cmu0 or cmu1 channel is configured in basic (pma direct) 1 configuration, use their local clock dividers to provide clock to their respective transmitter channels. f for information about clocking restrictions in basic (pma direct) 1 mode, refer to the ?non-bonded basic (pma direct) mode channel configurations? section in the stratix iv transceiver clocking chapter. f for information about routing the clocks to transceiver channels in basic (pma direct) 1 mode, refer to the stratix iv transceiver clocking chapter. basic (pma direct) n configuration you can configure a transceiver channel in this mode by setting the which protocol will you be using field to basic (pma direct) and the which sub protocol will you be using field to n . in this mode, all the transmitter channels can receive their high-speed clock from the cmu0 pll from the transceiver blocks or the atx pll present on the same side of the device. these clocks are provided through the n_top or n_bottom clock line. in this mode, if you use a cmu pll to generate the transceiver channel datapath interface clocks, only the cmu0 central clock divider of the transceiver block containing the cmu pll is used. f for information about clocking restrictions in basic (pma direct) n mode, refer to the ?non-bonded basic (pma direct) mode channel configurations? section in the stratix iv transceiver clocking chapter. table 1?68. fpga fabric-pma interface widths and data rates supported in basic (pma direct) 1/n single-width and double-width modes for stratix iv gx and gt devices basic (pma direct) functional mode fpga fabric-pma interface width supported data rate range stratix iv gx stratix iv gt c2 speed grade c3/i3 speed grade c4 speed grade i1, i2, i3 1/n single-width mode 8 bit 0.6gbps to 2.6gbps 0.6gbps to 2.6gbps 0.6gbps to 2.6gbps 2.488 gbps to 2.6 gbps 10 bit 0.6gbps to 3.25gbps 0.6gbps to 3.25gbps 0.6gbps to 3.25gbps 2.488 gbps to 3.25 gbps 1/n double-width mode 16 bit 1.0gbps to 5.2gbps 1.0gbps to 5.2gbps 1.0gbps to 5.0gbps 2.488 gbps to 5.2 gbps 20 bit 1.0gbps to 6.5gbps 1.0gbps to 6.5gbps 1.0gbps to 5.0gbps 2.488 gbps to 6.5 gbps 1?188 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation f for more information about combining multiple transceiver channels, refer to the configuring multiple protocols and data rates in a transceiver block chapter. each receiver in a receiver channel has a dedicated cdr that provides a high-speed clock. f for more information about timing closure in basic (pma direct) mode, refer to an 580: achieving timing closure in basic (pma direct) functional mode . loopback modes stratix iv gx and gt devices provide various loopback options that allow you to verify how different functional blocks work in the transceiver channel. the available loopback options are: ?serial loopback? on page 1?188 ?available in all functional modes except pci express (pipe) mode ?parallel loopback? on page 1?189 ?available in either single-width or double-width modes. ?reverse serial loopback? on page 1?191 ?available in basic mode only ?reverse serial pre-cdr loopback? on page 1?191 ?available in basic mode only ?pci express (pipe) reverse parallel loopback? on page 1?192 ?supported in pci express (pipe) protocol only (this loopback mode does not support stratix iv gt devices) serial loopback the serial loopback option is available for all functional modes except pci express (pipe) mode. figure 1?151 shows the datapath for serial loopback. the data from the fpga fabric passes through the transmitter channel and gets looped back to the receiver channel, bypassing the receiver buffer. the received data is available to the fpga logic for verification. using this option, you can check the working for all enabled pcs and pma functional blocks in the transmitter and receiver channel. when you enable the serial loopback option, the altgx megawizard plug-in manager provides the rx_seriallpbken port to dynamically enable serial loopback on a channel-by-channel basis. set the rx_seriallpbken signal to logic high to enable serial loopback. when serial loopback is enabled, the transmitter channel sends the data to both the tx_dataout output port and to the receiver channel. the differential output voltage on the tx_dataout ports is based on the selected v od settings. the looped back data is received by the receiver cdr and is retimed through different clock domains. you must provide an alignment pattern for the word aligner to enable the receiver channel to retrieve the byte boundary. chapter 1: stratix iv transceiver architecture 1?189 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 suppose the device is not in serial loopback mode and is receiving data from a remote device. at this point, the receiver cdr?s recovered clock is locked to the data from that source. if the device is placed in serial loopback mode, the data source to the receiver changes from the remote device to local transmitter channel. this prompts the receiver cdr to start tracking the phase of the new data source. during this time, the receiver cdr?s recovered clock may be unstable. as the receiver pcs is running off of this recovered clock, you must place the receiver pcs under reset by asserting the rx_digitalreset signal during this time period. 1 when moving into or out of serial loopback, you must assert rx_digitalreset for a minimum of two parallel clock cycles. parallel loopback you can configure a transceiver channel in this mode by setting the which protocol will you be using ? field to basic and the which sub protocol will you be using? field to bist . you can only configure a receiver and transmitter transceiver channel in this functional mode. you can configure a transceiver channel in this mode in either a single-width or double-width configuration. the bist pattern generator and pattern verifier are located near the fpga fabric in the pcs block of the transceiver channel. this placement allows for testing the complete transmitter pcs and receiver pcs datapaths for bit errors. this mode is primarily used for transceiver channel debugging, if needed. figure 1?151. serial loopback datapath recei v er channel pcs transmitter channel pcs transmitter channel pma recei v er channel pma fpga fa b ric tx phase compen- sation fifo byte serializer 8b/10b encoder bist prbs, high-fre q, lo w -freg pattern generator serial loop b ack can be dynamically enab led w ord aligner bist prbs v erifier deske w fifo rate match fifo 8b/10b decoder byte de- serializer byte ordering rx phase compen- sation fifo serializer de- serializer receiv er cdr 1?190 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation the parallel loopback mode is available only with a built-in 16-bit incremental pattern generator and verifier. the channel width is fixed to 16 bits in this mode. also in this mode, the incremental pattern 00-ff is looped back to the receiver channel at the pcs functional block boundary before the pma and is sent to the tx_dataout port. the received data is verified by the verifier. this loopback allows you to verify the complete pcs block. the differential output voltage of the transmitted serial data on the tx_dataout port is based on the selected v od settings. the datapath for parallel loopback is shown in figure 1?152 . the incremental data pattern is not available to the fpga logic for verification. table 1?69 lists the enabled pcs functional blocks for single-width and double-width mode. the last column in table 1?69 lists the supported channel width setting for parallel loopback. the status signals rx_bistdone and rx_bisterr indicate the status of the verifier. the rx_bistdone port is asserted and stays high when the verifier either receives one full cycle of incremental pattern or it detects an error in the receiver data. the rx_bisterr signal is asserted and stays high when the verifier detects an error. you can reset the incremental pattern generator and verifier by asserting the tx_digitalreset and rx_digitalreset signals, respectively. figure 1?152. enabled pcs functional blocks in parallel loopback recei v er channel pcs transmitter channel pcs transmitter channel pma recei v er channel pma fpga fa b ric bist incremental pattern generator tx phase compen- sation fifo byte serializer 8b/10b encoder parallel loopb ack w ord aligner 8b/10b decoder byte de- serializer rx compen- sation fifo bist incremental pattern v erifier de- serializer receiv er cdr serializer table 1?69. enabled pcs functional blocks for parallel loopback configuration 8b/10b encoder byte serializer data rate range supported channel width setting in the altgx megawizard plug-in manager for parallel loopback single-width mode enabled enabled 600 mbps to 3.125 gbps 16 double-width mode enabled disabled 1 gbps to 5 gbps 16 chapter 1: stratix iv transceiver architecture 1?191 transceiver block architecture ? march 2010 altera corporation stratix iv device handbook volume 2 reverse serial loopback reverse serial loopback is available as a subprotocol under basic functional mode. in reverse serial loopback mode, the data is received through the rx_datain port, retimed through the receiver cdr and sent out to the tx_dataout port. the received data is also available to the fpga logic. figure 1?153 shows the transceiver channel datapath for reverse serial loopback mode. the active block of the transmitter channel is only the transmitter buffer. you can change the output differential voltage and the pre-emphasis first post tap values on the transmitter buffer through the altgx megawizard plug-in manager or through the dynamic reconfiguration controller. reverse serial loopback is often implemented when using a bit error rate tester (bert) on the upstream transmitter. reverse serial pre-cdr loopback the reverse serial pre-cdr loopback is available as a subprotocol under basic functional mode. in reverse serial pre-cdr loopback, the data received through the rx_datain port is looped back to the tx_dataout port before the receiver cdr. the received data is also available to the fpga logic. figure 1?154 shows the transceiver channel datapath for reverse serial pre-cdr loopback mode. the active block of the transmitter channel is only the transmitter buffer. you can change the output differential voltage on the transmitter buffer through the altgx megawizard plug-in manager. the pre-emphasis settings for the transmitter buffer cannot be changed in this configuration. figure 1?153. reverse serial loopback datapath (grayed-out blocks are not active in this mode) receiver channel pcs transmitter channel pcs transmitter channel pma receiver channe l pma fpga fabric tx phase compen- sation fifo byte serialzier 8b/10b encoder serializer reverse serial loopback word aligner 8b/10b decoder byte de- serializer byte ordering rx phase compen- sation fifo receiver cdr de- serializer 1?192 chapter 1: stratix iv transceiver architecture transceiver block architecture stratix iv device handbook volume 2 ? march 2010 altera corporation pci express (pipe) reverse parallel loopback pci express (pipe) reverse parallel loopback is only available in pci express (pipe) functional mode for gen1 and gen2 data rates. as shown in figure 1?155 , the received serial data passes through the receiver cdr, deserializer, word aligner, and rate matching fifo buffer. it is then looped back to the transmitter serializer and transmitted out through the tx_dataout port. the received data is also available to the fpga fabric through the rx_dataout port. this loopback mode is compliant with the pci express (pipe) specification 2.0. to enable this loopback mode, assert the tx_detectrxloopback port. 1 this is the only loopback option supported in pci express (pipe) functional mode. figure 1?154. reverse serial pre-cdr loopback datapath receiver channel pcs transmitter channel pcs transmitter channel pma receiver channel pma fpga fabric serializer reverse serial pre-cdr loopback receiver cdr de- serializer word aligner 8b/10b decoder byte de- serializer byte ordering rx phase compen- sation fifo chapter 1: stratix iv transceiver architecture 1?193 auxiliary transmit (atx) pll block ? march 2010 altera corporation stratix iv device handbook volume 2 in figure 1?155 , the grayed areas show the inactive paths when the pci express (pipe) reverse parallel loopback mode is enabled. auxiliary transmit (atx) pll block stratix iv gx and gt transceivers contain the atx pll block that you can use to generate high-speed clocks for the transmitter channels on the same side of the device. each: stratix iv gx device has 6g atx pll stratix iv gt device has 6g atx pll and 10g atx plls f for data rates supported by these atx plls, refer to the stratix iv device datasheet section. 6g atx pll block stratix iv gx can have either two (one on each side of the device) or four (two on each side of the device) 6g atx plls, depending on the specific devices. f for data rates supported by 6g atx plls, refer to the stratix iv device datasheet section. figure 1?155. pci express (pipe) reverse parallel loopback mode datapath (grayed-out blocks are not active in this mode) rx phase compensation fifo tx phase compensation fifo byte ordering byte deserializer byte serializer 8b/10b decoder 8b10b encoder rate match fifo receiver channel pcs receiver channel pma deskew fifo word aligner deserializer cdr transmitter channel pcs transmitter channel pma serializer wrclk wrclk rdclk rdclk reverse parallel loopback path pci express hard ip fpga fabric pipe interface 1?194 chapter 1: stratix iv transceiver architecture auxiliary transmit (atx) pll block stratix iv device handbook volume 2 ? march 2010 altera corporation 10g atx pll block each stratix iv gt device has two 10g atx pll blocks, one located on each side of the device. the 10g atx plls provide low-jitter transceiver clocks to implement 40g/100g ethernet and sfi-s links specified by ieee802.3ba and oif specifications. in ep4s40g2f40 and ep4s40g5h40 devices, you can use each 10g atx pll to generate transceiver clocks for up to six channels at data rates of up to 11.3 gbps each. in ep4s100g2f40, ep4s100g5h40, and ep4s100g5f45 devices, you can use each 10g atx pll to generate transceiver clocks for up to 12 channels at data rates of up to 11.3 gbps each. figure 1?159 and figure 1?160 show transceiver channels that support data rates up to 11.3 gbps in each stratix iv gt device. the 10g atx pll block consists of: 10g atx pll?synthesizes the input reference clock to generate the high-speed serial transceiver clock at frequency of half the configured data rate atx clock divider block?divides the high-speed serial clock from the 10g atx pll to generate the low-speed parallel transceiver clock the 10g atx pll architecture is functionally similar to the 6g atx pll architecture, except that it is optimized for the 10 gbps data rate range. figure 1?156 shows the location of the atx pll blocks in two transceiver block device families. figure 1?156. location of atx pll blocks in a four-transceiver block stratix iv gx device (two on each side) gxbl1 gxbr1 atx pll l0 (6g) atx pll r0 (6g) gxbl0 gxbr0 chapter 1: stratix iv transceiver architecture 1?195 auxiliary transmit (atx) pll block ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?157 shows the location of the atx pll blocks in three transceiver block device families (for 230k and 530k devices and all other devices). figure 1?158 shows the location of the atx pll blocks in four transceiver block device families. figure 1?157. location of atx pll blocks with a six transceiver block stratix iv gx device (three on each side) figure 1?158. location of atx pll blocks in an eight-transceiver block stratix iv gx device (four on each side) gxbl0 gxbl2 gxbl1 atx pll l0 (6g) atx pll r0 (6g) gxbr0 gxbr1 gxbr2 in 230k and 530k stratix i v gx de vices gxbl2 gxbl1 gxbl0 atx pll l0 (6g) atx pll r0 (6g) gxbr0 gxbr1 gxbr2 atx pll l1 (6g) atx pll r1 (6g) in stratix i v gx de vices other than 230k and 530k gxbl3 gxbl2 gxbl1 gxbl0 atx pll l1 (6g) atx pll l0 (6g) gxbr0 atx pll r0 (6g) atx pll r1 (6g) gxbr1 gxbr2 gxbr3 1?196 chapter 1: stratix iv transceiver architecture auxiliary transmit (atx) pll block stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?159 and figure 1?160 show the locations of the 6g and 10g atx plls in each stratix iv gt device. input reference clocks for the atx pll block the 6g atx pll block does not have a dedicated reference clock pin. the following are the possible input reference clock sources: refclks from the transceiver blocks on the same side of the device if the corresponding cmu channels are not used as transceiver channels input reference clock provided through the pll cascade clock network clock inputs connected through the global clock lines altera recommends using the refclk pins from the adjacent transceiver block below the atx pll block to improve performance. figure 1?159. location of transceiver channel and pll in stratix iv gt devices (ep4s40g2f40, ep4s40g5h40, ep4s100g2f40 and ep4s100g5h40) atx pll l1 (10g) atx pll l0 (6g) transceiver block gxbl0 transceiver block gxbl1 transceiver block gxbl2 atx pll r1 (10g) atx pll r0 (6g) transceiver block gxbr0 transceiver block gxbr1 transceiver block gxbr2 figure 1?160. location of transceiver channel and pll in stratix iv gt devices (ep4s100g5f45) atx pll l2 (10g) atx pll l1 (6g) transceiver block gxbl1 transceiver block gxbl2 transceiver block gxbl3 atx pll r2 (10g) atx pll r1 (6g) transceiver block gxbr1 transceiver block gxbr2 transceiver block gxbr3 atx pll l0 (6g) atx pll r0 (6g) transceiver block gxbl0 transceiver block gxbr0 chapter 1: stratix iv transceiver architecture 1?197 auxiliary transmit (atx) pll block ? march 2010 altera corporation stratix iv device handbook volume 2 for the 10g atx pll, stratix iv gt devices only allow driving the reference clock source from one of the dedicated reflck pins on the same side of the device. 1 for improved jitter performance, altera strongly recommends using the refclk pins of the transceiver block located immediately below the 10g atx pll block to drive the input reference clock. f for more information about the input reference clocks for atx plls, refer to the stratix iv transceiver clocking chapter. architecture of the atx pll block figure 1?161 shows the atx pll block components (the atx pll, atx clock divider, and a shared control signal generation block). the functional blocks on the atx pll are similar to the blocks explained in ?cmu0 pll? on page 1?99 . the values of the /m and /l divider settings in the atx pll are automatically selected by the quartus ii software based on the transceiver channel configuration. the atx pll high-speed clock output provides high-speed serial clocks for non-bonded functional modes such as cei (with the ?none? subprotocol). figure 1?161. atx pll block notes to figure 1?161 : (1) in non-bonded functional modes (for example, cei functional mode), the transmitter channel uses the transmitter local clock divider to divide this high-speed clock output to provide clocks for its pma and pcs blocks. (2) this is used in basic 4, 8, and pci express (pipe) 4 and 8 functional modes. 8 atx pll high-speed clock (1) atx pll block pll_po w erdo wn cascaded pll clock glob al clock line itb clock lines pcierates witch atx pll inp ut reference clock atx pll high-speed serial clock for bonded modes (2) atx clock divider b lock pcie_gen2s witch pcie_gen2s witch_done pci express rate s witch controller 1?198 chapter 1: stratix iv transceiver architecture auxiliary transmit (atx) pll block stratix iv device handbook volume 2 ? march 2010 altera corporation atx clock divider the atx clock divider divides the atx pll high-speed clock and provides high-speed serial and low-speed parallel clock for bonded functional modes such as pci express (pipe) (4 and 8), basic 4 and 8, and pma-direct mode with n configuration. for pci express (pipe) functional mode support, the atx clock divider consists of the pci express (pipe) rateswitch circuit to enable dynamic rateswitch between pci express (pipe) gen1 and gen2 data rates. for more information on this circuit, refer to ?cmu0 channel? on page 1?98 . the clock outputs from the atx pll block are provided to the transmitter channels through the n_top or n_bottom clock lines, as shown in figure 1?162 . f for more information, refer to the stratix iv transceiver clocking chapter. the differences between 10g atx pll, 6g atx pll, and cmu pll table 1?70 lists the differences between the 10g atx pll, 6g atx pll, and cmu pll. figure 1?162. atx clock divider 0 1 atx clock di vider b lock pcie_gen2s witch_done pcie_gen2s witch atx pll high-speed clock o utput pci express clocks witch circuit /s (4, 5, 8, 10) /2 lo w-speed parallel clocks (for bonded modes) coreclko u t to fpga fab ric (for bonded modes) high-speed serial clock (for bonded modes) table 1?70. differences between the 10g atx pll, 6g atx pll, and cmu pll (part 1 of 2) difference category/plls 10g atx pll 6g atx pll cmu pll available in stratix iv gt device stratix iv gx and gt devices stratix iv gx and gt devices data rates (gbps) 9.9 to 11.3 4.8 to 5.4 and 6.0 and 6.5 2.4 to 2.7 and 3.0 and 3.25 (1) 1.2 to 1.35 and 1.5 to 1.625 (1) 0.6 to 8.5 input reference clock options only dedicated refclk pins on the same side of the device (2) , (3) clock inputs connected through the inter transceiver block (itb) lines. clock inputs connected through the pll cascade clock network. clock inputs connected through the global clock lines. (3) clock inputs connected through the inter transceiver block (itb) lines. clock inputs connected through the pll cascade clock network. clock inputs connected through the global clock lines, refclk0 and refclk1 clock input, dedicated refclks in the transceiver block. (3) chapter 1: stratix iv transceiver architecture 1?199 calibration blocks ? march 2010 altera corporation stratix iv device handbook volume 2 calibration blocks stratix iv gx and gt devices contain calibration circuits that calibrate the oct resistors and the analog portions of the transceiver blocks to ensure that the functionality is independent of process, voltage, or temperature variations. calibration block location figure 1?163 shows the location and number of calibration blocks available for different stratix iv gx and gt devices. in figure 1?163 through figure 1?168 , the calibration block r0 and l0 refer to the calibration blocks on the right and left side of the devices, respectively. power supply?v cca_l/r (v) options for plls 3.3 3.0 or 3.3 (4) 2.5 or 3.0 or 3.3 (4) phase noise lower when compared with the cmu pll (5) lower when compared with the cmu pll (5) higher when compared with the atx plls (5) notes to ta bl e 1? 70 : (1) using the l dividers available in atx plls. (2) for improved jitter performance, altera strongly recommends using the refclk pins of the transceiver block located immediately below the 10g atx pll block to drive the input reference clock. (3) for more information, refer to the input reference clock source table in the stratix iv transceiver clocking chapter. (4) option in stratix iv gt devices. (5) for more information about phase noise and pll bandwidths of atx and cmu plls, refer to the characterization reports. table 1?70. differences between the 10g atx pll, 6g atx pll, and cmu pll (part 2 of 2) difference category/plls 10g atx pll 6g atx pll cmu pll figure 1?163. calibration block locations in stratix iv gx and gt device with two transceiver blocks (on each side) stratix iv gx and gt device gxbl1 gxbl0 gxbr1 gxbr0 calibration block l0 calibration block r0 2k 2k atx pll l0 atx pll r0 1?200 chapter 1: stratix iv transceiver architecture calibration blocks stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?164 shows stratix iv gx 230k and 530k devices that have three transceiver blocks each on the left and right side and one atx pll block on each side. figure 1?164. calibration block locations in stratix iv gx 230k and 530k devices with three transceiver blocks (on each side) stratix iv gx device calibration block l1 calibration block r1 gxbl2 gxbr2 gxbl1 gxbr1 gxbl0 gxbr0 calibration block l0 calibration block r0 2k 2k 2k 2k atx pll l0 atx pll r0 chapter 1: stratix iv transceiver architecture 1?201 calibration blocks ? march 2010 altera corporation stratix iv device handbook volume 2 figure 1?165 shows stratix iv gx devices other than 230k and 530k that have three transceiver blocks each on the left and right side and two atx pll blocks on each side. figure 1?165. calibration block locations in stratix iv gx devices other than 230k and 530k with three transceiver blocks (on each side) stratix iv gx device calibration block l1 calibration block r1 gxbl2 gxbr2 gxbl1 gxbr1 gxbl0 gxbr0 calibration block l0 calibration block r0 2k 2k 2k 2k atx pll l0 atx pll r0 atx pll l1 atx pll r0 1?202 chapter 1: stratix iv transceiver architecture calibration blocks stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?166 shows stratix iv gx devices that have four transceiver blocks each on the left and right side and two atx pll blocks on each side. figure 1?167 shows stratix iv gx devices that have two transceiver blocks only on the right side of the device. the quartus ii software automatically selects the appropriate calibration block based on the assignment of the transceiver tx_dataout and rx_datain pins. figure 1?166. calibration block locations in stratix iv gx devices with four transceiver blocks (on each side) figure 1?167. calibration block locations in stratix iv gx devices with two transceiver blocks (right side only) stratix iv gx device calibration block l1 calibration block r1 gxbl3 gxbr3 gxbl2 gxbr2 gxbl1 gxbr1 gxbl0 gxbr0 calibration block l0 calibration block r0 2k 2k 2k 2k atx pll l1 atx pll l0 atx pll r0 atx pll r1 stratix iv gx device gxbr1 gxbr0 calibration block r0 2k atx pll r0 chapter 1: stratix iv transceiver architecture 1?203 calibration blocks ? march 2010 altera corporation stratix iv device handbook volume 2 calibration the calibration block internally generates a constant internal reference voltage, independent of process, voltage, or temperature variations. it uses the internal reference voltage and external reference resistor (you must connect the resistor to the rref pin) to generate constant reference currents. these reference currents are used by the analog block calibration circuit to calibrate the transceiver blocks. the oct calibration circuit calibrates the oct resistors present in the transceiver channels. you can enable the oct resistors in the transceiver channels through the altgx megawizard plug-in manager. you must connect a separate 2 k (tolerance max 1%) external resistor on each rref pin in the stratix iv gx and gt device to ground. to ensure proper operation of the calibration block, the rref resistor connection in the board must be free from external noise. input signals to the calibration block the altgx megawizard plug-in manager provides the cal_blk_clk and cal_blk_powerdown ports to control the calibration block: cal_blk_clk ?you must use the cal_blk_clk port to provide input clock to the calibration clock. the frequency of cal_blk_clk must be within 10 mhz to 125 mhz (this range is preliminary. final values will be available after characterization). you can use dedicated clock routes such as the global or regional clock. if you do not have suitable input reference clock or dedicated clock routing resources available, use divide-down logic from the fpga fabric to generate a slow clock and use local clocking routing. drive the cal_blk_clk port of all altgx instances that are associated with the same calibration block from the same input pin or logic. cal_blk_powerdown ?you can perform calibration multiple times by using the cal_blk_powerdown port available through the altgx megawizard plug-in manager. assert this signal for approximately 500 ns (this is preliminary. final values will be available after characterization). following de-assertion of cal_blk_powerdown , the calibration block restarts the calibration process. drive the cal_blk_powerdown port of all altgx instances that are associated with the same calibration block from the same input pin or logic. 1?204 chapter 1: stratix iv transceiver architecture built-in self test modes stratix iv device handbook volume 2 ? march 2010 altera corporation figure 1?168 shows the required inputs to the calibration block. built-in self test modes this section describes built-in self test (bist) modes. bist mode pattern generators and verifiers each transceiver channel in the stratix iv gx and gt devices contain a different bist pattern generator and verifier. using these bist patterns, you can verify the functionality of the functional blocks in the transceiver channel without requiring user logic. the bist functionality is provided as an optional mechanism for debugging transceiver channels. figure 1?169 shows the enabled input and output ports when you select bist mode (except incremental patterns). figure 1?168. input signals to the calibration blocks calibration block rref pin cal_blk_clk cal_blk_powerdown internal reference voltage generator reference signal oct calibration circuit analog block calibration circuit oct calibration control analog block calibration control figure 1?169. input and output ports for bist modes notes to figure 1?169 : (1) rx_serilalpbken is required in prbs. (2) rx_bisterr and rx_bistdone are only available in prbs and bist modes. tx_datain[] tx_digitalreset rx_digitalreset rx_seriallp b ken[] (1) pll_inclk bu ilt-in self test (bist) tx_datao ut rx_bisterr (2) rx_bistdone (2) chapter 1: stratix iv transceiver architecture 1?205 built-in self test modes ? march 2010 altera corporation stratix iv device handbook volume 2 three types of pattern generators and verifiers are available: bist incremental data generator and verifier?this is only available in parallel loopback mode. for more information, refer to ?serial loopback? on page 1?188 . high frequency and low frequency pattern generator?the high frequency patterns generate alternate ones and zeros and the low frequency patterns generate five ones and five zeroes in single-width mode and ten ones and ten zeroes in double-width mode. these patterns do not have a corresponding verifier. you can enable the serial loopback option to dynamically loop the generated pattern to the receiver channel using the rx_seriallpbken port. therefore, the 8b/10b encoder/decoder blocks are bypassed in the basic prbs mode. pseudo random binary sequence (prbs) generator and verifier?the prbs generator and verifier interface with the serializer and deserializer in the pma blocks. the advantage of using a prbs data stream is that the randomness yields an environment that stresses the transmission medium. in the data stream, you can observe both random jitter and deterministic jitter using a time interval analyzer, bit error rate tester, or oscilloscope. the prbs repeats after completing an iteration. the number of bits the prbsx pattern sends before repeating the pattern is (2 ^x -1 ) bits. different prbs patterns are available as a subprotocol under basic functional mode for single-width and double-width mode, as shown in the following sections. you can enable the serial loopback option in basic prbs mode to loop the generated pattern to the receiver channel. this creates a rx_seriallpbken port that you can use to dynamically control the serial loopback. the 8b/10b encoder/decoder blocks are bypassed in basic prbs mode. figure 1?170 shows the datapath for the prbs patterns. the generated prbs pattern is sent to the transmitter serializer. the verifier checks the data from the word aligner. figure 1?170. bist prbs, high frequency, and low frequency pattern datapath recei v er channel pcs transmitter channel pcs transmitter channel pma recei v er channel pma fpga fa b ric tx phase compen- sation fifo byte serializer 8b/10b encoder bist prbs, high-fre q, lo w -freg pattern generator serial loop b ack can be dynamically enab led w ord aligner bist prbs v erifier deske w fifo rate match fifo 8b/10b decoder byte de- serializer byte ordering rx phase compen- sation fifo serializer de- serializer receiv er cdr 1?206 chapter 1: stratix iv transceiver architecture built-in self test modes stratix iv device handbook volume 2 ? march 2010 altera corporation prbs in single-width mode table 1?71 lists the various prbs patterns and corresponding word alignment patterns for prbs in single-width mode configuration. the status signals rx_bistdone and rx_bisterr indicate the status of the verifier. the rx_bistdone port gets asserted and stays high when the verifier either receives one full cycle of incremental pattern or it detects an error in the receiver data. the rx_bisterr signal gets asserted and stays high when the verifier detects an error. you can reset the prbs pattern generator and verifier by asserting the tx_digitalreset and rx_digitalreset signals, respectively. prbs in double-width mode table 1?72 lists the various prbs patterns and corresponding word alignment patterns for prbs in double-width mode configuration. table 1?71. available prbs, high frequency, and low frequency patterns in single-width mode patterns polynomial channel width of 8bit (1) word alignment pattern with channel width 8 bit maximum data rate with channel width 8 bit (gbps) channel width of 10 bit (1) word alignment pattern maximum data rate with channel width 10 bit (gbps) prbs 7 x 7 + x 6 + 1 y 16?h3040 2.5 n na n/a prbs 8 x 8 + x 7 + 1 y 16?hff5a 2.5 n na n/a prbs 10 x 10 + x 7 + 1 n na n/a y 10?h3ff 3.125 prbs 23 x 23 + x 18 + 1 y 16?hffff 2.5 n na n/a high frequency (2) 1010101010 y na 2.5 y na 3.125 low frequency (2) 0000011111 n na n/a y na 3.125 notes to ta bl e 1? 71 : (1) channel width refers to the what is the channel width? option in the general screen of the altgx megawizard plug-in manager. based on the selection, an 8 or 10 bits wide pattern is generated as indicated by a yes (y) or no (n) . (2) a verifier is not available for the specified patterns. table 1?72. available prbs, high frequency, and low frequency patterns in double-width mode (part 1 of 2) patterns polynomial channel width of 16-bit (1) word alignment pattern with channel width of 16-bit maximum data rate with channel width of 16-bit (gbps) channel width of 20-bit (1) word alignment pattern maximum data rate with channel width of 20-bit (gbps) prbs 7 x 7 + x 6 + 1 y 16?h3040 5 y 20?h43040 6.375 prbs 23 x 23 + x 18 + 1 y 32?h007ffff f 5 y 40?h00007ff fff 6.375 high frequency (2) 1010101010 y na 5 y n/a 6.375 chapter 1: stratix iv transceiver architecture 1?207 transceiver port lists ? march 2010 altera corporation stratix iv device handbook volume 2 the status signals rx_bisterr and rx_bistdone are available to indicate the status of the verifier. for more information about the behavior of these status signals, refer to ?single-width mode? on page 1?17 . transceiver port lists instantiate the stratix iv gx and gt transceivers using the altgx megafunction instance in the quartus ii megawizard plug-in manager. the altgx megafunction instance allows you to configure transceivers for your intended protocol and select optional control and status ports to and from the instantiated transceiver channels. table 1?73 through table 1?79 provide a brief description of the altgx megafunction ports. table 1?73 lists the altgx megafunction transmitter ports. low frequency (2) 0000011111 n na n/a y n/a 6.375 notes to ta bl e 1? 72 : (1) channel width refers to the what is the channel width? option in the general screen of the altgx megawizard plug-in manager. based on the selection, a 16 or 20 bits wide pattern is generated as indicated by a yes (y) or no (n) . (2) verifier is not available for the specified patterns. table 1?72. available prbs, high frequency, and low frequency patterns in double-width mode (part 2 of 2) patterns polynomial channel width of 16-bit (1) word alignment pattern with channel width of 16-bit maximum data rate with channel width of 16-bit (gbps) channel width of 20-bit (1) word alignment pattern maximum data rate with channel width of 20-bit (gbps) table 1?73. stratix iv gx and gt altgx megafunction ports: transmitter ports (part 1 of 4) port name input/ output clock domain description scope transmitter phase compensation fifo tx_datain input synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclk for bonded modes. parallel data input from the fpga fabric to the transmitter. bus width?depends on the channel width multiplied by the number of channels per instance. channel 1?208 chapter 1: stratix iv transceiver architecture transceiver port lists stratix iv device handbook volume 2 ? march 2010 altera corporation tx_clkout output clock signal fpga fabric-transceiver interface clock. bonded channel configurations?not available. non-bonded channel configurations?each channel has a tx_clkout signal. use this clock signal to clock the parallel data tx_datain from the fpga fabric into the transmitter. channel tx_coreclk input clock signal optional write clock port for the transmitter phase compensation fifo. if not selected?the quartus ii software automatically selects tx_clkout/coreclkout as the write clock for transmitter phase compensation fifo. if selected?you must drive this port with a clock that is frequency locked to tx_clkout/coreclkout . channel tx_phase_comp_fifo_ error output synchronous to tx_clkout/ coreclkout clock signal. transmitter phase compensation fifo full or empty indicator. a high level?the transmitter phase compensation fifo is either full or empty. channel 8b/10b encoder tx_ctrlenable input synchronous to tx_clkout/ coreclkout clock signal. 8b/10b encoder /kx.y/ or /dx.y/ control. when asserted high?the 8b/10b encoder encodes the data on the tx_datain port as a /kx.y/ control code group. when de-asserted low?it encodes the data on the tx_datain port as a /dx.y/ data code group. channel width: 8? tx_ctrlenable = 1 16? tx_ctrlenable = 2 32? tx_ctrlenable = 4 channel table 1?73. stratix iv gx and gt altgx megafunction ports: transmitter ports (part 2 of 4) port name input/ output clock domain description scope chapter 1: stratix iv transceiver architecture 1?209 transceiver port lists ? march 2010 altera corporation stratix iv device handbook volume 2 tx_forcedisp input asynchronous signal. minimum pulse width is two parallel clock cycles. 8b/10b encoder force disparity control. when asserted high?forces the 8b/10b encoder to encode the data on the tx_datain port with a positive or negative disparity depending on the tx_dispval signal level. when de-asserted low?the 8b/10b encoder encodes the data on the tx_datain port according to the 8b/10b running disparity rules. channel width: 8? tx_forcedisp = 1 16? tx_forcedisp = 2 32? tx_forcedisp = 4 channel tx_dispval input asynchronous signal. minimum pulse width is two parallel clock cycles. 8b/10b encoder force disparity value. a high level?when the tx_forcedisp signal is asserted high, it forces the 8b/10b encoder to encode the data on the tx_datain port with a negative starting running disparity. a low level?when the tx_forcedisp signal is asserted high, it forces the 8b/10b encoder to encode the data on the tx_datain port with a positive starting running disparity. channel width: 8? tx_dispval = 1 16? tx_dispval = 2 32? tx_dispval = 4 channel tx_invpolarity input asynchronous signal. minimum pulse width is two parallel clock cycles. transmitter polarity inversion control. this feature is useful for correcting situations in which the positive and negative signals of the differential serial link are accidentally swapped during board layout. when asserted high in single-width modes?the polarity of every bit of the 8-bit or 10-bit input data to the serializer gets inverted. when asserted high in double-width modes?the polarity of every bit of the 16-bit or 20-bit input data to the serializer gets inverted. channel table 1?73. stratix iv gx and gt altgx megafunction ports: transmitter ports (part 3 of 4) port name input/ output clock domain description scope 1?210 chapter 1: stratix iv transceiver architecture transceiver port lists stratix iv device handbook volume 2 ? march 2010 altera corporation table 1?74 lists the altgx megafunction receiver ports. transmitter physical media attachment tx_dataout output n/a transmitter serial data output port. channel fixedclk input clock signal 125-mhz clock for receiver detect and offset cancellation in pci express (pipe) mode. channel table 1?73. stratix iv gx and gt altgx megafunction ports: transmitter ports (part 4 of 4) port name input/ output clock domain description scope table 1?74. stratix iv gx and gt altgx megafunction ports: receiver ports (part 1 of 8) port name input/ output clock domain description scope rx_syncstatus output synchronous to coreclkout clock signal word alignment synchronization status indicator. automatic synchronization state machine mode?this signal is driven high if the conditions required to remain in synchronization are met. driven low if the conditions required to lose synchronization are met. manual alignment mode?the behavior of this signal depends on whether the transceiver is configured in single-width or double-width mode. bit-slip mode?not available. for more information, refer to ?word aligner in single-width mode? on page 1?57 and ?word aligner in double-width mode? on page 1?63 . channel width: 8/10? rx_syncstatus = 1 16/20? rx_syncstatus = 2 32/40? rx_syncstatus = 4 channel rx_bitslip input asynchronous signal. minimum pulse width is two parallel clock cycles. bit-slip control for the word aligner configured in bit-slip mode. at every rising edge, word aligner slips one bit into the received data stream, effectively shifting the word boundary by one bit. channel rx_ala2size input asynchronous signal. minimum pulse width is two parallel clock cycles. available only in sonet oc-12 and oc-48 modes. select between these options: 0 = 16-bit a1a2 1 = 32-bit a1a1a2a2 channel chapter 1: stratix iv transceiver architecture 1?211 transceiver port lists ? march 2010 altera corporation stratix iv device handbook volume 2 rx_rlv output asynchronous signal. driven for a minimum of two recovered clock cycles in configurations without byte serializer and a minimum of three recovered clock cycles in configurations with byte serializer. run-length violation indicator. a high pulse is driven when the number of consecutive 1s or 0s in the received data stream exceeds the programmed run length violation threshold. channel rx_invpolarity input asynchronous signal. minimum pulse width is two parallel clock cycles. generic receiver polarity inversion control. useful feature for correcting situations where the positive and negative signals of the differential serial link are accidentally swapped during board layout. when asserted high in single-width modes?the polarity of every bit of the 8-bit or 10-bit input data word to the word aligner gets inverted. when asserted high in double-width modes?the polarity of every bit of the 16-bit or 20-bit input data to the word aligner gets inverted. channel rx_revbitorderwa input asynchronous signal. minimum pulse width is two parallel clock cycles. receiver bit reversal control. this is a useful feature where the link transmission order is msb to lsb. available only in basic single-width and double-width modes with the word aligner configured in bit-slip mode. when asserted high in basic single-width modes?the 8-bit or 10-bit data d[7:0] or d[9:0] at the output of the word aligner gets rewired to d[0:7] or d[0:9] , respectively. when asserted high in basic double-width modes?the 16-bit or 20-bit data d[15:0] or d[19:0] at the output of the word aligner gets rewired to d[0:15] or d[0:19] , respectively. channel table 1?74. stratix iv gx and gt altgx megafunction ports: receiver ports (part 2 of 8) port name input/ output clock domain description scope 1?212 chapter 1: stratix iv transceiver architecture transceiver port lists stratix iv device handbook volume 2 ? march 2010 altera corporation rx_revbyteorderwa input asynchronous signal. minimum pulse width is two parallel clock cycles. receiver byte reversal control. this is a useful feature in situations where the msbyte and lsbyte of the transmitted data are erroneously swapped. available only in basic double-width mode. when asserted high, the msbyte and lsbyte of the 16- and 20-bit data at the output of the word aligner get swapped. channel deskew fifo rx_channelaligned output synchronous to coreclkout clock signal xaui deskew fifo channel aligned indicator. available only in xaui mode. a high level?the xaui deskew state machine is either in align_acquired_1 , align_acquired_2 , align_acquired_3 , or align_acquired_4 state, as specified in the pcs deskew state diagram in the ieee p802.3ae specification. a low level?the xaui deskew state machine is either in loss_of_alignment , align_detect_1 , align_detect_2 , or align_detect_3 state, as specified in the pcs deskew state diagram in the ieee p802.3ae specification. transceive r block rate match (clock rate compensation) fifo rx_ rmfifodatainserted output synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclkout for bonded modes. rate match fifo insertion status indicator. a high level?the rate match pattern byte has inserted to compensate for the ppm difference in reference clock frequencies between the upstream transmitter and the local receiver. channel rx_rmfifodatadeleted output synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclkout for bonded modes. rate match fifo deletion status indicator. a high level?the rate match pattern byte got deleted to compensate for the ppm difference in reference clock frequencies between the upstream transmitter and the local receiver. channel table 1?74. stratix iv gx and gt altgx megafunction ports: receiver ports (part 3 of 8) port name input/ output clock domain description scope chapter 1: stratix iv transceiver architecture 1?213 transceiver port lists ? march 2010 altera corporation stratix iv device handbook volume 2 rx_rmfifofull output synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclkout for bonded modes. rate match fifo full status indicator. a high level indicates that the rate match fifo is full. without byte serializer ?driven a minimum of two recovered clock cycles. with byte serializer?driven a minimum of three recovered clock cycles. channel rx_rmfifoempty output synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclkout for bonded modes. rate match fifo empty status indicator. a high level?the rate match fifo is empty. without byte serializer?driven a minimum of two recovered clock cycles. with byte serializer?driven a minimum of three recovered clock cycles. channel 8b/10b decoder rx_ctrldetect output synchronous to coreclkout clock signal receiver control code indicator. available in configurations with 8b/10b decoder. a high level?the associated received code group is a control (/kx.y/) code group. a low level?the associated received code group is a data (/dx.y/) code group. the width of this signal depends on the following channel width: channel width: 8? rx_ctrldetect = 1 16? rx_ctrldetect = 2 32? rx_ctrldetect = 4 channel table 1?74. stratix iv gx and gt altgx megafunction ports: receiver ports (part 4 of 8) port name input/ output clock domain description scope 1?214 chapter 1: stratix iv transceiver architecture transceiver port lists stratix iv device handbook volume 2 ? march 2010 altera corporation rx_errdetect output synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclkout for bonded modes. 8b/10b code group violation or disparity error indicator. available in configurations with 8b/10b decoder. a high level?a code group violation or disparity error was detected on the associated received code group. use with the rx_disperr signal to differentiate between a code group violation and/or a disparity error as follows: ? [rx_errdetect: rx_disperr ] ? 2?b00?no error ? 2?b10?code group violation ? 2?b11?disparity error or both channel width: 8? rx_errdetect = 1 16? rx_errdetect = 2 32? rx_errdetect = 4 channel rx_disperr output synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclkout for bonded modes. 8b/10b disparity error indicator port. available in configurations with 8b/10b decoder. a high level?a disparity error was detected on the associated received code group. channel width: 8? rx_disperr = 1 16? rx_disperr = 2 32? rx_disperr = 4 channel rx_runningdisp output synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclkout for bonded modes. 8b/10b running disparity indicator. available in configurations with the 8b/10b decoder. a high level?the data on the rx_dataout port was received with a negative running disparity. a low level?the data on the rx_dataout port was received with a positive running disparity. channel width: 8? rx_runningdisp = 1 16? rx_runningdisp = 2 32? rx_runningdisp = 4 channel table 1?74. stratix iv gx and gt altgx megafunction ports: receiver ports (part 5 of 8) port name input/ output clock domain description scope chapter 1: stratix iv transceiver architecture 1?215 transceiver port lists ? march 2010 altera corporation stratix iv device handbook volume 2 byte ordering block rx_enabyteord input asynchronous signal enable byte ordering control. available in configurations with the byte ordering block enabled. the byte ordering block is rising-edge sensitive to this signal. a low-to-high transition triggers the byte ordering block to restart the byte ordering operation. channel rx_ byteorderalignstatus output synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclkout for bonded modes. byte ordering status indicator. available in configurations with the byte ordering block enabled. a high level?the byte ordering block has detected the programmed byte ordering pattern in the lsbyte of the received data from the byte deserializer. channel receiver phase compensation fifo rx_dataout output synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclkout for bonded modes. parallel data output from the receiver to the fpga fabric. the bus width depends on the channel width multiplied by the number of channels per instance. channel rx_clkout output clock signal recovered clock from the receiver channel. available only when the rate match fifo is not used in the receiver datapath. channel rx_coreclk input clock signal optional read clock port for the receiver phase compensation fifo. if not selected?the quartus ii software automatically selects rx_clkout/tx_clkout/ coreclkout as the read clock for the receiver phase compensation fifo. if selected?drive this port with a clock that has 0 ppm difference with respect to rx_clkout/tx_clkout/ coreclkout . channel table 1?74. stratix iv gx and gt altgx megafunction ports: receiver ports (part 6 of 8) port name input/ output clock domain description scope 1?216 chapter 1: stratix iv transceiver architecture transceiver port lists stratix iv device handbook volume 2 ? march 2010 altera corporation rx_phase_comp_fifo_ error output synchronous to tx_clkout or coreclkout . tx_clkout for non-bonded modes. coreclkout for bonded modes. receiver phase compensation fifo full or empty indicator. a high level?the receiver phase compensation fifo is either full or empty. channel receiver physical media attachment (pma) rx_datain input n/a receiver serial data input port. channel rx_cruclk input clock signal input reference clock for the receiver clock and data recovery. channel rx_pll_locked output asynchronous signal receiver cdr lock-to-reference indicator. a high level?the receiver cdr is locked to the input reference clock. a low level?the receiver cdr is not locked to the input reference clock. channel rx_freqlocked output asynchronous signal receiver cdr lock mode indicator. a high level?the receiver cdr is in lock-to-data mode. a low level?the receiver cdr is in lock-to-reference mode. channel rx_locktodata input asynchronous signal receiver cdr lock-to-data mode control signal. when asserted high?the receiver cdr is forced to lock-to-data mode. when de-asserted low?the receiver cdr lock mode depends on the rx_locktorefclk signal level. channel rx_locktorefclk input asynchronous signal receiver cdr lock-to-reference mode control signal. the rx_locktorefclk signal, along with the rx_locktodata signal, controls whether the receiver cdr is in automatic (0/0), lock-to-reference (0/1), or lock-to-data (1/x) mode. channel table 1?74. stratix iv gx and gt altgx megafunction ports: receiver ports (part 7 of 8) port name input/ output clock domain description scope chapter 1: stratix iv transceiver architecture 1?217 transceiver port lists ? march 2010 altera corporation stratix iv device handbook volume 2 table 1?75 lists the altgx megafunction cmu ports. rx_signaldetect output asynchronous signal signal threshold detect indicator. available in basic functional mode when the 8b/10b encoder/decoder is selected. available in pci express (pipe) mode. a high level?that the signal present at the receiver input buffer is above the programmed signal detection threshold value. if the electrical idle inference block is disabled in pci express (pipe) mode, the rx_signaldetect signal is inverted and driven on the pipeelecidle port. channel rx_seriallpbken input asynchronous signal serial loopback control port. 0?normal datapath, no serial loopback 1?serial loopback channel table 1?74. stratix iv gx and gt altgx megafunction ports: receiver ports (part 8 of 8) port name input/ output clock domain description scope table 1?75. stratix iv gx and gt altgx megafunction ports: cmu (part 1 of 2) port name input/ output clock domain description scope pll_inclk input clock signal input reference clock for the cmu phase-locked loop. transceiver block pll_locked output asynchronous signal cmu pll lock indicator. a high level?the cmu pll is locked to the input reference clock. a low level?the cmu pll is not locked to the input reference clock. transceiver block 1?218 chapter 1: stratix iv transceiver architecture transceiver port lists stratix iv device handbook volume 2 ? march 2010 altera corporation table 1?76 lists the altgx megafunction dynamic reconfiguration ports. pll_powerdown input asynchronous signal. for minimum pulse width requirements, refer the device dc and switching characteristics chapter. cmu pll power down. asserted high?the cmu pll is powered down. de-asserted low?the cmu pll is active and locks to the input reference clock. note: asserting the pll_powerdown signal does not power down the refclk buffers. transceiver block coreclkout output clock signal fpga fabric-transceiver interface clock. generated by the cmu0 clock divider in the transceiver block in 4 bonded channel configurations. generated by the cmu0 clock divider in the master transceiver block in 8 bonded channel configurations. not available in non-bonded channel configurations. use to clock the write port of the transmitter phase compensation fifos in all bonded channels and to clock parallel data tx_datain from the fpga fabric into the transmitter phase compensation fifo of all bonded channels. use to clock the read port of the receiver phase compensation fifos in all bonded channels with rate match fifo enabled and to clock parallel data rx_dataout from the receiver phase compensation fifos of all bonded channels (with rate match fifo enabled) into the fpga fabric. transceiver block table 1?75. stratix iv gx and gt altgx megafunction ports: cmu (part 2 of 2) port name input/ output clock domain description scope table 1?76. stratix iv gx and gt altgx megafunction ports: dynamic reconfiguration (part 1 of 2) port name input/ output clock domain description scope reconfig_clk input clock signal dynamic reconfiguration clock. also used for offset cancellation in all modes except pci express (pipe) mode. if configured in transmitter only mode?the frequency range is 2.5 mhz to 50 mhz. if configured in receiver only or receiver and transceiver mode?the frequency range of this clock is 37.5 mhz to 50 mhz. chapter 1: stratix iv transceiver architecture 1?219 transceiver port lists ? march 2010 altera corporation stratix iv device handbook volume 2 table 1?77 lists the altgx megafunction pci express (pipe) interface ports. reconfig_togxb input asynchronous signal from the dynamic reconfiguration controller. reconfig_fromgxb output asynchronous signal to the dynamic reconfiguration controller. table 1?76. stratix iv gx and gt altgx megafunction ports: dynamic reconfiguration (part 2 of 2) port name input/ output clock domain description scope table 1?77. stratix iv gx and gt altgx megafunction ports: pci express (pipe) interface (part 1 of 4) port name input/ output clock domain description scope pci express (pipe) interface (available only in pci express [pipe] functional mode) powerdn input asynchronous signal pci express (pipe) power state control. functionally equivalent to the powerdown[1:0] signal defined in the pci express (pipe) specification revision 2.0. the width of this signal is 2 bits and is encoded as follows: ? 2'b00: p0?normal operation ? 2'b01: p0s?low recovery time latency, low power state ? 2'b10: p1?longer recovery time latency, lower power state ? 2'b11: p2?lowest power state channel tx_ forcedispcompliance input asynchronous signal force 8b/10b encoder to encode with a negative running disparity. functionally equivalent to the txcompliance signal defined in pci express (pipe) specification revision 2.0. must be asserted high only when transmitting the first byte of the pci express (pipe) compliance pattern to force the 8b/10b encode with a negative running disparity as required by the pci express (pipe) protocol. channel tx_forceelecidle input asynchronous signal force transmitter buffer to pci express (pipe) electrical idle signal levels. functionally equivalent to the txelecidle signal defined in the pci express (pipe) specification revision 2.0. available in the basic mode. channel rateswitch input asynchronous signal pci express (pipe) rateswitch control. 1?b0?gen1 (2.5 gbps) 1?b1?gen2 (5 gbps) 1?220 chapter 1: stratix iv transceiver architecture transceiver port lists stratix iv device handbook volume 2 ? march 2010 altera corporation tx_pipemargin input asynchronous signal transmitter differential output voltage level control. functionally equivalent to the txmargin signal defined in the pci express (pipe) specification revision 2.0. available only in pci express (pipe) gen2 configuration. the width of this signal is 3 bits and is decoded as follows: ? 3?b000?normal operating range ? 3?b001?full swing = 800 - 1200 mv ? 3?b010?tbd ? 3?b011?tbd ? 3?b100?if last value, full swing = 200 to 400 mv ? 3?b101?if last value, full swing = 200 to 400 mv ? 3?b110?if last value, full swing = 200 to 400 mv ? 3?b111?if last value, full swing = 200 to 400 mv tx_pipedeemph input asynchronous signal transmitter buffer de-emphasis level control. functionally equivalent to the txdeemph signal defined in the pci express (pipe) specification revision 2.0. available only in pci express (pipe) gen2 configuration. 1?b0: -6 db de-emphasis 1?b1:-3.5 db de-emphasis pipe8b10binvpolarity input asynchronous signal pci express (pipe) polarity inversion control. functionally equivalent to the rxpolarity signal defined in the pci express (pipe) specification revision 2.0. available only in pci express (pipe) mode. when asserted high?the polarity of every bit of the 10-bit input data to the 8b/10b decoder gets inverted. channel table 1?77. stratix iv gx and gt altgx megafunction ports: pci express (pipe) interface (part 2 of 4) port name input/ output clock domain description scope chapter 1: stratix iv transceiver architecture 1?221 transceiver port lists ? march 2010 altera corporation stratix iv device handbook volume 2 tx_detectrxloopback input asynchronous signal receiver detect or pci express (pipe) loopback control. functionally equivalent to the txdetectrx/loopback signal defined in the pci express (pipe) specification revision 2.0. when asserted high in the p1 power state with the tx_forceelecidle signal asserted? the transmitter buffer begins the receiver detection operation. after the receiver detect completion is indicated on the pipephydonestatus port, this signal must be de-asserted. when asserted high in the p0 power state with the tx_forceelecidle signal de-asserted?the transceiver datapath gets dynamically configured to support parallel loopback, as described in ?pci express (pipe) reverse parallel loopback? on page 1?192 . channel pipestatus output n/a pci express (pipe) receiver status port. functionally equivalent to the rxstatus[2:0] signal defined in the pci express (pipe) specification revision 2.0. the width of this signal is 3 bits per channel. the encoding of receiver status on the pipestatus port is as follows: ? 000?received data ok ? 001?1 skip added ? 010?1 skip removed ? 011?receiver detected ? 100?8b/10b decoder error ? 101?elastic buffer overflow ? 110?elastic buffer underflow ? 111?received disparity error channel pipephydonestatus output n/a phy function completion indicator. functionally equivalent to the phystatus signal defined in the pci express (pipe) specification revision 2.0. assert this signal high for one parallel clock cycle to communicate completion of several phy functions, such as power state transition, receiver detection, and signaling rate change between gen1 (2.5 gbps) and gen2 (5 gbps). channel table 1?77. stratix iv gx and gt altgx megafunction ports: pci express (pipe) interface (part 3 of 4) port name input/ output clock domain description scope 1?222 chapter 1: stratix iv transceiver architecture transceiver port lists stratix iv device handbook volume 2 ? march 2010 altera corporation table 1?78 lists the altgx megafunction reset and power down ports. rx_pipedatavalid output n/a valid data and control on the rx_dataout and rx_ctrldetect ports indicator. functionally equivalent to the rxvalid signal defined in the pci express (pipe) specification revision 2.0. channel pipeelecidle output asynchronous signal electrical idle detected or inferred at the receiver indicator. functionally equivalent to the rxelecidle signal defined in the pci express (pipe) specification revision 2.0. if the electrical idle inference block is enabled? it drives this signal high when it infers an electrical idle condition, as described in ?electrical idle inference? on page 1?136 . otherwise, it drives this signal low. if the electrical idle inference block is disabled? the rx_signaldetect signal from the signal detect circuitry in the receiver buffer is inverted and driven on this port. channel table 1?77. stratix iv gx and gt altgx megafunction ports: pci express (pipe) interface (part 4 of 4) port name input/ output clock domain description scope table 1?78. stratix iv gx and gt altgx megafunction ports: reset and power down (part 1 of 2) port name input/ output clock domain description scope gxb_powerdown input asynchronous signal. for minimum pulse width requirements, refer the device dc and switching characteristics chapter. transceiver block power down. when asserted high?all digital and analog circuitry within the pcs, pma, cmu channels, and the ccu of the transceiver block, is powered down. asserting the gxb_powerdown signal does not power down the refclk buffers. transceiver block rx_digitalreset input asynchronous signal. minimum pulse width is two parallel clock cycles. receiver pcs reset. when asserted high?the receiver pcs blocks are reset. refer to reset control and power down. channel chapter 1: stratix iv transceiver architecture 1?223 reference information ? march 2010 altera corporation stratix iv device handbook volume 2 table 1?79 lists the altgx megafunction calibration block ports. reference information use the links listed in table 1?80 for more information about some useful reference terms used in this chapter. rx_analogreset input asynchronous signal. minimum pulse width is two parallel clock cycles. receiver pma reset. when asserted high?analog circuitry within the receiver pma gets reset. refer to reset control and power down. channel tx_digitalreset input asynchronous signal. minimum pulse width is two parallel clock cycles. transmitter pcs reset. when asserted high, the transmitter pcs blocks are reset. refer to reset control and power down. channel table 1?78. stratix iv gx and gt altgx megafunction ports: reset and power down (part 2 of 2) port name input/ output clock domain description scope table 1?79. stratix iv gx and gt altgx megafunction ports: calibration block port name input/ output clock domain description scope cal_blk_clk input clock signal clock for transceiver calibration blocks. device cal_blk_powerdown input clock signal calibration block power down control. device table 1?80. reference information (part 1 of 3) terms used in this chapter useful reference points (oif) cei phy interface mode page 1?179 8b/10b decoder page 1?86 8b/10b encoder page 1?19 aeq page 1?46 auxiliary transmit (atx) pll block page 1?193 basic (pma direct) functional mode page 1?185 basic functional mode page 1?108 built-in self test modes page 1?204 byte ordering block page 1?92 byte serializer page 1?90 calibration blocks page 1?199 clock and data recovery unit (cdr) page 1?50 cmu channel architecture page 1?97 cmu0 pll page 1?99 cmu1 pll page 1?99 1?224 chapter 1: stratix iv transceiver architecture reference information stratix iv device handbook volume 2 ? march 2010 altera corporation cpri and obsai page 1?121 deserializer page 1?55 deskew fifo page 1?72 deterministic latency mode page 1?119 eyeq page 1?48 gige mode page 1?161 lock-to-data (ltd) page 1?51 lock-to-reference (ltr) page 1?50 low latency pcs datapath page 1?109 offset cancellation in the receiver buffer and receiver cdr page 1?54 parallel loopback page 1?189 pci express (pipe) clock switch circuitry page 1?52 pci express (pipe) mode page 1?124 pci express (pipe) reverse parallel loopback page 1?192 programmable common mode voltage page 1?36 programmable equalization and dc gain page 1?45 programmable pre-emphasis page 1?32 programmable differential on-chip termination page 1?38 rate match (clock rate compensation) fifo page 1?74 receiver bit reversal page 1?70 receiver input buffer page 1?36 receiver phase compensation fifo page 1?95 receiver polarity inversion page 1?68 reverse serial loopback page 1?191 reverse serial pre-cdr loopback page 1?191 sata and sas options page 1?118 sdi mode page 1?175 serial loopback page 1?188 serial rapidio mode page 1?180 signal threshold detection circuitry page 1?45 sonet/sdh mode page 1?169 transceiver block architecture page 1?11 transceiver channel locations page 1?4 transceiver port lists page 1?207 transmitter bit reversal page 1?27 transmitter local clock divider block page 1?35 transmitter output buffer page 1?30 transmitter polarity inversion page 1?25 tx phase compensation fifo page 1?14 table 1?80. reference information (part 2 of 3) terms used in this chapter useful reference points chapter 1: stratix iv transceiver architecture 1?225 document revision history ? march 2010 altera corporation stratix iv device handbook volume 2 document revision history table 1?81 shows the revision history for this chapter. word aligner page 1?56 xaui mode page 1?150 table 1?80. reference information (part 3 of 3) terms used in this chapter useful reference points table 1?81. document revision history (part 1 of 2) date and document version changes made summary of changes march 2010, v4.1 added two references to the beginning of the chapter. updated the ?configuring cmu channels for clock generation? section. updated figure 1?101 . minor text edits. ? november 2009, v4.0 added ?adaptive equalization (aeq)?, ?eyeq?, ?sata and sas options?, ?deterministic latency mode?, ?cpri and obsai?, and ?reference information? sections. added figure 1?91, figure 1?93, figure 1?95, and figure 1?97. added stratix iv gt device information. updated figures. updated tables. re-organized chapter information. minor text edits. ? june 2009, v3.1 updated the ?introduction?, ?auxiliary transmit (atx) pll block?, ?rate match (clock rate compensation) fifo?, ?transmitter buffer electrical idle?, ?pci express (pipe) gen2 (5 gbps) support?, ?reverse serial loopback?, and ?reverse serial pre-cdr loopback? sections. added new ?pci express electrical gold test with compliance base board (cbb)?, ?recommendation when using the electrical idle inference block?. and ?rate match fifo in serial rapidio mode? sections. added new figure 1?165. updated table 1?2, table 1?17, table 1?32, table 1?34, and table 1?52. updated figure 1?7, and figure 1?165 through figure 1?168. minor text edits. ? march 2009, v3.0 reorganized sections. added the section ?link coupling?. updated the section ?dc-coupled links?. ? 1?226 chapter 1: stratix iv transceiver architecture document revision history stratix iv device handbook volume 2 ? march 2010 altera corporation november 2008 v2.0 added offset cancellation in the receiver buffer and receiver cdr to the receiver channel datapath section ? may 2008 v1.0 initial release. ? table 1?81. document revision history (part 2 of 2) ? march 2010 altera corporation stratix iv device handbook volume 2 2. stratix iv transceiver clocking this chapter provides detailed information about the stratix ? iv transceiver clocking architecture. for this chapter, the term ?stratix iv devices? includes both stratix iv gx and gt devices. similarly, the term ?stratix iv transceivers? includes both stratix iv gx and gt transceivers. the clocking architecture chapter is divided into three main sections: ?input reference clocking? on page 2?2 ?describes how the reference clock is provided to the clock multiplier unit (cmu)/auxiliary transmit phase-locked loop (atx pll) to generate the clocks required for transceiver operation. ?transceiver channel datapath clocking? on page 2?20 ?describes the clocking architecture internal to the transceiver block. ?fpga fabric-transceiver interface clocking? on page 2?50 ?describes the clocking options available when interfacing the transceiver with the fpga fabric. other sections in this chapter include: ?fpga fabric plls-transceiver plls cascading? on page 2?9 ?using the cmu/atx pll for clocking user logic in the fpga fabric? on page 2?71 ?configuration examples? on page 2?73 figure 2?1 shows an overview of the clocking architecture. figure 2?1. clocking architecture overview cmu/atx pll or cdr transcei v er channels inpu t reference clocks transcei v er channel datapath clocks fpga fa b ric-transcie v er interface clocks transcei v ers fpga fa b ric siv52002-3.1 2?2 chapter 2: stratix iv transceiver clocking glossary of terms stratix iv device handbook volume 2 ? march 2010 altera corporation glossary of terms table 2?1 lists the terms used in the chapter. input reference clocking each transceiver block has: two clock multiplier unit channels ( cmu0_channel and cmu1_channel) you can configure each as either a cmu to generate transceiver clocks or as a pma-only channel. f for more information, refer to the ?cmu channel architecture? section in the stratix iv transceiver architecture chapter. four regular channels when the cmu channel is configured as a cmu, the cmu pll synthesizes the input reference clock to generate the high-speed serial transceiver clock. when the cmu channel is configured as a receiver only or receiver and transmitter channel, the cmu pll acts as a cdr and uses the input reference clock as a training clock when it is in lock-to-reference (ltr) mode. each of the four regular channels also has a receiver cdr that uses the input reference clock as a training clock when it is in ltr mode. each stratix iv device also has atx plls that you can use in addition to the cmu plls to generate the high-speed serial transceiver clock. the atx plls also need an input reference clock for operation. 6g atx plls are available in both stratix iv gx and stratix iv gt devices. 10g atx plls are available only in stratix iv gt devices. f for more information, refer to the ?auxiliary transmit (atx) pll block? and the ?transmitter channel datapath? sections in the stratix iv transceiver architecture chapter. tab le 2 ?1 . glossary of terms used in this chapter convention description atx pll auxiliary transmit pll block. for more information, refer to the ?auxiliary transmit (atx) pll block? section in the stratix iv transceiver architecture chapter. cdr clock data recovery block. for more information, refer to the ?clock and data recovery unit? section in the stratix iv transceiver architecture chapter. cmu clock multiplier unit. for more information, refer to ?cmu channel architecture? section in the stratix iv transceiver architecture chapter. itb lines the inter-transceiver block (itb) clock lines provide an input reference clock path from the refclk pins of one transceiver block cmu plls and receiver cdrs of other transceiver blocks. they also provide input reference clock to atx plls. for more information, refer to ?inter- transceiver block (itb) clock lines? on page 2?8 . chapter 2: stratix iv transceiver clocking 2?3 input reference clocking ? march 2010 altera corporation stratix iv device handbook volume 2 input reference clock source receiver clock data recoveries (cdrs), cmu plls (when the cmu channel is configured as a cmu) and atx plls can derive the input reference clock from one of the sources shown in table 2?2 . when a cmu channel is configured as a channel, its cmu pll acts as a receiver cdr and can derive the input reference clock sources 2 through 5 listed in the table 2?2 . you can also use the refclk pin of the other cmu channel within the transceiver block as a clock source as long as the other cmu channel is not configured as a receiver only or receiver and transmitter channel. for example, the cmu0 pll can derive its input reference clock from the refclk1 pin if the cmu1 channel is not configured as a receiver only or receiver and transmitter channel. 1 when a cmu channel is configured as a channel, its refclk pin is used to receive serial input data. as a result, the refclk pin is not available to provide the input reference clock. table 2?3 lists the input reference clock frequencies allowed for the 10g atx pll. tab le 2 ?2 . input reference clock source index clock source cmu pll 6g atx pll 10g atx pll cdr jitter performance (5) 1 refclk0 and refclk1 pins of the same transceiver block yes no (1) no (1) yes 1 2 refclk0 and refclk1 pins of other transceiver blocks on the same side of the device using the inter-transceiver block (itb) clock lines (2) yes yes yes yes 2 (4) 3 clock output from the left and right plls in the fpga fabric with voltage controlled oscillator (vco) bypass mode (3) yes yes no yes 3 4 clock output from the left and right plls in the fpga fabric yes yes no yes 4 5 dedicated clk input pins on the fpga global clock network yes yes no yes 4 notes to ta bl e 2? 2 : (1) atx plls do not have dedicated refclk pins. (2) for more information, refer to ?inter-transceiver block (itb) clock lines? on page 2?8 . (3) for more information, refer to ?configuration examples? on page 2?73 . (4) for better jitter performance, altera strongly recommends using the refclk0 and refclk1 pins of the transceiver block located immediately below the atx pll. (5) lowest number indicates best jitter performance. tab le 2 ?3 . input reference clock frequencies for the 10g atx pll clock data rate allowed divider values reference clock frequency 9.9 gbps to 11.3 gbps m = 16, n = 1 281.25 to 322 mhz m = 16, n = 2 562.5 to 706.25 mhz 2?4 chapter 2: stratix iv transceiver clocking input reference clocking stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?2 shows the input reference clock sources for cmu plls and receiver cdrs within a transceiver block. one global clock line is available for each cmu pll and receiver cdr in a transceiver block. this allows each cmu pll and receiver cdr to derive its input reference clock from a separate fpga clk input pin. figure 2?2. input reference clock sources in a transceiver block refclk0 refclk1 itb clock lines global clock line pll cascade clock itb clock lines global clock line pll cascade clock itb clock lines global clock line itb clock lines global clock line itb clock lines global clock line itb clock lines global clock line cdr 6 6 cdr 6 cmu0 pll cmu1 pll 6 6 cdr 6 cdr transceiver block channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 2 2 pll cascade clock pll cascade clock pll cascade clock pll cascade clock chapter 2: stratix iv transceiver clocking 2?5 input reference clocking ? march 2010 altera corporation stratix iv device handbook volume 2 figure 2?3 shows the input reference clock sources for cmu plls, atx plls, and receiver cdrs in four transceiver blocks on the right side of the ep4sgx530f45 device. in this figure, the input reference clock sources for four transceiver blocks are located only on the right side of the device but the ep4sgx530nf45 device has similar input reference clock resources available for the four transceiver blocks located on the left side of the device as well. figure 2?3 also shows the itb clock lines on the right side of the device. the number of itb clock lines available in any stratix iv gx device is equal to the number of refclk pins available in that device. figure 2?3. input reference clock sources across transceiver blocks to fpga fabric itb[7:0] 8 6 6 refclk0 refclk0 refclk1 2 2 refclk1 2 2 refclk0 2 2 refclk1 6 refclk0 2 6 refclk1 2 global clock line pll cascade clock transceiver block gxbr3 two cmu plls and four rx cdrs 6 transceiver block gxbr2 global clock line pll cascade clock 6 transceiver block gxbr1 global clock line pll cascade clock 6 transceiver block gxbr0 two cmu plls and four rx cdrs global clock line pll cascade clock 6 atx pll r1 (6g) 8 itb clock lines global clock line pll cascade clock atx pll r0 (6g) 8 itb clock lines global clock line pll cascade clock two cmu plls and four rx cdrs two cmu plls and four rx cdrs 2?6 chapter 2: stratix iv transceiver clocking input reference clocking stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?4 shows the input reference clock sources for cmu plls, atx plls, and receiver cdrs in four transceiver blocks on the right side of the ep4s100g5f45 device. in this figure, the input reference clock sources for four transceiver blocks are located only on the right side of the ep4s100g5f45 device but the device has similar input reference clock resources available for the four transceiver blocks located on the left side of the device as well. figure 2?4 also shows the itb clock lines on the right side of the ep4s100g5f45 device. the number of itb clock lines available in any stratix iv gt device is equal to the number of refclk pins available in that device. figure 2?4. input reference clock sources across transceiver blocks for stratix iv gt devices to fpga fabric itb[7:0] 8 6 6 refclk0 refclk0 refclk1 2 2 refclk1 2 2 refclk0 2 2 refclk1 6 refclk0 2 6 refclk1 2 global clock line pll cascade clock transceiver block gxbr3 two cmu plls and four rx cdrs 6 transceiver block gxbr2 global clock line pll cascade clock 6 transceiver block gxbr1 global clock line pll cascade clock 6 transceiver block gxbr0 two cmu plls and four rx cdrs global clock line pll cascade clock 6 atx pll r1 (6g) 8 itb clock lines atx pll r0 (6g) 8 itb clock lines global clock line pll cascade clock two cmu plls and four rx cdrs two cmu plls and four rx cdrs atx pll r2 (10g) 8 itb clock lines global clock line pll cascade clock chapter 2: stratix iv transceiver clocking 2?7 input reference clocking ? march 2010 altera corporation stratix iv device handbook volume 2 refclk0 and refclk1 pins each transceiver block has two dedicated refclk pins that you can use to drive the cmu pll, receiver cdr, or both, input reference clocks. each of the two cmu plls and four receiver cdrs within a transceiver block can derive its input reference clock from either the refclk0 or refclk1 pin. 1 the refclk pins provide the cleanest input reference clock path to the cmu/atx plls when compared with other input reference clock sources. altera recommends using the refclk pins to drive the cmu pll input reference clock for improved transmitter output jitter performance. table 2?4 lists the electrical specifications for the input reference clock signal driven on the refclk pins. f for specifications regarding the input frequency supported by the refclk pins, refer to the dc and switching characteristics chapter. 1 if you select the hcsl i/o standard for the pci express (pipe) reference clock, add the following assignment to your project .qsf : set_instance_assignment -name input_termination off -to 2?8 chapter 2: stratix iv transceiver clocking input reference clocking stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?5 shows an example termination scheme for a reference clock signal when configured as hcsl. inter-transceiver block (itb) clock lines the refclk0 and refclk1 pins of other transceiver blocks using the itb clock lines provide an input reference clock path from the refclk pins of one transceiver block to the cmu plls and receiver cdrs of the other transceiver blocks. in designs that have channels located in different transceiver blocks, the itb clock lines eliminate the need to connect the on-board reference clock crystal oscillator to the refclk pin of each transceiver block. the itb clock lines also drive the clock signal on the refclk pins to the clock logic in the fpga fabric. the itb clock lines also provide an input reference clock path from the refclk pins of any transceiver block to the atx plls located on the same side of the device. each refclk pin drives one itb clock line for a total of up to eight itb clock lines on each of the right and left sides of the device, as shown in figure 2?3 on page 2?5 . 1 the itb clock lines provide input reference clock paths from the refclk pins of one transceiver block to the cmu plls and receiver cdrs of other transceiver blocks located on the same side of the device. dedicated clk input pins on the fpga global clock network stratix iv devices provide up to 8 differential clock input pins located in non-transceiver i/o banks that you can use to provide up to eight input reference clocks to the transceiver blocks. the quartus ii software automatically chooses the global clock (gclk) network to route the input reference clock signal from the clk pins to the transceiver blocks. f for more information, refer to the ?dedicated clock input pins? section in the clock networks and plls in stratix iv devices chapter. one gclk resource is available for each cmu pll, 6g atx pll, and receiver cdr. this allows each cmu pll, 6g atx pll, and receiver cdr to derive its input reference clock from a separate fpga clk input pin. figure 2?5. termination scheme for a reference clock signal when configured as hcsl (note 1) notes to figure 2?5 : (1) no biasing is required if the reference clock signals are generated from a clock source that conforms to the pci express (pi pe) specification. (2) select resistor values as recommended by the pci express (pipe) clock source vendor. pci express (hcsl) refclk source refclk + refclk - stratix iv rs rs rp = 50 rp = 50 (2) (2) chapter 2: stratix iv transceiver clocking 2?9 fpga fabric plls-transceiver plls cascading ? march 2010 altera corporation stratix iv device handbook volume 2 clock output from left and right p lls in the f pga fabric you can use the synthesized clock output from one of the left or right plls to provide the input reference clock to the cmu plls, 6g atx plls, and receiver cdrs. stratix iv devices provide a dedicated clock path from the left plls ( pll_l1, pll_l2, pll_l3 , and pll_l4 ) in the fpga fabric to the pll cascade network located on the left side of the device. stratix iv devices also provide a dedicated clock path from the right plls ( pll_r1, pll_r2, pll_r3 , and pll_r4 ) in the fpga fabric to the pll cascade network located on the right side of the device. the additional clock multiplication factors available in the left and right plls allow more options for on-board crystal oscillator frequencies. fpga fabric plls-transceiver plls cascading the cmu pll synthesizes the input reference clock to generate the high-speed serial clock used in the transmitter pma. the receiver cdr synthesizes the input reference clock in lock-to-reference (ltr) mode to generate the high-speed serial clock. this high-speed serial clock output from the cmu pll and the receiver cdr runs at a frequency that is half the configured data rate. the cmu plls and receiver cdrs only support multiplication factors (m) of 2, 4, 5, 8, 10, 16, 20, and 25. if you use an on-board crystal oscillator to provide the input reference clock through the dedicated refclk pins or itb lines, the allowed crystal frequencies are limited by the cmu pll and the receiver cdr multiplication factors. the input reference clock frequencies are also limited by the allowed phase frequency detector (pfd) frequency range. example 1: channel configuration with 4-gbps data rate consider a channel configured for 4-gbps data rate. the high-speed serial clock output from the cmu pll and the receiver cdr must run at 2 gbps. table 2?5 lists the allowed input reference clock frequencies for example 1. for a 4-gbps data rate, the quartus ii software only allows an input reference clock frequency of 80, 100, 125, 160, 200, 250, 400, and 500 mhz. to overcome this limitation, stratix iv devices allow the synthesized clock output from the left and right plls in the fpga fabric to drive the cmu pll and receiver cdr input reference clock. the additional clock multiplication factors available in the left and right plls allow more options for on-board crystal oscillator frequencies. tab le 2 ?5 . allowed input reference clock frequency for example 1 multiplication factor (m) on-board crystal reference clock frequency (mhz) allowed with /n = 1 with /n = 2 2 1000 2000 no. violates the pfd frequency limit. 4 500 1000 no. violates the pfd frequency limit. 5 400 800 yes but only for /n = 1. 82 5 0 5 0 0 y e s 10 200 400 yes 16 125 250 yes 20 100 200 yes 25 80 160 yes 2?10 chapter 2: stratix iv transceiver clocking fpga fabric plls-transceiver plls cascading stratix iv device handbook volume 2 ? march 2010 altera corporation dedicated left and right pll cascade network stratix iv devices have a dedicated pll cascade network on the left and right side of the device that connects to the input reference clock selection multiplexer of the cmu plls, 6g atx plls, and receiver cdrs on the left and right side of the device, respectively. the dedicated pll cascade networks are segmented by bidirectional tri-state buffers located along the clock line. segmentation of the dedicated pll cascade network allows two or more left and right plls to drive the cascade clock line simultaneously. because the number of left and right plls and transceiver blocks vary from device to device, the capability of cascading a left and right pll to the cmu plls, 6g atx plls, and receiver cdrs also varies from device to device. the following sections describe the stratix iv gx and gt fpga fabric-transceiver plls cascading for the various device packages. chapter 2: stratix iv transceiver clocking 2?11 fpga fabric plls-transceiver plls cascading ? march 2010 altera corporation stratix iv device handbook volume 2 fpga fabric plls-transceiver plls cascading in the 780-pin package stratix iv gx devices in 780-pin packages do not support fpga fabric plls-transceiver plls cascading. fpga fabric plls-transceiver plls cascading in the 1152-pin package figure 2?6 shows the fpga fabric plls-transceiver plls cascading options allowed in the ep4sgx110ff35 device (red), the ep4sgx230ff35, ep4sgx290ff35 and ep4sgx360ff35 devices (blue), and the ep4sgx530hh35 device (black). figure 2?6. fpga fabric plls-transceiver plls cascading options allowed for 1152-pin package devices cdr cdr cdr cdr pll cascade network pll cascade network pll_l2 pll_r2 ep4sgx110ff35 transceiver block gxbl1 channel 3 channel 2 cdr cdr cmu1 pll cmu0 pll cdr cdr channel 1 channel 0 transceiver block gxbl0 cdr channel 3 cdr channel 2 cmu0 pll cmu1 pll channel 1 channel 0 cdr cdr cdr cdr cdr cdr channel 0 channel 1 channel 2 channel 3 cmu1 pll cmu0 pll transceiver block gxbr0 channel 0 channel 1 cmu0 pll cmu1 pll transceiver block gxbr1 channel 2 channel 3 atx pll l0 (6g) atx pll r0 (6g) ep4sgx230ff35 ep4sgx290ff35 ep4sgx360ff35 ep4sgx530hh35 2?12 chapter 2: stratix iv transceiver clocking fpga fabric plls-transceiver plls cascading stratix iv device handbook volume 2 ? march 2010 altera corporation fpga fabric plls-transceiver plls cascading in the 1517-pin package figure 2?7 shows the fpga fabric plls-transceiver plls cascading options allowed in the ep4sgx230kf40, ep4sgx290kf40, ep4sgx360kf40, and ep4sgx530kf40 devices. 1 for stratix iv gt devices, fpga fabric plls-transceiver plls cascading is not supported for the 10g atx plls. for the ep4s40g2kf40, ep4s40g5kf40, ep4s100g2kf40, and ep4s100g5kf40 devices, fpga fabric plls-transceiver plls cascading for the 6g atx plls and cmu plls is the same as the stratix iv gx devices in the 1517-pin package. figure 2?7. fpga fabric plls-transceiver plls cascading options allowed in the 1517-pin package devices note to figure 2?7 : (1) atx pll l1 and atx pll r1 are not present in the ep4sgx230kf40 device. cdr pll cascade network pll cascade network ep4sgx230kf40 ep4sgx290kf40 ep4sgx360kf40 ep4sgx530kf40 transceiver block gxbl2 channel 3 channel 2 channel 1 channel 0 cdr cdr cdr cdr cmu1 pll cmu0 pll transceiver block gxbl1 channel 2 channel 3 cmu0 pll cmu1 pll cdr cdr cdr cdr channel 1 channel 0 transceiver block gxbr1 channel 0 channel 1 channel 2 channel 3 cdr cdr cdr cmu1 pll cmu0 pll transceiver block gxbr2 channel 3 channel 2 channel 1 channel 0 cdr cdr cdr cdr cmu1 pll cmu0 pll pll_l2 pll_l3 transceiver block gxbl0 channel 3 channel 2 channel 1 channel 0 cdr cdr cdr cdr cmu1 pll cmu0 pll pll_r2 pll_r3 transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 cdr cdr cdr cdr cmu1 pll cmu0 pll atx pll l1 (6g) (1) atx pll l0 (6g) atx pll r0 (6g) atx pll r1 (6g) (1) chapter 2: stratix iv transceiver clocking 2?13 fpga fabric plls-transceiver plls cascading ? march 2010 altera corporation stratix iv device handbook volume 2 fpga fabric plls-transceiver plls cascading in the 1932-pin package figure 2?8 shows the fpga fabric plls-transceiver plls cascading options allowed in the ep4sgx530nf45, ep4sgx360nf45, and ep4sgx290nf45 devices. 1 for stratix iv gt devices, fpga fabric plls-transceiver plls cascading is not supported for the 10g atx plls. for the ep4s100g3nf45, ep4s100g4n45, and ep4s100g5nf45 devices, fpga fabric plls-transceiver plls cascading for the 6g atx plls and cmu plls is the same as the stratix iv gx devices in the 1932-pin package. figure 2?8. fpga fabric plls-transceiver plls cascading options allowed in the 1932-pin package device cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr channel 1 cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr channel 2 cdr cdr cdr cdr cdr cdr cdr cdr transceiver block gxbr0 transceiver block gxbl3 ep4sgx530nf45 ep4sgx360nf45 ep4sgx290nf45 pll cascade n etwork pll cascade n etwork pll_l1 channel 3 channel 1 channel 0 cmu1 pll cmu0 pll pll_l2 transceiver block gxbl2 channel 2 channel 3 cmu1 pll cmu0 pll channel 1 channel 0 pll_l3 transceiver block gxbl1 channel 2 channel 3 cmu1 pll cmu0 pll channel 1 channel 0 transceiver block gxbl0 channel 2 channel 3 cmu1 pll cmu0 pll pll_l4 channel 1 channel 0 pll_r4 channel 0 cmu1 pll cmu0 pll channel 3 channel 2 transceiver block gxbr1 cmu1 pll cmu0 pll channel 3 channel 2 channel 1 channel 0 pll_r2 pll_r3 transceiver block gxbr2 channel 3 channel 2 channel 1 channel 0 cmu1 pll cmu0 pll channel 1 channel 0 cmu1 pll cmu0 pll transceiver block gxbr3 channel 3 channel 2 pll_r1 atx pll l0 (6g) atx pll l1 (6g) atx pll r0 (6g) atx pll r1 (6g) 2?14 chapter 2: stratix iv transceiver clocking fpga fabric plls-transceiver plls cascading stratix iv device handbook volume 2 ? march 2010 altera corporation fpga fabric plls-transceiver plls cascading rules you can only cascade the left plls ( pll_l1, pll_l2, pll_l3 , and pll_l4 ) to the transceiver blocks located on the left side of the device. similarly, you can only cascade the right plls ( pll_r1, pll_r2, pll_r3 , and pll_r4 ) to the transceiver blocks located on the right side of the device. the pll cascade networks are single clock lines segmented by bidirectional tri-state buffers located along the clock line. segmentation of the pll cascade network allows two left and right plls to drive the cascade clock line simultaneously and provides the input reference clock to the cmu plls and receiver cdrs in different transceiver blocks. when cascading two or more fpga fabric plls to the cmu plls and receiver cdrs, there must be no crossover in the cascaded clock paths on the pll cascade network ( figure 2?9 ). 1 for better noise rejection, ensure the bandwidth setting of the fpga fabric pll (the upstream pll) is lower than the transceiver pll (the downstream pll). example 2: design target?ep4sgx530nf45 device if your design is targeted for a ep4sgx530nf45 device, it requires providing input reference clocks to the following cmu plls and receiver cdrs from two right plls in the fpga fabric: cmu0 pll in transceiver block gxbr1 receiver cdrs in channel 2 and channel 3 in transceiver block gxbr1 case 1: use pll_r4 to provide the input reference clock to the receiver cdrs in channel 2 and channel 3 (shown in green) and use pll_r1 to provide the input reference clock to the cmu0 pll (shown in blue) in transceiver block gxbr1. chapter 2: stratix iv transceiver clocking 2?15 fpga fabric plls-transceiver plls cascading ? march 2010 altera corporation stratix iv device handbook volume 2 figure 2?9 shows that this fpga fabric-transceiver pll cascading configuration is illegal due to crossover (shown in red) of the cascade clock paths on the pll cascade network. figure 2?9. illegal fpga fabric-transceiver pll cascading configuration cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr ep4sgx530nf45 pll cascade network pll cascade network pll_l1 pll_r1 transceiver block gxbl3 channel 3 channel 2 channel 1 channel 0 cmu1 pll cmu0 pll transceiver block gxbl2 channel 3 channel 2 cmu1 pll cmu0 pll channel 1 channel 0 transceiver block gxbl1 channel 3 channel 2 pll_l2 pll_l3 channel 1 channel 0 cmu1 pll cmu0 pll transceiver block gxbl0 channel 3 channel 2 cmu1 pll cmu0 pll channel 1 channel 0 pll_l4 transceiver block gxbr0 pll_r4 channel 3 channel 2 channel 1 channel 0 cmu1 pll cmu0 pll transceiver block gxbr1 channel 3 channel 2 channel 1 channel 0 cmu1 pll cmu0 pll pll_r3 transceiver block gxbr2 pll_r2 cmu1 pll cmu0 pll transceiver block gxbr3 channel 3 channel 2 channel 3 channel 2 channel 1 channel 0 channel 1 channel 0 cmu1 pll cmu0 pll atx pll l0 (6g) atx pll l1 (6g) atx pll r0 (6g) atx pll r1 (6g) x 2?16 chapter 2: stratix iv transceiver clocking fpga fabric plls-transceiver plls cascading stratix iv device handbook volume 2 ? march 2010 altera corporation case 2: use pll_r1 to provide the input reference clock to the receiver cdrs in channel 2 and channel 3 (shown in blue) and use pll_r4 to provide the input reference clock to the cmu0 pll (shown in green) in transceiver block gxbr1. figure 2?10 shows that this fpga fabric-transceiver pll cascading configuration is legal as there is no crossover of the cascade clock paths on the pll cascade network. figure 2?10. legal fpga fabric-transceiver pll cascading configuration cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr cdr ep4sgx530nf45 pll cascade network pll cascade network pll_l1 transceiver block gxbl3 channel 3 channel 2 cmu1 pll cmu0 pll transceiver block gxbl2 channel 3 channel 2 channel 1 channel 0 channel 1 channel 0 cmu1 pll cmu0 pll pll_l2 pll_l3 transceiver block gxbl1 channel 3 channel 2 channel 1 channel 0 cmu1 pll cmu0 pll transceiver block gxbl0 channel 3 channel 2 channel 1 channel 0 cmu1 pll cmu0 pll pll_l4 pll_r4 transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 cmu1 pll cmu0 pll transceiver block gxbr1 channel 3 channel 2 channel 1 channel 0 cmu1 pll cmu0 pll pll_r3 pll_r2 transceiver block gxbr2 channel 1 channel 0 channel 3 channel 2 transceiver block gxbr2 pll_r1 channel 3 channel 2 channel 1 channel 0 cmu1 pll cmu0 pll cmu1 pll cmu0 pll atx pll l0 (6g) atx pll l1 (6g) atx pll r0 (6g) atx pll r1 (6g) chapter 2: stratix iv transceiver clocking 2?17 fpga fabric plls-transceiver plls cascading ? march 2010 altera corporation stratix iv device handbook volume 2 left and right, left, or right pll in vco bypass mode if all cmu channels on the same side of the device are configured as channels, all refclk pins are used as receiver serial input data pins. all cmu plls are also used as receiver cdrs. in such designs, you must use the 6g atx plls to generate the high-speed serial and low-speed parallel transceiver clocks provided that the configured data rate is supported by the 6g atx plls. additionally, altera recommends providing the input reference clock to the 6g atx pll using the left or right pll cascade clock line because none of the refclk pins are available. to avoid jitter amplification because of cascading of the left or right pll to the 6g atx pll, you must place the left or right pll in vco bypass mode. f for more information about cmu plls, refer to ?configuring cmu channels as transceiver channels? in the stratix iv transceiver architecture chapter. figure 2?11 shows that in vco bypass mode, the input reference clock from the dedicated fpga clk pins to the inclk port of the left and right, left, or right pll bypasses the pll loop and is driven directly on the pll output clock port. figure 2?11. left and right, left, or right pll in vco bypass mode /n /m left and right pll reference clock from the dedicated clk pin phase fre quency detector charge pump + loop filter v oltage controlled oscillator c1 inpu t reference clock to the 6g atx pll 2?18 chapter 2: stratix iv transceiver clocking fpga fabric plls-transceiver plls cascading stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?12 shows 24 channels on the right side of the ep4sgx530nf45 device configured in basic (pma direct) n mode running at 6.5 gbps with a 20-bit fpga fabric-pma interface width. because all 24 channels on the right side of the device are configured in basic (pma direct) n mode, use the right pll_r1 configured in vco bypass mode to provide the input reference clock to the 6g atx pll. because the data rate of 6.5 gbps requires a left and right, left, or right pll to meet fpga fabric-transmitter pma interface timing, the tx_clkout from one of the 24 channels is phase shifted using pll_r2 . use the phase-shifted output clock from pll_r2 to clock the fpga fabric logic that generates the transmitter parallel data and control signals. chapter 2: stratix iv transceiver clocking 2?19 fpga fabric plls-transceiver plls cascading ? march 2010 altera corporation stratix iv device handbook volume 2 for more information about configuring left or right plls in vco bypass mode, refer to ?configuration example 4: configuring left and right, left, or right pll in vco bypass mode? on page 2?78 . figure 2?12. input reference clocking using left and right, left, or right pll in vco bypass mode (note 3) notes to figure 2?12 : (1) for more information, refer to ?transceiver channel datapath clocking? on page 2?20 . (2) for more information, refer to an 580: achieving timing closure in basic (pma direct) functional mode . (3) the green line represents the pll cascade clock line and the blue lines represent 6g atx pll r1. channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 atx pll block r1 (6g) channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 atx pll block r1 (6g) channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 xn_bottom (1) xn_top (1) transceiver block gxbr0 transceiver block gxbr1 transceiver block gxbr 2 channel 3 channel 2 cmu1 channel channel 1 channel 0 transceiver block gxbr 3 pll_r1 (vco bypass mode) pll_r2 (phase shift 45o to meet interface timing) dedicated fpga clk pin pll cascade clock line reference clock tx_clkout fpga fabric (transmitter data generation logic) fpga fabric (transmitter data generation logic) cmu0 channel (2) 2?20 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation transceiver channel datapath clocking this section describes the transmitter channel and receiver channel datapath clocking in various configurations. datapath clocking varies with physical coding sublayer (pcs) configurations in different functional modes as well as channel bonding options. this section contains: ?transmitter channel datapath clocking? on page 2?20 ?receiver channel datapath clocking? on page 2?38 1 clocking described in this section is internal to the transceiver and clock routing is primarily performed by the quartus ii software. f for more information about manually picking and placing cmu and atx plls, refer to an 578: manual placement of cmu plls and atx plls in stratix iv gx and gt devices . transmitter channel datapath clocking this section describes the transmitter channel pma and pcs datapath clocking in non-bonded and bonded channel configurations: ?non-bonded channel configurations? on page 2?24 ?bonded channel configurations? on page 2?27 ?non-bonded basic (pma direct) mode channel configurations? on page 2?33 ?bonded basic (pma direct) n mode channel configurations? on page 2?35 chapter 2: stratix iv transceiver clocking 2?21 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 transmitter channel-to-channel skew optimization for modes other than basic (pma direct) mode high-speed serial clock and low-speed parallel clock skew between channels and unequal latency in the transmitter phase compensation fifo contribute to transmitter channel-to-channel skew. transmitter datapath clocking is set up to provide low channel-to-channel skew when compared with non-bonded channel configurations. in bonded channel configurations?the high-speed serial clock and low-speed parallel clock for all bonded channels are generated by the cmu0 clock divider or the atx clock divider block, resulting in lower channel-to-channel clock skew. the transmitter phase compensation fifo in all bonded channels (except in basic [pma direct] n mode) share common pointers and control logic generated in the central control unit (ccu), resulting in equal latency in the transmitter phase compensation fifo of all bonded channels. the lower transceiver clock skew and equal latency in the transmitter phase compensation fifos in all channels provides lower channel-to-channel skew in bonded channel configurations. in non-bonded channel configurations?the high-speed serial clock and low-speed parallel clock in each channel are generated independently by its local clock divider. this results in higher channel-to-channel clock skew. the transmitter phase compensation fifo in each non-bonded channel (except in basic [pma direct] mode) has its own pointers and control logic that can result in unequal latency in the transmitter phase compensation fifo of each channel. the higher transceiver clock skew and unequal latency in the transmitter phase compensation fifo in each channel can result in higher channel-to-channel skew. transmitter channel datapath clocking resources the stratix iv transceivers support various non-bonded and bonded transceiver clocking configurations through the dedicated 1, 4, and n high-speed serial and low-speed parallel clock lines. 2?22 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?13 shows the transceiver clock distribution in 1, 4, 8, and n bonded modes. figure 2?13. transceiver clock distribution in the stratix iv gt ep4s100g5f45 and stratix iv gx ep4sgx530kf40 devices note to tab l e 2 ?1 4 : (1) the 10g atx pll block is not available for the ep4sgx530kf40 device. transcei v er block gxbr3 channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel atx pll block (10g) (1) transcei v er block gxbr2 channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel atx pll block (6g) transcei v er block gxbr1 channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel atx pll block (6g) transcei v er block gxbr0 channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel xn_top x1 cmu1 gxbr3 x4 gxbr3 xn_bottom x1 cmu0 gxbr3 x1 cmu1 gxbr2 x1 cmu0 gxbr2 x4 gxbr2 x4 gxbr1 x4 gxbr0 x1 cmu0 gxbr1 x1 cmu1 gxbr1 x1 cmu1 gxbr0 x1 cmu0 gxbr0 chapter 2: stratix iv transceiver clocking 2?23 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 non-bonded and bonded configurations use the following: 1 non-bonded configurations use the 1 clock lines to distribute only the high-speed serial transceiver clock synthesized by the cmu0 pll or cmu1 pll to the clock transmitter channels located in the same transceiver block. the low-speed parallel transceiver clock is generated in the transceiver channels using the local clock dividers. 4 bonded configurations use the 4_gxb clock lines to distribute both the high-speed serial and low-speed parallel transceiver clocks generated by the cmu0_channel to clock the bonded transmitter channels located in the same transceiver block. 8 and n bonded configurations use the n_top or n_bottom clock lines to distribute both the high-speed serial and low-speed parallel transceiver clocks generated by the cmu0 channel block to all bonded transmitter channels located across transceiver blocks. atx plls always use n lines to distribute the high-speed serial and low-speed parallel transceiver clocks. use the n_top line if the cmu0 pll or atx pll that generates the transceiver clocks is located at the top of the transmitter channel. use the n_bottom line if the cmu0 pll or atx pll is located at the bottom of the transmitter channel. because there is only one n_top and n_bottom line on each side of the device, using an atx pll limits the use of the n clock lines to distribute the transceiver clocks to other transmitter channels in the design. transmitter channel clocking configurations figure 2?14 shows various transmitter channel clocking configurations. transmitter channels configured in modes other than basic (pma direct) mode use both the transmitter channel pcs and pma blocks. as a result, stratix iv devices allow placing these transmitter channels only in the four regular channels of a transceiver block. stratix iv devices do not allow configuring the cmu channels in any mode other than basic (pma direct) mode because of the absence of pcs blocks in the cmu channels. figure 2?14. transmitter channel clocking configurations transmitter channel clocking configu rations non-bonded basic (pma direct) bonded basic (pma direct) xn non-bonded bonded x4 bonded x8 bonded 2?24 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation the transmitter channel datapath clocking in modes other than basic (pma direct) mode depends on whether the transmitter channel is configured in non-bonded or bonded mode. non-bonded channel configurations the following modes other than basic (pma direct) functional mode have a non-bonded transmitter channel configuration: pci express (pipe) 1?gen1 and gen2 gigabit ethernet (gige) serial rapidio sonet/sdh sdi (oif) cei phy interface basic (except basic 4 and basic 8 modes) deterministic latency use the cmu channels to generate transceiver clocks for all the non-bonded functional modes listed above. additionally, use the atx plls to generate transceiver clocks for pci express (pipe) 1 gen 2, (oif) cei phy, and basic functional mode. f for data rates supported by atx plls, refer to the ?auxiliary transmit (atx) pll block? section in the stratix iv transceiver architecture chapter. chapter 2: stratix iv transceiver clocking 2?25 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 figure 2?15 shows transmitter channel datapath clocking in non-bonded channel configurations when clocked using the cmu plls. figure 2?15. transmitter datapath clocking in a non-bonded configuration clocked by cmu pll (note 1) note to figure 2?15 : (1) the red lines represent the fpga fabric-transceiver interface clock, the green lines represent the low-speed parallel clock, and the blue lines represent the 1 high-speed serial clock. fpga fabric transmitter channel pcs transmitter channel pma / 2 transmitter channel pcs transmitter channel pma / 2 wrclk wrclk rdclk rdclk transmitter channel pcs transmitter channel pma / 2 wrclk wrclk rdclk rdclk serializer transmitter channel pcs transmitter channel pma / 2 wrclk wrclk rdclk rdclk pci express hard ip pipe interface tx phase compensation fifo wrclk rdclk byte serializer wrclk rdclk channel 3 serializer x1 high-speed serial cloc k local clock divider block low-speed parallel clock tx_clkout[3] fpga fabric-transciever interface clock tx_coreclk[3] pci express hard ip pipe interface tx phase compensation fifo byte serializer channel 2 serializer x1 high-speed serial clock local clock divider block low-speed parallel clock tx_clkout[2] fpga fabric-transciever interface clock tx_coreclk[2] pci express hard ip pipe interface input reference clock cmu1 pll cmu1 clock divider cmu1 channel cmu0 channel cmu0 clock divider cmu0 pll input reference clock tx phase compensation fifo byte serializer channel 1 serializer x1 high-speed serial clock local clock divider block low-speed parallel clock tx_clkout[1] fpga fabric-transceiver interface clock tx_coreclk[1] pci express hard ip pipe interface tx phase compensation fifo byte serializer channel 0 8b/10b encoder x1 high-speed serial clock local clock divider block low-speed parallel clock tx_clkout[0] fpga fabric-transceiver interface clock tx_coreclk[0] 8b/10b encoder 8b/10b encoder 8b/10b encoder 2?26 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation in non-bonded channel configurations clocked by cmu pll, each channel can derive its clock independently from either cmu0 pll or cmu1 pll within the same transceiver block. the cmu pll synthesizes the input reference clock to generate a clock that is distributed to the local clock divider block in each channel using the 1 high-speed serial clock line. depending on the configured functional mode, the local clock divider block in each channel generates the low-speed parallel clock and high-speed serial clock. the serializer in the transmitter channel pma uses both the low-speed parallel clock and high-speed serial clock for its parallel-in-serial-out operation. the low-speed parallel clock clocks the 8b/10b encoder (if enabled) and the write port of the byte serializer (if enabled) in the transmitter channel pcs. depending on whether you use the byte serializer or not, the low-speed parallel clock (when you do not use the byte serializer) or a divide-by-two version of the low-speed parallel clock (when you use the byte serializer) from the cmu0 clock divider block clocks the read port of the transmitter phase compensation fifo in all four bonded channels. this clock is driven directly on the tx_clkout port as the fpga fabric-transceiver interface clock. you can use the coreclkout signal to clock the transmitter data and control logic in the fpga fabric for all four bonded channels. 1 if you configure the atx pll to clock the transmitter channel, the atx pll block drives the high-speed serial clock and low-speed parallel clock to the transmitter channel on the n_top or n_bottom lines. f for more information, refer to the configuring multiple protocols and data rates in a transceiver block chapter. table 2?2 lists the transmitter channel datapath clock frequencies in non-bonded functional modes that have a fixed data rate. tab le 2 ?6 . transmitter channel datapath clock frequencies in non-bonded functional modes functional mode data rate high-speed serial clock frequency low-speed parallel clock frequency (mhz) fpga fabric-transceiver interface clock frequency without byte serializer (mhz) with byte serializer (mhz) pci express (pipe) 1 (gen 1) 2.5 gbps 1.25 ghz 250 250 125 pci express (pipe) 1 (gen 2) 5 gbps 2.5 ghz 500 n/a 250 gige 1.25 gbps 625 mhz 125 125 n/a serial rapidio 1.25 gbps 625 mhz 125 n/a 62.5 2.5 gbps 1.25 ghz 250 n/a 125 3.125 gbps 1.5625 ghz 312.5 n/a 156.25 sonet/sdh oc12 622 mbps 311 mhz 77.75 77.75 n/a sonet/sdh oc48 2.488 gbps 1.244 ghz 311 n/a 155.5 hd-sdi 1.485 gbps 742.5 mhz 148.5 148.5 74.25 1.4835 gbps 741.75 mhz 148.35 148.35 74.175 3g-sdi 2.97 gbps 1.485 ghz 297 n/a 148.5 2.967 gbps 1.4835 ghz 296.7 n/a 148.35 chapter 2: stratix iv transceiver clocking 2?27 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 bonded channel configurations in pcs and pma bonded channel configurations, the pcs and pma blocks of all bonded channels are clocked by the same low-speed parallel clock and high-speed serial clock from the cmu0 clock divider or the atx pll block. the phase compensation fifos of all bonded channels also share common read and write pointers and enable signals generated in the ccu. stratix iv devices support 4 pcs and pma channel bonding that allows bonding of four channels within the same transceiver block. stratix iv devices also support 8 channel bonding that allows bonding of eight pcs and pma channels across two transceiver blocks on the same side of the device. 4 pcs and pma bonded channel configuration the following functional modes support 4 pcs and pma bonded transmitter channel configuration: pci express (pipe) 4?gen1 and gen2 xaui basic 4 use the cmu channels to generate the transceiver clocks for all 4 bonded functional modes listed above. additionally, use the atx plls to generate the transceiver clocks for pci express (pipe) 4 gen 2 and basic 4 functional mode. 1 you must assign tx_dataout[0] of the 4 bonded link (xaui or pci express [pipe] 4) to physical channel 0 of the transceiver block, tx_dataout[1] to physical channel 1 of the transceiver block, tx_dataout[2] to physical channel 2 of the transceiver block, and tx_dataout[3] to physical channel 3 of the transceiver block. otherwise, the quartus ii compilation errors out. 2?28 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?16 shows the transmitter channel datapath clocking in 4 channel bonding configurations when clocked using the cmu0 channel. figure 2?16. transmitter datapath clocking in x4 bonded configurations (note 1) note to figure 2?16 : (1) the red lines represent the fpga fabric-transceiver interface clock, the green lines represent the low-speed parallel clock, and the blue lines represent the high-speed serial clock. serializer transmitter channel pcs transmitter channel pma / 2 wrclk wrclk rdclk rdclk serializer transmitter channel pcs transmitter channel pma / 2 wrclk wrclk rdclk rdclk serializer transmitter channel pcs transmitter channel pma /2 wrclk wrclk rdclk rdclk serializer transmitter channel pcs transmitter channel pma / 2 wrclk wrclk rdclk rdclk channel 1 / 2 pci express hard ip pipe interface tx phase compensation fifo byte serializer channel 3 x4 high-speed serial clock x4 low-speed parallel clock tx_coreclk[3] pci express hard ip pipe interface tx phase compensation fifo byte serializer channel 2 x4 high-speed serial clock x4 low-speed parallel clock tx_coreclk[2] coreclkout fpga fabric-transceiver interface clock input reference clock cmu1 pll cmu1 channel cmu0 channel x4 low-speed parallel clock x4 high-speed serial clock cmu0 clock divider cmu0 pll input reference clock fpga fabric pci express hard ip pipe interface tx phase compensation fifo byte serializer x4 high-speed serial clock x4 high-speed serial clock x4 low-speed parallel clock byte serializer tx phase compensation fifo pipe interface pci express hard ip tx_coreclk[0] tx_coreclk[1] x4 low-speed parallel clock channel 0 8b/10b encoder 8b/10b encoder 8b/10b encoder 8b/10b encoder fpga fabric-transceiver interface clock fpga fabric-transceiver interface clock fpga fabric-transceiver interface clock chapter 2: stratix iv transceiver clocking 2?29 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 the transceiver clocks are distributed to the four bonded channels on the 4 high-speed serial and 4 low-speed parallel clock lines. the serializer in the transmitter channel pma of the four bonded channels uses the same low-speed parallel clock and high-speed serial clock from cmu0 channel for their parallel-in-serial-out operation. the low-speed parallel clock clocks the 8b/10b encoder and the write port of the byte serializer (if enabled) in the transmitter channel pcs. depending on whether the you use the byte serializer or not, the low-speed parallel clock (when you do not use the byte serializer) or a divide-by-two version of the low-speed parallel clock (when you use the byte serializer) from the cmu0 clock divider block clocks the read port of the transmitter phase compensation fifo in all four bonded channels. this clock is driven directly on the coreclkout port as the fpga fabric-transceiver interface clock. you can use the coreclkout signal to clock the transmitter data and control logic in the fpga fabric for all four bonded channels. 1 the atx pll block drives the high-speed serial clock and low-speed parallel clock to the transmitter channels on the n_top or n_bottom lines. f for more information, refer to the configuring multiple protocols and data rates in a transceiver block chapter. in 4 pcs and pma bonded channel configurations, the transmitter phase compensation fifos in all four bonded channels share common read and write pointers and enable signals generated in the cmu0 channel of the transceiver block. this ensures equal transmitter phase compensation fifo latency across all four bonded channels, resulting in low transmitter channel-to-channel skew. table 2?3 lists the transmitter datapath clock frequencies in 4 bonded functional modes that have a fixed data rate. 8 pcs and pma bonded channel configuration the following functional modes support 8 pcs and pma bonded transmitter channel configuration: pci express (pipe) 8?gen1 and gen2 basic 8 tab le 2 ?7 . transmitter datapath clock frequencies in 4 bonded functional modes functional mode data rate high-speed serial clock frequency low-speed parallel clock frequency (mhz) fpga fabric-transceiver interface clock frequency without byte serializer (mhz) with byte serializer (mhz) pci express (pipe) 4 (gen 1) 2.5 gbps 1.25 ghz 250 250 125 pci express (pipe) 4 (gen 2) 5 gbps 2.5 ghz 500 n/a 250 xaui 3.125 gbps 1.5625 ghz 312.5 n/a 156.25 2?30 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation use the cmu channels to generate the transceiver clocks for all 8 pcs and pma bonded functional modes listed above. additionally, use the atx plls to generate the transceiver clocks for pci express (pipe) 8 gen 2 and basic 8 functional modes. the eight bonded channels are located in two transceiver blocks, referred to as the master transceiver block and the slave transceiver block, with four channels each. when clocked using a cmu pll, the cmu0 clock divider in cmu0 channel of the master transceiver block drives the high-speed serial clock and low-speed parallel clock on the xn_top clock line. the serializer in the transmitter channel pma of all eight bonded channels uses the same low-speed parallel clock and high-speed serial clock driven by the cmu0 channel of the master transceiver block on the xn_top clock line. the low-speed parallel clock from cmu0 channel of the master transceiver block clocks the 8b/10b encoder and the write port of the byte serializer (if enabled) in the transmitter channel pcs of all eight channels. depending on whether you use the byte serializer or not, the low-speed parallel clock (when you do not use the byte serializer) or a divide-by-two version of the low-speed parallel clock (when you use the byte serializer) from the cmu0 clock divider block clocks the read port of the transmitter phase compensation fifo in all eight bonded channels. this clock is driven directly on the coreclkout port as the fpga fabric-transceiver interface clock. you can use the coreclkout signal to clock the transmitter data and control logic in the fpga fabric for all eight bonded channels. 1 if you choose the atx pll to generate the transceiver clocks for the 8 bonded channels, altera recommends placing the atx pll between the master and slave transceiver block to minimize transmitter channel-to-channel skew. in this configuration, the atx pll block drives the high-speed serial clock and low-speed parallel clock to the master transceiver block on the n_bottom lines. it drives the high-speed serial clock and low-speed parallel clock to the slave transceiver block on the n_top lines. f for more information, refer to the configuring multiple protocols and data rates in a transceiver block chapter. in pci express (pipe) 8 and basic 8 bonded channel configurations, the transmitter phase compensation fifos in all eight bonded channels share common read and write pointers and enable signals generated in the central control unit of the master transceiver block. this ensures equal transmitter phase compensation fifo latency across all eight bonded channels, resulting in low transmitter channel-to-channel skew. 1 the difference in clock routing delays between the 4 clock lines and the n clock lines can result in higher transmitter channel-to-channel skew. to compensate for this difference in clock routing delays between the 4 and the n clock lines, the stratix iv transceivers introduce a fixed amount of delay in the 4 clock lines of the transceiver block whose cmu0 channel generates the transceiver clocks in basic 8 bonded channel configuration. chapter 2: stratix iv transceiver clocking 2?31 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 figure 2?17 shows the transmitter datapath clocking in pci express (pipe) 8 channel bonding configurations when clocked using the cmu channel in the master transceiver block. figure 2?18 through figure 2?20 show the allowed master and slave transceiver block locations and pci express (pipe) logical lane to physical transceiver channel mapping in all stratix iv devices. 1 the quartus ii compilation errors out if you do not map the pci express (pipe) logical lanes to the physical transceiver channels, as shown in figure 2?18 through figure 2?20 . figure 2?17. transmitter datapath clocking in x8 bonded configuration (note 1) note to figure 2?17 : (1) the red lines represent the fpga fabric-transceiver interface clock, the green lines represent the low-speed parallel clock, and the blue lines represent the high-speed serial clock. pipe interface transmitter channel pcs /2 wrclk wrclk rdclk rdclk cmu0 clock divider /2 transmitter channel pcs transmitter channel pma /2 wrclk wrclk rdclk rdclk master transceiver block slave transceiver block pci express hard ip pipe interface tx phase compensation fifo byte serializer serializer low-speed parallel clock from cmu0 of the master transceiver block tx_coreclk[7:4] cmu1 pll cmu1 clock divider cmu1 channel cmu0 channel cmu0 clock divider cmu0 pll fpga fabric pci express hard ip tx phase compensation fifo byte serializer serializer tx_coreclk[3:0] coreclkout fpga fabric-transceiver interface clock input reference clock cmu1 pll cmu1 channel cmu0 channel cmu1 clock divider low-speed parallel clock high-speed serial clock cmu0 pll input reference clock transmitter channel pma 8b/10b encoder 8b/10b encoder low-speed parallel clock from cmu0 of the master transceiver block fpga fabric-transceiver interface clock 2?32 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?18 shows one pci express (pipe) 8 link in two transceiver block devices and two pci express (pipe) 8 links in four transceiver block devices. figure 2?19 shows two pci express (pipe) 8 links in six transceiver block devices. figure 2?18. one pci express (pipe) x8 link in two transceiver block devices and two pci express (pipe) x8 links in four transceiver block devices ep4sgx290fh29, ep4sgx360fh29, ep4sgx110ff35, ep4sgx230ff35, ep4sgx290ff35, ep4sgx360ff35, ep4sgx230hf35, ep4sgx290hf35, ep4sgx360hf35, ep4sgx530hh35 pci express lane 7 pci express lane 6 pci express lane 5 pci express lane 4 pci express lane 3 pci express lane 2 pci express lane 1 pci express lane 0 transceiver block gxbl1 (slave) channel3 channel2 channel1 channel0 transceiver block gxbl0 (master) second pci express (pipe) x8 link first pci express (pipe) x8 link transceiver block gxbr1 (slave) transceiver block gxbr0 (master) channel3 channel2 channel1 channel0 channel3 channel2 channel1 channel0 channel3 channel2 channel1 channel0 pci express lane 7 pci express lane 6 pci express lane 5 pci express lane 4 pci express lane 3 pci express lane 2 pci express lane 1 pci express lane 0 ep4sgx70df29 ep4sgx110df29 ep4sgx230df29 two pci express (pipe) x8 links in four transceiver block devices one pci express (pipe) x8 link in two transceiver block devices figure 2?19. two pci express (pipe) 8 links in six transceiver block devices (note 1) note to figure 2?19 : (1) stratix iv devices with six transceiver blocks allow a maximum of two pci express (pipe) 8 links occupying four transceiver blocks. you can configure the other two transceiver blocks to implement other functional modes. ep4sgx230kf40, ep4sgx290kf40, ep4sgx360kf40, ep4sgx530kf40 transceiver block gxbl2 channel3 channel2 channel1 channel0 transceiver block gxbl1 (slave) channel3 channel2 channel1 channel0 second pci express (pipe) x8 link transceiver block gxbl0(master) channel3 channel2 channel1 channel0 pci express lane 7 pci express lane 6 pci express lane 5 pci express lane 4 pci express lane 3 pci express lane 2 pci express lane 1 pci express lane 0 first pci express (pipe) x8 link channel3 channel2 channel1 channel0 channel3 channel2 channel1 channel0 channel3 channel2 channel1 channel0 pci express lane 7 pci express lane 6 pci express lane 5 pci express lane 4 pci express lane 3 pci express lane 2 pci express lane 1 pci express lane 0 transceiver block gxbr2 transceiver block gxbr1 (slave) transceiver block gxbr0 (master) chapter 2: stratix iv transceiver clocking 2?33 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 figure 2?20 shows four pci express (pipe) 8 links in eight transceiver block devices. non-bonded basic (pma direct) mode channel configurations figure 2?21 shows four regular channels and the cmu1 channel in a transceiver block configured in non-bonded basic (pma direct) mode. each channel derives its clock independently from either the cmu0 pll or cmu1 pll within the same transceiver block if the cmu channel is configured as a cmu pll. f for more information about basic (pma direct) mode, refer to the stratix iv transceiver architecture chapter. figure 2?20. four pci express (pipe) 8 links in eight transceiver block devices ep4sgx530nf45 transceiver block gxbl3 (slave) pci express lane 7 pci express lane 6 pci express lane 5 pci express lane 4 pci express lane 3 pci express lane 2 pci express lane 1 pci express lane 0 channel3 channel2 channel1 channel0 fourth pci express (pipe) x8 link transceiver block gxbl2 (master) channel3 channel2 channel1 channel0 third pci express (pipe) x8 link pci express lane 7 pci express lane 6 pci express lane 5 pci express lane 4 pci express lane 3 pci express lane 2 pci express lane 1 pci express lane 0 transceiver block gxbl1 (slave) transceiver block gxbl0 (master) channel3 channel2 channel1 channel0 channel3 channel2 channel1 channel0 first pci express (pipe) x8 link second pci express (pipe) x8 link pci express lane 7 pci express lane 6 pci express lane 5 pci express lane 4 pci express lane 3 pci express lane 2 pci express lane 1 pci express lane 0 pci express lane 7 pci express lane 6 pci express lane 5 pci express lane 4 pci express lane 3 pci express lane 2 pci express lane 1 pci express lane 0 transceiver block gxbr3 (slave) transceiver block gxbr2 (master) transceiver block gxbr1 (slave) transceiver block gxbr0 (master) channel3 channel2 channel1 channel0 channel3 channel2 channel1 channel0 channel3 channel2 channel1 channel0 channel3 channel2 channel1 channel0 2?34 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation 1 stratix iv devices do not allow the 6g atx pll to generate transceiver clocks in non-bonded basic (pma direct) mode. the transmitter clock for channels configured in non-bonded basic (pma direct) mode must be generated by one of the cmu plls in the transceiver block containing the channels. figure 2?21. transmitter channel pma directly interfacing to the user logic in the fpga fabric (note 1) note to figure 2?21 : (1) the green lines represent the low-speed parallel clock and the blue lines represent the high-speed serial clock. fpga fabric serializer transmitter channel pcs transmitter channel pma local clock divider block tx_clkout[3] serializer local clock divider block serializer transmitter channel pcs local clock divider block serializer local clock divider block cmu0_pll channel 3 channel 2 channel 1 channel 0 transmitter channel pcs tx_clkout[2] tx_clkout[1] transmitter channel pcs tx_clkout[0] serializer lo w -speed parallel clock lo w -speed parallel clock x1 high-speed serial clock transmitter channel pma x1 high-speed serial clock transmitter channel pma cmu0_channel lo w -speed parallel clock transmitter channel pcs transmitter channel pcs lo w -speed parallel clock transmitter channel pma transmitter channel pma x1 high-speed serial clock x1 high-speed serial clock cmu1_channel cmu1 clock divider cmu0 clock divider chapter 2: stratix iv transceiver clocking 2?35 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 the cmu0 pll synthesizes the input reference clock to generate a clock that is distributed to the local clock divider block in each of the four regular channels using the 1 high-speed serial clock line. it is also forwarded to the cmu1 clock divider in the cmu1 channel configured as a non-bonded basic (pma-direct) channel. the local clock divider block in each regular channel and the cmu1 clock divider in the cmu1 channel generate the low-speed parallel clock and high-speed serial clock. the serializer in the transmitter channel pma of each channel uses both the low-speed parallel clock and high-speed serial clock for its parallel-in-serial-out operation. the low-speed parallel clock is also driven directly on the tx_clkout port as the fpga fabric-transceiver interface clock. you can use the tx_clkout port to clock transmitter data and control logic in the fpga fabric. bonded basic (pma direct) n mode channel configurations bonded basic (pma direct) n mode offers low transmitter channel-to-channel skew in addition to the flexibility of implementing custom pcs logic in the fpga fabric. stratix iv devices allow bonding all regular channels and cmu channels on one side of the device in basic (pma direct) n mode. for example, devices such as ep4sgx530nf45 or ep4s100g5f45 allow bonding of up to 24 channels placed in four transceiver blocks on each side of the device. 1 the coreclkout port is not available in basic (pma direct) n mode. in bonded channel configurations, the cmu0 clock divider of all the transceiver blocks is used, as shown in figure 2?17 . unlike bonded channel configurations, in basic (pma direct) n configuration: if you use the atx pll to generate the transceiver datapath interface clocks, only the clock divider of the atx pll is used. if you use the cmu pll to generate the transceiver datapath interface clocks, only the cmu0 clock divider block of the transceiver block containing the cmu pll is used. 2?36 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?22 shows transmitter channel clocking for 17 channels configured in basic (pma direct) n mode. figure 2?22 shows 17 channels configured in basic (pma direct) n mode and located across three transceiver blocks on the right side of the stratix iv device. each of the two transceiver blocks, gxbr0 and gxbr2 , contain six of the 17 n bonded channels located in four regular channels and two cmu channels. the remaining five of the 17 n bonded channels are located in four regular channels and the cmu1 channel of the transceiver block gxbr1 . 1 stratix iv devices allow both cmu channels and 6g atx pll blocks to generate the high-speed serial and low-speed parallel transceiver clocks when configured in basic (pma direct) n mode. figure 2?22. transmitter channel clocking for 17 channels configured in basic (pma direct) n mode fpga fabric serializer cmu1_channel transmitter channel pma serializer serializer serializer cmu0_pll cmu0 clock divider serializer serializer transceiver block gxbr1 transceiver block gxbr0 transceiver block gxbr2 xn_bottom high-speed serial and lo w -speed parallel clock x4 high-speed serial and lo w -speed parallel clock xn_top high-speed serial and lo w -speed parallel clock regu lar channel tx pma cmu0 channel tx pma regu lar channel tx pma cmu1 channel tx pma regu lar channel tx pcs regu lar channel tx pcs regu lar channel tx pma regu lar channel tx pcs cmu0 channel tx pma chapter 2: stratix iv transceiver clocking 2?37 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 f for more examples regarding this clocking scheme, refer to: ?example 1: channel configuration with 4-gbps data rate? on page 2?9 an 571: implementing the serdes framer interface level 5 (sfi-5.1) protocol in stratix iv devices an 572: implementing the scalable serdes framer interface (sfi-s) protocol in stratix iv gt devices transmitter channel-to-channel skew optimization in basic (pma direct) n mode in basic (pma-direct) n mode, the cmu0 channel distributes the transceiver clocks to the channels placed in the same transceiver block using the 4 clock lines. the 4 clock lines drive the n_top and n_bottom clock lines to distribute the transceiver clocks to the transmitter channels located in transceiver blocks on the bottom and top. the difference in clock routing delays between the 4 clock lines and the n clock lines can result in higher transmitter channel-to-channel skew. to compensate for this difference in clock routing delays between the 4 and the n clock lines, the stratix iv transceivers introduce a fixed amount of delay in the 4 clock lines of the transceiver block whose cmu0 channel generates the transceiver clocks. 1 the delay compensation mechanism engaged in basic (pma direct) mode only compensates for the clock routing delays between the transceiver block whose cmu0 channel generates the transceiver clocks and its adjacent transceiver block located above and below. to minimize transmitter channel-to-channel skew in n bonded channels, use the recommended placement shown in table 2?8 . 1 if you use the atx pll to generate the transceiver clocks, altera recommends that you place the channels in the transceiver blocks adjacent to the atx pll on both sides of the atx pll. f if the quartus ii software does not automatically pick the most optimal location for skew, refer to an 578: manual placement of cmu plls and atx plls in stratix iv gx and gt devices for manual placement of the cmu and atx plls. tab le 2 ?8 . recommended placement of channels and cmu in bonded modes channel placement cmu placement 2 adjacent transceiver blocks in either of the two transceiver blocks. 3 adjacent transceiver blocks in the middle transceiver block. 4 adjacent transceiver blocks in either of the middle transceiver blocks. 2?38 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation meeting timing in basic (pma direct) mode timing may not be met for higher data rates when transceiver channels are configured in basic (pma direct) functional mode. to meet fpga fabric-transmitter pma interface timing above certain data rates, you may need to phase shift the interface clock tx_clkout used to clock the transmitter user logic. to meet fpga fabric-receiver hold time violations, you may have to modify the way data is captured in the fpga fabric. f for more information, refer to an 580: achieving timing closure in basic (pma direct) functional mode . receiver channel datapath clocking this section describes the receiver pma and pcs datapath clocking in supported configurations. the receiver datapath clocking varies between non-bonded and bonded channel configurations. it also varies with the use of pcs blocks, such as deskew fifo and rate matcher. this section describes the following: ?non-bonded channel configurations? on page 2?38 ?bonded channel configurations? on page 2?42 ?basic (pma direct) mode channel configurations? on page 2?48 non-bonded channel configurations in non-bonded channel configurations, receiver pcs blocks of each channel are clocked independently. each non-bonded channel also has separate rx_analogreset and rx_digitalreset signals that allow independent reset of the receiver pcs logic in each channel. 1 for more information about transceiver reset and power down signals, refer to the reset control and power down chapter. in non-bonded channel configurations, receiver channel datapath clocking has two scenarios: ?non-bonded receiver clocking without rate matcher? on page 2?38 ?non-bonded receiver clocking with rate matcher? on page 2?40 non-bonded receiver clocking without rate matcher the following functional modes have non-bonded receiver channel configuration without rate matcher: sonet/sdh sdi (oif) cei phy interface basic without rate matcher chapter 2: stratix iv transceiver clocking 2?39 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 figure 2?23 shows receiver datapath clocking in non-bonded channel configurations without rate matcher. in non-bonded configurations without rate matcher, the cdr in each receiver channel recovers the serial clock from the received data. the serial recovered clock is divided within the receiver pma to generate the parallel recovered clock. the deserializer uses the serial recovered clock in the receiver pma. the parallel recovered clock and deserialized data is forwarded to the receiver pcs. the parallel recovered clock in each channel clocks the word aligner and 8b/10b decoder (if enabled). figure 2?23. receiver datapath clocking in non-bonded configurations without rate matcher (note 1) note to figure 2?23 : (1) the red lines represent the fpga fabric-transceiver interface clock, the green lines represent the parallel recovered clock, and the blue lines represent the serial recovered clock. receiver channel pcs receiver channel pma /2 /2 /2 /2 receiver channel pcs receiver channel pcs receiver channel pcs receiver channel pma receiver channel pma rx_coreclk[3] pci express hard ip pipe interface rx phase compensation fifo rx_clkout[3] fpga fabric-transceiver interface clock byte ordering byte de-serializer channel 3 ch3 parallel recovered clock de- serializer cdr channel 2 receiver channel pma de- serializer cdr word aligner 8b/10b decoder ch2 parallel recovered clock byte de-serializer byte ordering rx phase compensation fifo pipe interface pci express hard ip rx_clkout[2] fpga fabric-transceiver interface clock rx_coreclk[2] fpga fabric pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de-serializer ch1 parallel recovered clock channel 1 cdr de- serializer rx_clkout[1] fpga fabric-transceiver interface clock rx_coreclk[1] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de-serializer de- serializer cdr channel 0 ch0 parallel recovered clock rx_clkout[0] fpga fabric-transceiver interface clock rx_coreclk[0] word aligner 8b/10b decoder word aligner 8b/10b decoder word aligner 8b/10b decoder input reference clock input reference clock input reference clock input reference clock serial recovered clock serial recovered clock serial recovered clock serial recovered clock 2?40 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation depending on whether you use the byte deserializer or not, the parallel recovered clock (when you do not use the byte deserializer) or a divide-by-two version of the parallel recovered clock (when you use the byte deserializer) clocks the write port of the receiver phase compensation fifo. this clock is driven directly on the rx_clkout port as the fpga fabric-transceiver interface clock. you can use the rx_clkout signal to capture the receiver data and status signals in the fpga fabric. table 2?9 lists the receiver datapath clock frequencies in non-bonded functional modes without rate matcher. non-bonded receiver clocking with rate matcher the following functional modes have non-bonded receiver channel configuration with rate-matcher: pci express (pipe) 1 gige serial rapidio basic with rate matcher tab le 2 ?9 . receiver datapath clock frequencies in non-bonded functional modes without rate matcher functional mode data rate serial recovered clock frequency parallel recovered clock frequency (mhz) fpga fabric-transceiver interface clock frequency without byte deserializer (mhz) with byte deserializer (mhz) sonet/sdh oc12 622 mbps 311 mhz 77.75 77.75 n/a sonet/sdh oc48 2.488 gbps 1.244 ghz 311 n/a 155.5 hd-sdi 1.485 gbps 742.5 mhz 148.5 148.5 74.25 1.4835 gbps 741.75 mhz 148.35 148.35 74.175 3g-sdi 2.97 gbps 1.485 ghz 297 n/a 148.5 2.967 gbps 1.4835 ghz 296.7 n/a 148.35 chapter 2: stratix iv transceiver clocking 2?41 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 figure 2?24 shows the receiver datapath clocking in non-bonded channel configurations with rate matcher. in non-bonded configurations with rate matcher, the cdr in each receiver channel recovers the serial clock from the received data. the serial recovered clock is divided within the receiver pma to generate the parallel recovered clock. the deserializer uses the serial recovered clock in the receiver pma. the parallel recovered clock and deserialized data is forwarded to the receiver pcs. figure 2?24. receiver datapath clocking in non-bonded configurations with rate matcher (note 1) note to figure 2?24 : (1) the red lines represent the fpga fabric-transceiver interface clock, the green lines represent the low-speed parallel clock, the dark red lines represent the parallel recovered clock, and the blue lines represent the serial recovered clock. receiver channel pcs receiver channel pma /2 transmitter channel pma /2 /2 /2 receiver channel pcs receiver channel pcs receiver channel pcs receiver channel pma receiver channel pma transmitter channel pma transmitter channel pma rx_coreclk[3] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder channel 3 word aligner rate match fifo ch3 parallel recovered clock de- serializer cdr local clock divider from cmu0 pll from cmu1 pll channel 2 receiver channel pma transmitter channel pma de- serializer cdr local clock divider from cmu0 pll from cmu1 pll ch2 parallel recovered clock word aligner rate match fifo 8b/10b decoder low-speed parallel clock low-speed parallel clock byte de- serializer byte ordering rx phase compensation fifo pipe interface tx_clkout[3] tx_clkout[2] fpga fabric_transceiver interface clock fpga fabric_transceiver interface clock rx_coreclk[2] pci express hard ip fpga fabric pci express hard ip pipe interface fpga fabric_transceiver interface clock tx_clkout[1] rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder rate match fifo word aligner ch1 parallel recovered clock low-speed parallel clock channel 1 de- serializer cdr local clock divider from cmu0 pll from cmu1 pll channel 0 cdr de- serializer local clock divider from cmu0 pll from cmu1 pll ch0 parallel recovered clock low-speed parallel clock word aligner rate match fifo 8b/10b decoder byte de- serializer byte ordering rx phase compensation fifo pipe interface pci express hard ip tx_clkout[0] fpga fabric_transceiver interface clock rx_coreclk[1] rx_coreclk[0] serial recovered clock serial recovered clock serial recovered clock serial recovered clock input reference clock input reference clock input reference clock input reference clock 2?42 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation the parallel recovered clock from the receiver pma in each channel clocks the word aligner and the write port of the rate match fifo. the low-speed parallel clock from the transmitter local clock divider block in each channel clocks the read port of the rate match fifo, the 8b/10b decoder, and the write port of the byte deserializer (if enabled). the parallel transmitter pcs clock or its divide-by-two version (if byte deserializer is enabled) clocks the write port of the receiver phase compensation fifo. it is also driven on the tx_clkout port as the fpga fabric-transceiver interface clock. you can use the tx_clkout signal to latch the receiver data and status signals in the fpga fabric. table 2?10 lists the receiver datapath clock frequencies in non-bonded functional modes with rate matcher. bonded channel configurations the stratix iv device supports 4 channel bonding that allows bonding of four channels within the same transceiver block. it also supports 8 channel bonding that allows bonding of eight channels across two transceiver blocks on the same side of the device. in bonded channel configurations, the low-speed parallel clock for all bonded channels are generated by the same cmu0 clock divider or the atx clock divider block, resulting in lower channel-to-channel clock skew. the receiver phase compensation fifo in all bonded channels (except in basic [pma direct] n mode) share common pointers and control logic generated in the central control unit, resulting in equal latency in the receiver phase compensation fifo of all bonded channels. 1 bonding is not supported on the receive side for basic 4 and basic 8 functional modes. if you use rate matcher, the clocking scheme for basic 4 and basic 8 functional modes, the clocking is similar to pci express (pipe) 4 mode, as shown in figure 2?26 on page 2?45 and pci express (pipe) 8 mode, as shown in figure 2?27 on page 2?47 . table 2?10. receiver datapath clock frequencies in non-bonded functional modes with rate matcher functional mode data rate serial recovered clock frequency parallel recovered clock and parallel transmitter pcs clock frequency (mhz) fpga fabric-transceiver interface clock frequency without byte deserializer (mhz) with byte deserializer (mhz) pci express (pipe) 1 (gen 1) 2.5 gbps 1.25 ghz 250 250 125 pci express (pipe) 1 (gen 2) 5 gbps 2.5 ghz 500 n/a 250 gige 1.25 gbps 625 mhz 125 125 n/a serial rapidio 1.25 gbps 625 mhz 125 n/a 62.5 2.5 gbps 1.25 ghz 250 n/a 125 3.125 gbps 1.5625 ghz 312.5 n/a 156.25 chapter 2: stratix iv transceiver clocking 2?43 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 4 bonded channel configuration the following functional modes support 4 receiver channel bonded configuration: xaui ( ?x4 bonded channel configuration with deskew fifo? on page 2?43 ) pci express (pipe) ( ?x4 bonded channel configuration without deskew fifo? on page 2?45 ) x4 bonded channel configuration with deskew fifo xaui functional mode has 4 bonded channel configuration with deskew fifo. figure 2?25 shows the receiver datapath clocking in 4 channel bonding configurations with deskew fifo. figure 2?25. receiver datapath clocking in x4 bonded channel configuration with deskew fifo (note 1) note to figure 2?25 : (1) the red lines represent the fpga fabric-transceiver interface clock, the green lines represent the low-speed parallel clock, the dark red lines represent the ch0 parallel recovered clock, and the blue lines represent the serial recovered clock. fpga fabric receiver channel pcs receiver channel pma /2 /2 /2 /2 /2 receiver channel pcs receiver channel pcs receiver channel pcs receiver channel pma receiver channel pma receiver channel pma rx_coreclk[3] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder rate match fifo word aligner channel 3 channel 2 de- serializer cdr ch3 parallel recovered clock ch0 parallel recovered clock low-speed parallel clock from cmu0 clock divider rx_coreclk[2] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder rate match fifo word aligner de- serializer cdr ch2 parallel recovered clock ch0 parallel recovered clock low-speed parallel clock from cmu0 clock divider coreclkout fpga fabric-transceiver interface clock input reference clock input reference clock cmu1 channel cmu0 channel cmu0 clock divider cmu1 clock divider low-speed parallel clock rx_coreclk[1] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder rate match fifo channel 1 word aligner de- serializer cdr ch1 parallel recovered clock low-speed parallel clock from cmu0 clock divider ch0 parallel recovered clock rx_coreclk[0] pci express hard ip pipe interface rx phase compensation fifo byte de- serializer byte ordering 8b/10b decoder rate match fifo word aligner deskew fifo low-speed parallel clock from cmu0 clock divider channel 0 de- serializer cdr ch0 parallel recovered clock cmu1 pll cmu0 pll input reference clock input reference cloc k input reference clock input reference clock serial recovered clock deskew fifo deskew fifo deskew fifo serial recovered clock serial recovered clock serial recovered clock 2?44 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation in 4 bonded channel configurations with deskew fifo, the cdr in each receiver channel recovers the serial clock from the received data. the serial recovered clock is divided within each channel?s receiver pma to generate the parallel recovered clock. the deserializer uses the serial recovered clock in the receiver pma. the parallel recovered clock and deserialized data is forwarded to the receiver pcs in each channel. the parallel recovered clock from the receiver pma in each channel clocks the word aligner in that channel. the parallel recovered clock from channel 0 clocks the deskew fifo and the write port of the rate match fifo in all four bonded channels. the low-speed parallel clock from the cmu0 clock divider block in cmu0_channel clocks the read port of the rate match fifo, the 8b/10b decoder, and the write port of the byte deserializer (if enabled) in all four bonded channels. the low-speed parallel clock or its divide-by-two version (if byte deserializer is enabled) clocks the write port of the receiver phase compensation fifo. it is also driven on the coreclkout port as the fpga fabric-transceiver interface clock. you can use the coreclkout signal to latch the receiver data and status signals in the fpga fabric for all four bonded channels. table 2?11 lists the receiver datapath clock frequencies in 4 bonded functional modes with deskew fifo. table 2?11. receiver datapath clock frequencies in x4 bonded functional modes with deskew fifo functional mode data rate serial recovered clock frequency parallel recovered clock and parallel transmitter pcs clock frequency (mhz) fpga-fabric transceiver interface clock frequency without byte deserializer (mhz) with byte deserializer (mhz) pci express (pipe) 4 (gen 1) 2.5 gbps 1.25 ghz 250 250 125 pci express (pipe) 4 (gen 2) 5 gbps 2.5 ghz 500 n/a 250 xaui 3.125 gbps 1.5625 mhz 312.5 n/a 156.25 chapter 2: stratix iv transceiver clocking 2?45 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 x4 bonded channel configuration without deskew fifo pci express (pipe) 4 functional modes have 4 bonded channel configuration without deskew fifo. figure 2?26 shows the receiver datapath clocking in 4 channel bonding configurations without deskew fifo. figure 2?26. receiver datapath clocking in x4 bonded channel configuration without deskew fifo (note 1) note to figure 2?26 : (1) the red lines represent the fpga fabric-transceiver interface clock, the green lines represent the low-speed parallel clock, the dark red lines represent the parallel recovered clock, and the blue lines represent the serial recovered clock. receiver channel pcs receiver channel pma /2 /2 /2 /2 /2 receiver channel pcs receiver channel pcs receiver channel pcs receiver channel pma receiver channel pma receiver channel pma rx_coreclk[3] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder rate match fifo word aligner channel 3 de- serializer cdr ch3 parallel recovered clock low-speed parallel clock from cmu0 clock divider rx_coreclk[2] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder rate match fifo word aligner channel 2 de- serializer cdr ch2 parallel recovered clock low-speed parallel clock from cmu0 clock divider coreclkout fpga fabric_transceiver interface clock input reference clock input reference clock cmu0 clock divider cmu0 channel cmu1 channel cmu1 clock divider low-speed parallel clock channel 1 fpga fabric rx_coreclk[1] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder rate match fifo ch1 parallel recovered clock low-speed parallel clock from cmu0 clock divider word aligner de- serializer cdr rx_coreclk[0] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder rate match fifo word aligner channel 0 de- serializer cdr ch0 parallel recovered clock low-speed parallel clock from cmu0 clock divider cmu1 pllcmu1 pll cmu0 pll serial recovered clock input reference clock serial recovered clock input reference clock serial recovered clock input reference clock serial recovered clock input reference clock 2?46 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation in 4 bonded channel configurations without deskew fifo, the cdr in each receiver channel recovers the serial clock from the received data. the serial recovered clock is divided within each channel?s receiver pma to generate the parallel recovered clock. the deserializer uses the serial recovered clock in the receiver pma. the parallel recovered clock and deserialized data is forwarded to the receiver pcs in each channel. the parallel recovered clock from the receiver pma in each channel clocks the word aligner and the write side of the rate matcher fifo in that channel. the low-speed parallel clock from the cmu0 clock divider block in cmu0_channel clocks the read port of the rate match fifo, the 8b/10b decoder, and the write port of the byte deserializer (if enabled). the low-speed parallel clock or its divide-by-two version (if byte deserializer is enabled) clocks the receiver phase compensation fifo. it is also driven on the coreclkout port as the fpga fabric-transceiver interface clock. you can use the coreclkout signal to latch the receiver data and status signals in the fpga fabric for all four bonded channels. table 2?12 lists the receiver datapath clock frequencies in 4 bonded functional modes without deskew fifo. table 2?12. receiver datapath clock frequencies in x4 bonded functional modes without deskew fifo functional mode data rate serial recovered clock frequency parallel recovered clock and parallel transmitter pcs clock frequency (mhz) fpga fabric-transceiver interface clock frequency without byte deserializer (mhz) with byte deserializer (mhz) pci express (pipe) 4 (gen 1) 2.5 gbps 1.25 ghz 250 250 125 pci express (pipe) 4 (gen 2) 5 gbps 2.5 ghz 500 n/a 250 chapter 2: stratix iv transceiver clocking 2?47 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 x8 bonded channel configuration pci express (pipe) 8 functional mode supports the 8 receiver channel bonding configuration. the eight bonded channels are located in two transceiver blocks, referred to as the master transceiver block and slave transceiver block, with four channels each. figure 2?27 shows the receiver datapath clocking in pci express (pipe) 8 bonded channel configuration. figure 2?27. receiver datapath clocking in x8 bonded channel configuration (note 1) note to figure 2?27 : (1) the red lines represent the fpga fabric-transceiver interface clock, the green lines represent the low-speed parallel clock, the dark red lines represent the parallel recovered clock, and the blue lines represent the serial recovered clock. master transceiver block slave transceiver block /2 /2 receiver channel pcs /2 receiver channel pcs receiver channel pma rx_coreclk[7:4] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder rate match fifo word aligner receiver channel pma de- serializer cdr parallel recovered clock low-speed parallel clock from cmu0 clock divider fpga fabric cmu1 channel cmu0 channel cmu1 pll cmu0 pll cmu1 clock divider cmu0 clock divider rx_coreclk[3:0] pci express hard ip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder rate match fifo word aligner de- serializer cdr parallel recovered clock low-speed parallel clock from cmu0 clock divider coreclkout fpga fabric_transceiver interface clock input reference clock input reference clock cmu1 channel cmu0 channel cmu0 clock divider cmu1 clock divider cmu1 pll cmu0 pll serial recovered clock input reference cloc k serial recovered clock input reference clock 2?48 chapter 2: stratix iv transceiver clocking transceiver channel datapath clocking stratix iv device handbook volume 2 ? march 2010 altera corporation the cdr in each of the eight receiver channels recovers the serial clock from the received data on that channel. the serial recovered clock is divided within each channel?s receiver pma to generate the parallel recovered clock. the deserializer uses the serial recovered clock in the receiver pma. the parallel recovered clock and deserialized data from the receiver pma in each channel is forwarded to the receiver pcs in that channel. the parallel recovered clock from the receiver pma in each channel clocks the word aligner and the write side of the rate matcher fifo in that channel. the low-speed parallel clock from the cmu0 clock divider of the master transceiver block clocks the read port of the rate match fifo, the 8b/10b decoder, and the write port of the byte deserializer (if enabled) in all eight channels. the low-speed parallel clock or its divide-by-two version (if byte deserializer is enabled) clocks the write port of the receiver phase compensation fifo in all eight channels. it is also driven on the coreclkout port as the fpga fabric-transceiver interface clock. you can use the coreclkout signal to latch the receiver data and status signals in the fpga fabric for all eight bonded channels. table 2?13 lists the receiver datapath clock frequencies in pci express (pipe) 8 functional mode. basic (pma direct) mode channel configurations figure 2?28 shows six channels in a transceiver block configured in basic (pma direct) functional mode with two of the channels being cmu channels. the receiver channel pma directly interfaces to the user logic in the fpga fabric. the cdr recovers the high-speed serial clock and low-speed parallel clock for the deserializer. the low-speed parallel clock is forwarded to the fpga fabric as rx_clkout. 1 bonded mode is not available for the receivers configured in basic (pma direct) functional mode. data registers to capture the receiver data in the fpga fabric for each channel must be clocked by rx_clkout forwarded by that channel?s cdr. table 2?13. receiver datapath clock frequencies pci express (pipe) x8 functional mode functional mode data rate serial recovered clock frequency parallel recovered clock and parallel transmitter pcs clock frequency (mhz) fpga fabric-transceiver interface clock frequency without byte deserializer (mhz) with byte deserializer (mhz) pci express (pipe) 8 (gen 1) 2.5 gbps 1.25 ghz 250 250 125 pci express (pipe) 8 (gen 2) 5 gbps 2.5 ghz 500 n/a 250 chapter 2: stratix iv transceiver clocking 2?49 transceiver channel datapath clocking ? march 2010 altera corporation stratix iv device handbook volume 2 figure 2?28. receiver channel pma directly interfacing to the user logic in the fpga fabric (note 1) note to figure 2?28 : (1) the green lines represent the low-speed parallel clock and the blue lines represent the serial recovered clock. de- serializer cdr fpga fabric rx_clkout[5] channel 3 de- serializer cdr rx_clkout[4] channel 2 de- serializer cdr rx_clkout[3] cmu1_channel de- serializer cdr rx_clkout[2] cmu0_channel de- serializer cdr rx_clkout[1] channel 1 de- serializer cdr rx_clkout[0] channel 0 lo w -speed parallel clock lo w -speed parallel clock lo w -speed parallel clock lo w -speed parallel clock lo w -speed parallel clock lo w -speed parallel clock receiv er channel pcs receiv er channel pcs receiv er channel pcs receiv er channel pcs receiv er channel pma receiv er channel pma receiv er channel pma receiv er channel pma receiv er channel pma receiv er channel pma high-speed serial cloc k high-speed serial clock high-speed serial cloc k high-speed serial clock high-speed serial clock high-speed serial cloc k 2?50 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation fpga fabric-transceiver interface clocking the fpga fabric-transceiver interface clocks consist of clock signals from the fpga fabric to the transceiver blocks and clock signals from the transceiver blocks to the fpga fabric. these clock resources use the clock networks in the fpga core that include the global, regional, and periphery clock networks. the fpga fabric-transceiver interface clocks can be subdivided into the following three categories: input reference clocks ?refer to ?input reference clock source? on page 2?3 . transceiver datapath interface clocks ?are used to transfer data, control, and status signals between the fpga fabric and the transceiver channels. the transceiver channel forwards the tx_clkout signal (in non-bonded modes) or the coreclkout signal (in bonded channel modes) to the fpga fabric to clock the data and control signals into the transmitter. the transceiver channel also forwards the recovered rx_clkout clock (in configurations without rate matcher) or tx_clkout/coreclkout (in configurations with rate matcher) to the fpga fabric to clock the data and status signals from the receiver into the fpga fabric. other transceiver clocks ?the following transceiver clocks form a part of the fpga fabric-transceiver interface clocks: cal_blk_clk ?calibration block clock fixed_clk ?125 mhz fixed-rate clock used in the pci express (pipe) receiver detect circuitry and for the adaptive equalization (aeq) block reconfig_clk ?clock used for transceiver dynamic reconfiguration (for more information, refer to table 2?5 on page 2?9 ) 1 in basic (pma direct) functional mode, only tx_clkout and rx_clkout are available to clock the logic in the core. in bonded mode, you may use tx_clkout of one of the channels to clock all of the channels. for receivers in bonded mode, you must use separate rx_clkout for each channel. table 2?14 lists the fpga fabric-transceiver interface clocks. table 2?14. fpga fabric-transceiver interface clocks (note 1) (part 1 of 2) clock name clock description interface direction fpga fabric clock resource utilization (1) pll_inclk cmu pll input reference clock when driven from an fpga clk input pin fpga fabric-to-transceiver gclk rx_cruclk receiver cdr input reference clock when driven from an fpga clk input pin fpga fabric-to-transceiver gclk, rclk tx_clkout phase compensation fifo clock transceiver-to-fpga fabric gclk, rclk, pclk coreclkout phase compensation fifo clock transceiver-to-fpga fabric gclk, rclk, pclk rx_clkout phase compensation fifo clock transceiver-to-fpga fabric gclk, rclk, pclk fixed_clk pci express (pipe) receiver detect clock fpga fabric-to-transceiver gclk, rclk reconfig_clk (2) transceiver dynamic reconfiguration clock fpga fabric-to-transceiver gclk chapter 2: stratix iv transceiver clocking 2?51 fpga fabric-transceiver interface clocking ? march 2010 altera corporation stratix iv device handbook volume 2 ?fpga fabric-transmitter interface clocking? on page 2?51 and ?fpga fabric-receiver interface clocking? on page 2?60 describe the criteria and methodology to share transmitter and receiver phase compensation fifo clocks in order to reduce the gclk, rclk, and pclk resource utilization in your design. fpga fabric-transmitter interface clocking the transmitter phase compensation fifo compensates for the phase difference between the fpga fabric clock (phase compensation fifo write clock) and the parallel transmitter pcs clock (phase compensation fifo read clock). the transmitter phase compensation fifo write clock forms the fpga fabric-transmitter interface clock. the phase compensation fifo write clock and read clocks must have exactly the same frequency (0 parts-per-million [ppm] frequency difference). stratix iv transceivers provide the following two options for selecting the transmitter phase compensation fifo write clock: ?quartus ii-selected transmitter phase compensation fifo write clock? on page 2?51 ?user-selected transmitter phase compensation fifo write clock? on page 2?57 1 user-selection is provided to share transceiver datapath interface clocks in order to reduce the gclk, rclk, and pclk resource utilization in your design. quartus ii-selected transmitter phase compensation fifo write clock if you do not select the tx_coreclk port in the altgx megawizard ? plug-in manager, the quartus ii software automatically selects the transmitter phase compensation fifo write clock for each channel in that altgx instance. the quartus ii software selects the fifo write clock depending on the channel configuration. non-bonded channel configuration in a non-bonded channel configuration, the transmitter channels may or may not be identical. identical transmitter channels are defined as channels that have exactly the same cmu pll input reference clock source, exactly the same cmu pll configuration, and exactly the same transmitter pma and pcs configuration. 1 identical transmitter channels may have different transmitter voltage output differential ( v od ), transmitter common mode voltage (v cm ), or pre-emphasis setting. cal_blk_clk transceiver calibration block clock fpga fabric-to-transceiver gclk, rclk note to tab l e 2 ?1 1 : (1) for more information about gclk, rclk, and pclk resources available in each device, refer to the clock networks and plls in stratix iv devices chapter. (2) ensure that the reconfig_clk is a free-running clock that is not derived from the transceiver blocks. table 2?14. fpga fabric-transceiver interface clocks (note 1) (part 2 of 2) clock name clock description interface direction fpga fabric clock resource utilization (1) 2?52 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation example 3: two groups of two identical channels in a transceiver block example 3 assumes channels 0 and 1, driven by cmu0_pll in a transceiver block, are identical. also, channels 2 and 3, driven by cmu1_pll in the same transceiver block, are identical. in this case, the quartus ii software automatically drives the write port of the transmitter phase compensation fifo in channels 0 and 1 with the tx_clkout[0] signal. it also drives the write port of the transmitter phase compensation fifo in channels 2 and 3 with the tx_clkout[2] signal. use the tx_clkout[0] signal to clock the transmitter data and control logic for channels 0 and 1 in the fpga fabric. use the tx_clkout[2] signal to clock the transmitter data and control logic for channels 2 and 3 in the fpga fabric. 1 this configuration uses two fpga global and/or regional clock resources, one for the tx_clkout[0] signal and the other for the tx_clkout[2] signal. chapter 2: stratix iv transceiver clocking 2?53 fpga fabric-transceiver interface clocking ? march 2010 altera corporation stratix iv device handbook volume 2 figure 2?29 shows the fpga fabric-transmitter interface clocking for example 3. figure 2?29. fpga fabric-transmitter interface clocking for example 3 (note 1) note to figure 2?29 : (1) the green lines represent the low-speed parallel clock and the blue lines represent the high-speed serial clock. /2 wrclk rdclk transmitter channel pcs transmitter channel pma /2 wrclk rdclk /2 wrclk rdclk /2 wrclk rdclk transmitter channel pcs transmitter channel pma transmitter channel pcs transmitter channel pma transmitter channel pma transmitter channel pcs channel 3 tx data and control logic tx_coreclk[3] channel 2 tx data and control logic tx phase compensation fifo tx phase compensation fifo channel 3 channel 2 local clock divider block local clock divider block tx_clkout[2] tx_coreclk[2] fpga fabric input reference clock input reference clock cmu1 pll cmu0 pll cmu1 clock divider cmu0 clock divider cmu1 channel cmu0 channel channel 1 channel 1 tx data and control logic tx_coreclk[1] tx phase compensation fifo local clock divider block channel 0 local clock divider block low-speed parallel clock tx phase compensation fifo channel 0 tx data and control logic tx_coreclk[0] tx_clkout[0] low-speed parallel clock low-speed parallel clock low-speed parallel clock high-speed serial clock 2?54 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation bonded channel configuration in 4 and 8 bonded channel configurations, all channels within the transceiver block are identical. the quartus ii software automatically drives the write port of the transmitter phase compensation fifo in all channels with the coreclkout signal. use the coreclkout signal to clock the transmitter data and control logic for all four channels in the fpga fabric. figure 2?30 shows the fpga fabric-transmitter interface clocking in a 4 bonded channel configuration. figure 2?30. fpga fabric-transmitter interface clocking in a x4 bonded channel configuration (note 1) note to figure 2?30 : (1) the green lines represent the parallel pcs clock. /2 wrclk rdclk transmitter channel pcs /2 wrclk rdclk /2 wrclk rdclk parallel pcs clock /2 wrclk rdclk /2 transmitter channel pcs transmitter channel pcs transmitter channel pcs channel 3 tx data and control logic tx_coreclk[3] tx phase compensation fifo channel 3 channel 2 parallel pcs clock parallel pcs clock tx phase compensation fifo channel 2 tx data and control logic tx_coreclk[2] coreclkout fpga fabric input reference clock cmu1 pll cmu0 pll cmu0 clock divider cmu1 channel cmu0 channel channel 1 channel 0 parallel pcs clock tx phase compensation fifo tx phase compensation fifo channel 1 tx data and control logic channel 0 tx data and control logic tx_coreclk[1] tx_coreclk[0] chapter 2: stratix iv transceiver clocking 2?55 fpga fabric-transceiver interface clocking ? march 2010 altera corporation stratix iv device handbook volume 2 limitations of the quartus ii software-selected transmitter phase compensation fifo write clock the quartus ii software uses a single tx_clkout signal to clock the transmitter phase compensation fifo write port of all identical channels within a transceiver block. this results in one global and/or regional clock resource being used for each group of identical channels within a transceiver block. for identical channels located across the transceiver blocks, the quartus ii software does not use a single tx_clkout signal to clock the write port of the transmitter phase compensation fifos for all channels. it uses one tx_clkout signal for each group of identical channels per transceiver block. this results in higher global and regional clock resource utilization. example 4: sixteen identical channels across four transceiver blocks figure 2?31 shows 16 identical transmitter channels located across four transceiver blocks. the quartus ii software uses tx_clkout from channel 0 in each transceiver block to clock the write port of the transmitter phase compensation fifo in all four channels in that transceiver block. this results in four global and/or regional clock resources being used, one for each transceiver block. 2?56 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?31. sixteen identical channels across four transceiver blocks for example 4 (note 1) note to figure 2?31 : (1) the red lines represent tx_clkout[12] , the blue lines represent tx_clkout[8] , the green lines represent tx_clkout[4] , and the brown lines represent tx_clkout[0] . channel [15:12] tx data and control logic tx_coreclk[15:12] tx_clkout[12] transceiver block gxbr3 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 transceiver block gxbr2 t x_clkout [ 8 ] tx_clkout[8] tx_coreclk[11:8] channel [11:8] tx data and control logic fpga fabric channel [7:4] tx data and control logic tx_coreclk[7:4] channel 3 channel 2 channel 1 channel 0 transceiver block gxbr1 tx_clkout[4] transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 tx_clkout[0] tx_coreclk[3:0] channel [3:0] tx data and control logic chapter 2: stratix iv transceiver clocking 2?57 fpga fabric-transceiver interface clocking ? march 2010 altera corporation stratix iv device handbook volume 2 because all 16 channels are identical, using a single tx_clkout to clock the transmitter phase compensation fifo in all 16 channels results in only one global or regional clock resource being used instead of four. to achieve this, you must choose the transmitter phase compensation fifo write clocks instead of the quartus ii software automatic selection, as described in ?user-selected transmitter phase compensation fifo write clock? on page 2?57 . user-selected transmitter phase compensation fifo write clock the altgx megawizard plug-in manager provides an optional port named tx_coreclk for each instantiated transmitter channel. if you enable this port, the quartus ii software does not automatically select the transmitter phase compensation fifo write clock source. instead, the signal that you drive on the tx_coreclk port of the channel clocks the write side of its transmitter phase compensation fifo. use the flexibility of selecting the transmitter phase compensation fifo write clock to reduce global and regional clock resource utilization. you can connect the tx_coreclk ports of all identical channels in your design and drive them using a common clock driver that has 0 ppm frequency difference with respect to the fifo read clocks of these channels. use the common clock driver to clock the transmitter data and control logic in the fpga fabric for all identical channels. this fpga fabric-transceiver interface clocking scheme uses only one global or regional clock resource for all identical channels in your design. example 5: sixteen identical channels across four transceiver blocks figure 2?32 shows 16 identical transmitter channels located across four transceiver blocks. the tx_coreclk ports of all 16 transmitter channels are connected together and driven by a common clock driver. this common clock driver also drives the transmitter data and control logic of all 16 transmitter channels in the fpga fabric. you use only one global or regional clock resource with this clocking scheme, compared to four global and regional clock resources needed without the tx_coreclk ports (the quartus ii software-selected transmitter phase compensation fifo write clock). 2?58 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation common clock driver selection rules the common clock driver driving the tx_coreclk ports of all identical channels must have 0 ppm frequency difference with respect to the transmitter phase compensation fifo read clocks of these channels. if there is any frequency difference between the fifo write clock ( tx_coreclk ) and the fifo read clock, the fifo overflows or under-runs, resulting in corrupted data transfer between the fpga fabric and the transmitter. figure 2?32. sixteen identical channels across four transceiver blocks for example 5 channel [15:12] tx data and control logic common clock driver tx_coreclk[15:12] tx_clkout[12] transceiver block gxbr3 channel 3 channel 2 channel 1 channel 0 transceiver block gxbr 2 channel 3 channel 2 channel 1 channel 0 tx_clkout[8] tx_coreclk[11:8] channel [11:8] tx data and control logic fpga fabric channel [7:4] tx data and control logic tx_coreclk[7:4] tx_clkout[4] transceiver block gxbr 1 channel 3 channel 2 channel 1 channel 0 transceiver block gxbr 0 channel 3 channel 2 channel 1 channel 0 tx_clkout[0] tx_coreclk[3:0] channel [3:0] tx data and control logic chapter 2: stratix iv transceiver clocking 2?59 fpga fabric-transceiver interface clocking ? march 2010 altera corporation stratix iv device handbook volume 2 table 2?15 lists the transmitter phase compensation fifo read clocks that the quartus ii software selects in various configurations. to ensure that you understand the 0 ppm clock driver rule, the quartus ii software expects the following set of user assignments whenever you use the tx_coreclk port to drive the transmitter phase compensation fifo write clock: gxb 0 ppm core clock setting 1 failing to make this assignment correctly when using the tx_coreclk port results in a quartus ii compilation error. the gxb 0 ppm core clock setting allows the following clock drivers to drive the tx_coreclk ports: tx_clkout in non-bonded channel configurations coreclkout in bonded channel configurations fpga_clk input pins tr a n sc e iv er refclk pins clock output from left and right and top and bottom plls ( pll_l, pll_r , and pll_t , pll_b) 1 the quartus ii software does not allow gated clocks or clocks generated in fpga logic to drive the tx_coreclk ports. because the gxb 0 ppm core clock setting allows the fpga clk input pins and transceiver refclk pins as the clock driver, the quartus ii compiler cannot determine if there is a 0 ppm difference between the fifo write clock and read clock for each channel. 1 you must ensure that the clock driver for all connected tx_coreclk ports has a 0 ppm difference with respect to the fifo read clock in those channels. table 2?15. transmitter phase compensation fifo read clocks configuration transmitter phase compensation fifo read clock without byte serializer with byte serializer non-bonded channel configuration parallel transmitter pcs clock from the local clock divider in the associated channel ( tx_clkout ) divide-by-two version of the parallel transmitter pcs clock from the local clock divider in the associated channel ( tx_clkout ) 4 bonded channel configuration low-speed parallel clock from the cmu0 clock divider of the associated transceiver block ( coreclkout ) divide-by-two version of the low-speed parallel clock from the cmu0 clock divider of the associated transceiver block ( coreclkout ) 8 bonded channel configuration low-speed parallel clock from the cmu0 clock divider of the master transceiver block ( coreclkout from master transceiver block) divide-by-two version of the low-speed parallel clock from the cmu0 clock divider of the master transceiver block ( coreclkout from master transceiver block) 2?60 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation table 2?16 lists the quartus ii assignments that you must make in the assignment editor. for more implementation information, refer to ?configuration example 2: configuring sixteen identical channels across four transceiver blocks? on page 2?75 . basic (pma direct) mode in basic (pma direct) mode, each channel must be clocked by its own tx_clkout. as a result, the number of global and/or regional clock resources required is significantly higher. in basic (pma direct) n mode, to save on global and/or regional clock resources, you may use tx_clkout from centrally located channels to clock all the channels. the coreclkout port is not available in basic (pma direct) n mode. fpga fabric-receiver interface clocking the receiver phase compensation fifo compensates for the phase difference between the parallel receiver pcs clock (fifo write clock) and the fpga fabric clock (fifo read clock). the receiver phase compensation fifo read clock forms the fpga fabric-receiver interface clock. the fifo write clock and read clock must have exactly the same frequency (0 ppm frequency difference). stratix iv transceivers provide the following two options for selecting the receiver phase compensation fifo read clock: ?quartus ii software-selected receiver phase compensation fifo read clock? on page 2?61 ?user-selected receiver phase compensation fifo read clock? on page 2?68 1 user-selection is provided to share transceiver datapath interface clocks in order to reduce the gclk, rclk, and pclk resource utilization in your design. table 2?16. quartus ii assignments from full design hierarchy name of one of the following clock drivers that you choose to drive the tx_coreclk ports of all identical channels (1) : tx_clkout coreclkout fpga clk input pins transceiver refclk pins clock output from the left and right or top and bottom plls tx_dataout port of one of the identical channels to tx_dataout pins of all identical channels whose tx_coreclk ports are connected together and driven by the 0 ppm clock driver. assignment name gxb 0 ppm core clock setting value on note to tab l e 2 ?1 3 : (1) you can find the full hierarchy name of the 0 ppm clock driver using the node finder feature in the quartus ii assignment editor. chapter 2: stratix iv transceiver clocking 2?61 fpga fabric-transceiver interface clocking ? march 2010 altera corporation stratix iv device handbook volume 2 quartus ii software-selected receiver phase compensation fifo read clock if you do not select the rx_coreclk port in the altgx megawizard plug-in manager, the quartus ii software automatically selects the receiver phase compensation fifo read clock for each channel in that altgx instance. the quartus ii software selects the fifo read clock depending on the channel configuration. in non-bonded channel configurations, the fpga fabric-receiver interface clocking has two scenarios: receivers the do not use a rate matcher block (refer to ?non-bonded receiver clocking without rate matcher? on page 2?38 receivers that use a rate matcher block (refer to ?non-bonded receiver clocking with rate matcher? on page 2?40 non-bonded channel configuration with rate matcher in non-bonded channel configuration, the transceiver channels may or may not be identical. identical transceiver channels are defined as channels that have exactly the same cmu pll and receiver cdr input reference clock sources, exactly the same cmu pll and receiver cdr configuration, and exactly the same pma and pcs configuration. example 6: two groups of two identical channels in a transceiver block example 6 assumes channels 0 and 1, driven by the cmu0 pll in a transceiver block, are identical. also, channels 2 and 3, driven by the cmu1 pll in the same transceiver block, are identical. in this case, the quartus ii software automatically drives the read port of the receiver phase compensation fifo in channels 0 and 1 with the tx_clkout[0] signal. it also drives the read port of the receiver phase compensation fifo in channels 2 and 3 with the tx_clkout[2] signal. use the tx_clkout[0] signal to latch the receiver data and status signals from channels 0 and 1 in the fpga fabric. use the tx_clkout[2] signal to latch the receiver data and status signals from channels 2 and 3 in the fpga fabric. 1 this configuration uses two fpga global and/or regional clock resources, one for the tx_clkout[0] signal and the other for the tx_clkout[2] signal. 2?62 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?33 shows the fpga fabric-receiver interface clocking for example 6. figure 2?33. fpga fabric-receiver interface clocking for example 6 (note 1) note to figure 2?33 : (1) the green lines represent the low-speed parallel clock and the blue lines represent the high-speed serial clock. /2 rdclk wrclk receiver channel pcs transmitter channel pma /2 rdclk wrclk receiver channel pcs /2 rdclk wrclk receiver channel pcs rx phase compensation fifo /2 rdclk wrclk channel 0 receiver channel pcs cmu1 pll cmu0 pll receiver channel pma transmitter channel pma receiver channel pma transmitter channel pma receiver channel pma transmitter channel pma receiver channel pma channel 3 rx data and status logic rx_coreclk[3] rx phase compensation fifo low-speed parallel clock channel 3 local clock divider block channel 2 local clock divider block low-speed parallel clock rx phase compensation fifo channel 2 rx data and status logic rx_coreclk[2] tx_clkout[2] fpga fabric reference clock reference clock cmu1 channel cmu0 channel channel 1 low-speed parallel clock rx phase compensation fifo channel 1 rx data and status logic rx_coreclk[1] tx_clkout[0] channel 0 rx data and status logic low-speed parallel clock local clock divider block local clock divider block rx_coreclk[0] high-speed serial clock chapter 2: stratix iv transceiver clocking 2?63 fpga fabric-transceiver interface clocking ? march 2010 altera corporation stratix iv device handbook volume 2 non-bonded channel configuration without rate matcher in non-bonded channel configuration without rate matcher, the quartus ii software cannot determine if the incoming serial data in all channels have a 0 ppm frequency difference. the quartus ii software automatically drives the read port of the receiver phase compensation fifo in each channel with the recovered clock driven on the rx_clkout port of that channel. use the rx_clkout signal from each channel to latch its receiver data and status signals in the fpga fabric. 1 this configuration uses one fpga global, regional clock, or both, resource per channel for the rx_clkout signal. 2?64 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?34 shows the fpga fabric-receiver interface clocking for non-bonded channel configurations without rate matcher. figure 2?34. fpga fabric-receiver interface clocking for non-bonded channel configurations without rate matcher (note 1) note to figure 2?34 : (1) the red lines represent rx_clkout[3] , the blue lines represent rx_clkout[2] , the green lines represent rx_clkout[1] , and the brown lines represent rx_clkout[0] . /2 rdclk wrclk parallel recovered clock receiver channel pcs receiver channel pma /2 rdclk wrclk receiver channel pcs /2 receiver channel pcs /2 receiver channel pcs receiver pma receiver channel pma receiver pma receiver channel pma receiver pma cdr receiver channel pma channel 3 rx data and status logic rx_coreclk[3] rx phase compensation fifo rx_clkout[3] channel 3 cdr rx_datain[3] channel 2 rx data and status logic rx_coreclk[2] rx phase compensation fifo parallel recovered clock channel 2 cdr rx_datain[2] channel 1 rx_datain[1] cdr parallel recovered clock fpga fabric channel 1 rx data and status logic rx_coreclk[1] rx_clkout[2] rx_clkout[1] channel 0 rx data and status logic rx_coreclk[0] rx_clkout[0] channel 0 parallel recovered clock rx_datain[0] input reference clock input reference cloc k input reference clock rdclk wrclk rx phase compensation fifo rdclk wrclk rx phase compensation fifo chapter 2: stratix iv transceiver clocking 2?65 fpga fabric-transceiver interface clocking ? march 2010 altera corporation stratix iv device handbook volume 2 bonded channel configuration all bonded transceiver channel configurations have rate matcher in the receiver data path. in 4 and 8 bonded channel configurations, the quartus ii software automatically drives the read port of the receiver phase compensation fifo in all channels with the coreclkout signal (from the master transceiver block in the case of 8 bonded mode). use the coreclkout signal to latch the receiver data and status signals from all channels in the fpga fabric. 1 this configuration uses one fpga global and/or regional clock resource per bonded link for the coreclkout signal. figure 2?35 shows the fpga fabric-receiver interface clocking in 4 bonded channel configuration. figure 2?35. fpga fabric-receiver interface clocking in a x4 bonded channel configuration (note 1) note to figure 2?35 : (1) the green lines represent low-speed parallel clock from the cmu0 clock divider. /2 rdclk wrclk transmitter channel pcs /2 transmitter channel pcs /2 rdclk wrclk transmitter channel pcs /2 /2 channel 3 rx data and status logic rx_coreclk[3] rx phase compensation fifo channel 3 channel 2 channel 2 rx data and status logic rx_coreclk[2] fpga fabric coreclkout reference clock cmu1 pll cmu0 pll cmu0 clock divider cmu1 channel cmu0 channel channel 1 channel 0 transmitter channel pcs rx phase compensation fifo channel 1 rx data and status logic channel 0 rx data and status logic rx_coreclk[1] rx_coreclk[0] low-speed parallel clock from cmu0 clock divider low-speed parallel clock from cmu0 clock divider low-speed parallel clock from cmu0 clock divider low-speed parallel clock from cmu0 clock divider rdclk wrclk rx phase compensation fifo rdclk wrclk rx phase compensation fifo rdclk wrclk rx phase compensation fifo 2?66 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation limitations of the quartus ii software-selected receiver phase compensation fifo read clock in non-bonded channel configurations without rate matcher, the quartus ii software cannot determine if the incoming serial data in all channels has a 0 ppm frequency difference. the quartus ii software uses the recovered clock rx_clkout signal from each channel to clock the read port of its receiver phase compensation fifo. this results in one global, regional, or global and regional clock resource being used per channel for the rx_clkout signal. example 7: sixteen channels across four transceiver blocks figure 2?36 shows 16 non-bonded receiver channels without rate matcher, located across four transceiver blocks. the incoming serial data to all 16 channels have a 0 ppm frequency difference with respect to each other. the quartus ii software uses rx_clkout from each channel to clock the read port of its receiver phase compensation fifo. this results in 16 global, regional, or global and regional clock resources being used, one for each channel. chapter 2: stratix iv transceiver clocking 2?67 fpga fabric-transceiver interface clocking ? march 2010 altera corporation stratix iv device handbook volume 2 because the recovered clock rx_clkout signals from all 16 channels have a 0 ppm frequency difference, you can use a single rx_clkout to clock the receiver phase compensation fifo in all 16 channels. this results in only one global, regional, or global and regional clock resource being used instead of 16. to achieve this, you must select the receiver phase compensation fifo read clocks instead of the quartus ii software default selection, as described in ?user-selected receiver phase compensation fifo read clock? on page 2?68 . figure 2?36. sixteen non-bonded receiver channels without rate match for example 7 channel [15:12] rx data and status logic rx_coreclk[15] rx_coreclk[14] rx_coreclk[13] rx_coreclk[12] rx_clkout[15] rx_clkout[14] rx_clkout[13] rx_clkout[12] transceiver block gxbr3 channel 3 channel 2 channel 1 channel 0 channel [11:8] rx data and status logic rx_clkout[11] rx_clkout[10] rx_clkout[9] rx_clkout[8] rx_coreclk[11] rx_coreclk[10] rx_coreclk[9] rx_coreclk[8] transceiver block gxbr2 channel 3 channel 2 channel 1 channel 0 fpga fabric channel [7:4] rx data and status logic rx_coreclk[7] rx_coreclk[6] rx_coreclk[5] rx_coreclk[4] rx_clkout[7] rx_clkout[6] rx_clkout[5] rx_clkout[4] transceiver block gxbr1 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 transceiver block gxbr0 channel [3:0] rx data and status logic rx_coreclk[3] rx_coreclk[2] rx_coreclk[1] rx_coreclk[0] rx_clkout[3] rx_clkout[2] rx_clkout[1] rx_clkout[0] 2?68 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation user-selected receiver phase compensation fifo read clock the altgx megawizard plug-in manager provides an optional port named rx_coreclk for each instantiated receiver channel. if you enable this port, the quartus ii software does not automatically select the receiver phase compensation fifo read clock source. instead, the signal that you drive on the rx_coreclk port of the channel clocks the read side of its receiver phase compensation fifo. you can use the flexibility of selecting the receiver phase compensation fifo read clock to reduce the global, regional, or global and regional clock resource utilization. you can connect the rx_coreclk ports of all receiver channels in your design and drive them using a common clock driver that has a 0 ppm frequency difference with respect to the fifo write clocks of these channels. use this common clock driver to latch the receiver data and status signals in the fpga fabric for these channels. this fpga fabric-transceiver interface clocking scheme uses only one global, regional, or global and regional clock resource for all channels. example 8: sixteen identical channels across four transceiver blocks figure 2?37 shows 16 channels located across four transceiver blocks. the incoming serial data to all 16 channels has a 0 ppm frequency difference with respect to each other. the rx_coreclk ports of all 16 channels are connected together and driven by a common clock driver. this common clock driver also latches the receiver data and status logic of all 16 receiver channels in the fpga fabric. only one global, regional, or global and regional clock resource is used with this clocking scheme, compared to 16 global, regional, or global and regional clock resources needed without the rx_coreclk ports (the quartus ii software-selected receiver phase compensation fifo read clock). chapter 2: stratix iv transceiver clocking 2?69 fpga fabric-transceiver interface clocking ? march 2010 altera corporation stratix iv device handbook volume 2 common clock driver selection rules the common clock driver driving the rx_coreclk ports of all channels must have a 0 ppm frequency difference with respect to the receiver phase compensation fifo write clocks of these channels. if there is any frequency difference between the fifo read clock ( rx_coreclk ) and the fifo write clock, the fifo overflows or under-runs, resulting in corrupted data transfer between the fpga fabric and the receiver. figure 2?37. sixteen identical channels across four transceiver blocks for example 8 common clock driver channel [15:12] rx data and status logic rx_coreclk[15:12] rx_clkout[15:12] transceiver block gxbr3 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 transceiver block gxbr2 rx_clkout[11:8] rx_coreclk[11:8] channel [11:8] rx data and status logic fpga fabric channel [7:4] rx data and status logic transceiver block gxbr1 channel 3 channel 2 channel 1 channel 0 rx_clkout[7:4] rx_coreclk[7:4] channel [3:0] rx data and status logic rx_coreclk[3:0] rx_clkout[3:0] transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 2?70 chapter 2: stratix iv transceiver clocking fpga fabric-transceiver interface clocking stratix iv device handbook volume 2 ? march 2010 altera corporation table 2?17 lists the receiver phase compensation fifo write clocks that the quartus ii software selects in various configurations. to ensure that you understand the 0 ppm clock driver rule, the quartus ii software expects the following set of user assignments whenever you use the rx_coreclk port to drive the receiver phase compensation fifo read clock: gxb 0 ppm core clock setting 1 failing to make this assignment correctly when using the rx_coreclk port results in a quartus ii compilation error. the gxb 0 ppm core clock setting allows the following clock drivers to drive the rx_coreclk ports: tx_clkout in non-bonded channel configurations with rate matcher tx_clkout and rx_clkout in non-bonded configurations without rate matcher coreclkout in bonded channel configurations fpga clk input pins tr a n sc e iv er refclk pins clock output from left and right and top and bottom plls ( pll_l, pll_r , and pll_t , pll_b) 1 the quartus ii software does not allow gated clocks or clocks generated in fpga logic to drive the tx_coreclk ports. because the 0 ppm clock group assignment allows the fpga clk input pins and transceiver refclk pins as the clock driver, the quartus ii compiler cannot determine if there is a 0 ppm difference between the fifo write clock and read clock for each channel. table 2?17. receiver phase compensation fifo write clocks configuration receiver phase compensation fifo write clock without byte serializer with byte serializer non-bonded channel configuration with rate matcher low-speed parallel clock from the local clock divider in the associated channel ( tx_clkout ) divide-by-two version of the low-speed parallel clock from the local clock divider in the associated channel ( tx_clkout ) non-bonded channel configuration without rate matcher parallel recovered clock from the receiver pma in the associated channel ( rx_clkout ) divide-by-two version of the parallel recovered clock from the receiver pma in the associated channel ( rx_clkout ) 4-bonded channel configuration low-speed parallel clock from the cmu0 clock divider of the associated transceiver block ( coreclkout ) divide-by-two version of the low-speed parallel clock from the cmu0 clock divider of the associated transceiver block ( coreclkout ) 8-bonded channel configuration low-speed parallel clock from the cmu0 clock divider of the master transceiver block ( coreclkout from the master transceiver block) divide-by-two version of the low-speed parallel clock from the cmu0 clock divider of the master transceiver block ( coreclkout from the master transceiver block) chapter 2: stratix iv transceiver clocking 2?71 using the cmu/atx pll for clocking user logic in the fpga fabric ? march 2010 altera corporation stratix iv device handbook volume 2 1 you must ensure that the clock driver for all connected rx_coreclk ports has a 0 ppm difference with respect to the fifo write clock in those channels. table 2?18 lists the quartus ii assignments that you must make. for more implementation details, refer to ?configuration example 3: configuring sixteen channels across four transceiver blocks? on page 2?76 . basic (pma direct) mode in basic (pma direct) mode, each channel must be clocked by its own rx_clkout. as a result, the number of global and/or regional clock resources required is significantly higher. bonding is not supported for receivers configured in basic (pma direct) functional mode. using the cmu/atx pll for clocking user logic in the fpga fabric some designs that use multiple clock domains may run out of plls in the fpga fabric. in such a scenario, if your design has cmu or atx plls that are not being used, it may be possible to use them for clocking user logic in the fpga fabric. however, the cmu plls and atx plls do not have many features that are supported by the plls in the fpga fabric. the following are the supported features on cmu plls and atx plls used as plls for clocking user logic in the fpga fabric: single clock output programmable pll bandwidth pll pfd power down control lock status signal table 2?18. quartus ii assignments from full design hierarchy name of one of the following clock drivers that you choose to drive the rx_coreclk ports of all identical channels (1) : tx_clkout rx_clkout coreclkout fpga clk input pins transceiver refclk pins clock output from the left and right or top and bottom plls tx_dataout port of one of the identical channels to rx_datain pins of all channels whose rx_coreclk ports are connected together and driven by the 0 ppm clock driver. assignment name gxb 0 ppm core clock setting value on note to tab l e 2 ?1 8 : (1) you can find the full hierarchy name of the 0 ppm clock driver using the node finder feature in the quartus ii assignment editor. 2?72 chapter 2: stratix iv transceiver clocking using the cmu/atx pll for clocking user logic in the fpga fabric stratix iv device handbook volume 2 ? march 2010 altera corporation to use this feature, you must create an altgx instance with a single channel in transmitter only mode that uses the required cmu pll or atx pll. follow these steps to create the altgx instance: 1. choose basic (pma direct) n mode as the protocol. 2. select transmitter only operation mode. 3. select the input clock frequency. 4. select the appropriate values of data rate and channel width based on the desired output clock frequency. to generate a 250 mhz clock using an input clock frequency of 50 mhz, select a channel width of 10 and a data rate of 2500 mbps ( equation 2?1 ). 5. you can select the pll bandwidth by choosing tx pll bandwidth mode . 6. you can instantiate the pll_locked port to indicate the pll lock status. 7. you can instantiate pll_powerdown or gxb_powerdown to enable the pll pfd power down control. 8. use tx_clkout of the altgx instance as the clock source for clocking user logic in the fpga fabric. equation 2?1. channel width data rate f o u t = chapter 2: stratix iv transceiver clocking 2?73 configuration examples ? march 2010 altera corporation stratix iv device handbook volume 2 configuration examples this section describes the following examples: ?configuration example 1: configuring 24 channels in basic (pma direct) n mode in the ep4s100g5f45 device? on page 2?73 ?configuration example 2: configuring sixteen identical channels across four transceiver blocks? on page 2?75 ?configuration example 3: configuring sixteen channels across four transceiver blocks? on page 2?76 ?configuration example 4: configuring left and right, left, or right pll in vco bypass mode? on page 2?78 configuration example 1: configuring 24 channels in basic (pma direct) n mode in the ep4s100g5f45 device each transceiver block has four regular channels and two cmu channels that you can configure in basic (pma direct) n mode. the ep4s100g5f45 device has four transceiver blocks located on each side of the device allowing configuration of up to 24 channels in basic (pma direct) n mode. when all 24 channels on one side of the device are configured in basic (pma direct) n mode, all eight cmu channels (two in each transceiver block) are configured as pma-only channels. use the refclk pins in each of the four transceiver blocks as receiver serial data input pins and configure the cmu plls as receiver cdrs when the cmu channel is configured as a pma-only channel. due to the non-availability of cmu plls, you must use the 6g atx pll to generate the high-speed serial and low-speed parallel transceiver clocks for all 24 channels. due to the non-availability of a refclk pin, you must use the left and right, or left or right pll in vco bypass mode to provide the reference clock through the pll cascade clock line. for more information about left and right pll vco bypass mode, refer to ?configuration example 4: configuring left and right, left, or right pll in vco bypass mode? on page 2?78 . figure 2?38 shows 24 channels on the right side of the ep4s100g5f45 device configured in basic (pma direct) n mode running at 6.5 gbps with a 20-bit fpga fabric-pma interface width. because all 24 channels on the right side of the device are configured in basic (pma direct) n mode, the right pll_r1 configured in vco bypass mode is used to provide the input reference clock to the 6g atx pll. the 6g atx pll generates the high-speed serial and low-speed parallel transceiver clocks that are distributed to the 24 channels though the n_top and n_bottom clock network. because the data rate of 6.5 gbps requires a left and right, or left or right pll to meet fpga fabric-transmitter pma interface timing, tx_clkout from one of the 24 channels is phase shifted by 315 using pll_r2 . the phase shifted output clock from pll_r2 is used to clock the fpga fabric logic that generates the transmitter parallel data and control signals. 2?74 chapter 2: stratix iv transceiver clocking configuration examples stratix iv device handbook volume 2 ? march 2010 altera corporation figure 2?38. twenty-four channels on the right side of the ep4s100g5f45 device configured in basic (pma direct) n mode for configuration example 1 (note 1) note to figure 2?38 : (1) the green line represents the pll cascade clock line and the blue lines represent the 6g atx pll block. channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 atx pll r0 (6g) channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 atx pll r1 (6g) channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 xn_bottom xn_top transceiver block gxbr 0 transceiver block gxbr 1 transceiver block gxbr 2 channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 transceiver block gxbr 3 atx pll r2 (10g) pll_r1 (vco bypass mode) pll_r2 (phase shift 315o to meet interface timing) dedicated fpga clk pin pll cascade clock line reference clock tx_clkout fpga fabric (transmitter data generation logic) fpga fabric (transmitter data generation logic) chapter 2: stratix iv transceiver clocking 2?75 configuration examples ? march 2010 altera corporation stratix iv device handbook volume 2 configuration example 2: configuring sixteen identical channels across four transceiver blocks 1 this example relates to ?user-selected receiver phase compensation fifo read clock? on page 2?68 . figure 2?39 shows 16 identical transmitter channels located across four transceiver blocks. the tx_coreclk ports of all 16 transmitter channels are connected together and driven by the tx_clkout[4] signal from channel 0 in transceiver block gxbr1. the tx_clkout[4] signal also drives the transmitter data and control logic of all 16 transmitter channels in the fpga fabric. with this clocking scheme, only one global clock resource is used by the tx_clkout[4] signal. figure 2?39. sixteen identical channels across four transceiver blocks for configuration example 2 channel [15:12] tx data and control logic tx_coreclk[15:12] transceiver block gxbr3 channel 3 channel 2 channel 1 channel 0 tx_clkout[12] transceiver block gxbr2 channel 3 channel 2 channel 1 channel 0 tx_clkout[8] tx_coreclk[11:8] channel [11:8] tx data and control logic fpga fabric tx_coreclk[7:4] transceiver block gxbr1 channel 3 channel 2 channel 1 channel 0 transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 tx_clkout[0] tx_coreclk[3:0] channel [3:0] tx data and control logic tx_clkout[4] channel [7:4] tx data and control logic 2?76 chapter 2: stratix iv transceiver clocking configuration examples stratix iv device handbook volume 2 ? march 2010 altera corporation table 2?19 lists the quartus ii assignments that you must make for the clocking scheme shown in figure 2?38 . configuration example 3: configuring sixteen channels across four transceiver blocks 1 this example relates to ?user-selected receiver phase compensation fifo read clock? on page 2?68 . figure 2?40 shows 16 non-bonded channels without rate matcher located across four transceiver blocks. the incoming serial data to all 16 channels has a 0 ppm frequency difference with respect to each other. the rx_coreclk ports of all 16 channels are connected together and driven by rx_clkout[9] in transceiver block gxbr2. rx_clkout[9] also clocks the receiver data and status signals of all 16 channels in the fpga fabric. with this clocking scheme, only one global, regional, or global and regional clock resource is used by rx_clkout[9]. table 2?19. quartus ii assignments from top_level/top_xcvr_instance1/altgx_component/tx_clkout[4] (1) to tx_dataout[15..0] assignment name gxb 0 ppm core clock setting value on note to tab l e 2 ?1 9 : (1) this is an example design hierarchy path for the tx_clkout[4] signal. chapter 2: stratix iv transceiver clocking 2?77 configuration examples ? march 2010 altera corporation stratix iv device handbook volume 2 figure 2?40. sixteen channels across four transceiver blocks for configuration example 3 channel [15:12] rx data and status logic rx_coreclk[15:12] transceiver block gxbr3 channel 3 channel 2 channel 1 channel 0 transceiver block gxbr2 channel 3 channel 2 channel 1 channel 0 rx_clkout[11:8] rx_coreclk[11:8] channel [11:8] rx data and status logic fpga fabric channel [7:4] rx data and status logic rx_coreclk[7:4] rx_clkout[7:4] transceiver block gxbr1 channel 3 channel 2 channel 1 channel 0 transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 rx_clkout[3:0] rx_coreclk[3:0] channel [3:0] rx data and status logic rx_clkout[15:12] rx_clkout[9] 2?78 chapter 2: stratix iv transceiver clocking configuration examples stratix iv device handbook volume 2 ? march 2010 altera corporation table 2?20 lists the quartus ii assignments that you must make for the clocking scheme shown in figure 2?40 . configuration example 4: configuring left and right, left, or right pll in vco bypass mode 1 this example relates to ?left and right, left, or right pll in vco bypass mode? on page 2?17 . to configure the left and right, left, or right pll in vco bypass mode, use the following steps: 1. under the general/modes tab, enter the desired input reference clock frequency. a. under pll type , select left_right_pll. b. under operation mode, select the with no compensation option ( figure 2?41 ). table 2?20. quartus ii assignments for appendix example 4 from top_level/top_xcvr_instance1/altgx_component/rx_clkout[9] (1) to rx_datain[15..0] assignment name gxb 0 ppm core clock setting value on note to tab l e 2 ?2 0 : (1) this is an example design hierarchy path for the rx_clkout[9] signal. figure 2?41. no compensation option used for configuration example 4 chapter 2: stratix iv transceiver clocking 2?79 configuration examples ? march 2010 altera corporation stratix iv device handbook volume 2 2. under the inputs/lock tab, select create output file(s) using the 'advanced' pll parameters ( figure 2?42) . figure 2?42. create output file(s) using the ?advanced? pll parameters option use for configuration example 4 2?80 chapter 2: stratix iv transceiver clocking configuration examples stratix iv device handbook volume 2 ? march 2010 altera corporation 3. under the output clocks tab turn off use this clock for clk c0. 4. turn on use this clock for clk c1 ( figure 2?43 ). 1 the vco bypass option is only enabled for clock output c1. 5. click finish for the megawizard plug-in manager to generate the verilog .v file for the altpll instantiation. next, from the command line, go to the directory where you have the altpll instance files ( .v or .vhd ) and type the following command: >> qmegawiz -silent -wiz_override="c1_test_source=1,c1_mode=bypass,clk1_counter=c1" < altpll design file > this command places your altpll instance in vco bypass mode. connect the clk c1 output of the left and right, left, or right pll to the input reference clock port of the 6g atx pll used to generate the transceiver clocks. figure 2?43. use this clock option used for configuration example 4 chapter 2: stratix iv transceiver clocking 2?81 document revision history ? march 2010 altera corporation stratix iv device handbook volume 2 document revision history table 2?21 shows the revision history for this chapter. table 2?21. document revision history date and document version changes made summary of changes march 2010, v3.1 updated ta bl e 2? 4 . updated figure 2?7 , figure 2?8 , figure 2?16 , and figure 2?21 . updated the ?transceiver channel datapath clocking? and ?configuration example 3: configuring sixteen channels across four transceiver blocks? sections. added a note to the ?refclk0 and refclk1 pins? section. changed ?datapath clocks? to ?datapath interface clocks?. minor text edits. ? november 2009, v3.0 added figure 2?1, figure 2?12,and figure 2?13. added table 2?1, table 2?2, table 2?8, and table 2?2. updated table 2?5 and table 2?14. updated all graphics. updated all sections. added stratix iv gt information. re-organized information. minor text edits. ? june 2009, v2.2 updated figure 2?5 and figure 2?7. updated the ?transceiver data rates supported in basic (pma direct) mode?, , ?fpga fabric plls-transceiver plls cascading in the 780-pin package?, ?fpga fabric plls-transceiver plls cascading in the 1152-pin package?, sections. removed table 2-5, table 2-6, table 2-7 removed figure 2-17 and figure 2-18. minor text edits. ? march 2009, v2.1 minor updates. ? november 2008, v2.0 update to chapter. ? may 2008 v1.0 initial release. ? 2?82 chapter 2: stratix iv transceiver clocking document revision history stratix iv device handbook volume 2 ? march 2010 altera corporation ? november 2009 altera corporation stratix iv device handbook volume 2 3. configuring multiple protocols and data rates in a transceiver block use this chapter to create transceiver instances and understand how to combine transceiver channels. the instances you can combine include receiver only and transmitter and receiver channels as well as channels configured in protocol functional modes, channels using pll cascade clocks, channels in multiple transceiver blocks, and channels with a basic (pma direct) configuration. this chapter also offers several examples of sharing the clock multiplier unit phase-locked loops (cmu plls). f for information about the supported data rate range for the atx pll, refer to the ?transceiver performance specifications? section in the dc and switching characteristics chapter. overview each transceiver channel in a stratix ? iv gx device can run at an independent data rate or in an independent protocol mode. within each transceiver channel, the transmitter and receiver channels can run at different data rates. each transceiver block consists of two cmu plls that provide clocks to all the transmitter channels within the transceiver block. each receiver channel contains a dedicated clock data recovery (cdr) unit. in addition to the cmu plls, the auxiliary transmit (atx) plls are available to provide clocks to the transmitter channels that are configured for a specific data rate range. this chapter includes the following sections: ?glossary of terms? on page 3?2 ?creating transceiver channel instances? on page 3?3 ?general requirements to combine channels? on page 3?3 ?sharing cmu plls? on page 3?5 ?sharing atx plls? on page 3?9 ?combining receiver only channels? on page 3?9 ?combining transmitter channel and receiver channel instances? on page 3?10 ?combining transceiver instances in multiple transceiver blocks? on page 3?12 ?combining transceiver instances using pll cascade clocks? on page 3?15 ?combining channels configured in protocol functional modes? on page 3?16 ?combining transceiver channels with basic (pma direct) configuration? on page 3?24 ?combination requirements when channel reconfiguration is enabled? on page 3?41 siv52003-4.0 3?2 chapter 3: configuring multiple protocols and data rates in a transceiver block glossary of terms stratix iv device handbook volume 2 ? november 2009 altera corporation ?combining transceiver channels when the adaptive equalization (aeq) is enabled? on page 3?46 ?combination requirements for stratix iv gt devices? on page 3?48 ?summary? on page 3?49 each transmitter channel has a local divider (/1, /2, or /4) that divides the high clock output of the cmu pll to provide high-speed serial and low-speed parallel clocks for its physical coding sublayer (pcs) and physical medium attachment (pma) functional blocks. you can configure the rx cdr present in the receiver channel to a distinct data rate and provide separate input reference clocks. each receiver channel also contains a local divider that divides the high-speed clock output of the rx cdr and provides clocks for its pcs and pma functional blocks. to enable transceiver channel settings, the quartus ? ii software provides the altgx megawizard tm plug-in manager interface. the altgx megawizard plug-in manager allows you to instantiate a single transceiver channel or multiple transceiver channels in receiver and transmitter , receiver only , and transmitter only configurations. glossary of terms table 3?1 lists the terms used in the chapter. f for more information about transceiver channel set up using a basic (pma direct) n configuration, refer to the stratix iv gx transceiver clocking chapter. tab le 3 ?1 . glossary of terms used in this chapter configuration description regular channels this refers to the four transceiver channels in each transceiver block that contain pcs. basic (pma direct) this refers to the basic (pma direct) configuration that you can use for both regular and cmu channels. basic (pma direct) mode has two variations, 1 and n. the term ?basic (pma direct)? used in this chapter refers to both 1 and n and to regular/cmu channels. any specific reference to 1 and n or regular/cmu channels is stated explicitly. non-basic (pma direct) this term refers to all single channel non-bonded configurations (for example, gige, pci express [pipe] 1) or bonded channel configurations that have pcs enabled (for example, basic 4 and 8, xaui, pci express [pipe] 4 and 8). also, any reference to a channel in non-basic (pma direct) mode indicates that the channel is a regular transceiver channel. basic (pma direct) 1 a transceiver channel set up in this configuration uses the high-speed serial clock from the cmu pll that is present within the same transceiver block. you can select this configuration by setting the which protocol you will be using? option to basic (pma direct) and the which sub protocol you will be using? option to none . basic (pma direct) n a transceiver channel set up in this configuration uses the n high-speed clock lines. you can select this configuration by setting the which protocol you will be using? option to basic (pma direct) and the which sub protocol you will be using? option to n . chapter 3: configuring multiple protocols and data rates in a transceiver block 3?3 creating transceiver channel instances ? november 2009 altera corporation stratix iv device handbook volume 2 creating transceiver channel instances the two ways you can instantiate multiple transceiver channels in the general screen of the altgx megawizard plug-in manager are: in the what is the number of channels? option, select the required value. this method creates all the transceiver channels with identical configurations. for examples, refer to ?combining transceiver instances in multiple transceiver blocks? on page 3?12 . in the what is the number of channels? option, select 1 and create a single channel transceiver instance. to instantiate additional transceiver channels with an identical configuration, select the created altgx instance multiple times. if you need additional transceiver channels with different configurations, create separate altgx megafunction instances with different settings and use them in your design. when you create instances using the above methods, you can force the placement of up to four transceiver channels within the same transceiver block. do this by assigning the tx_dataout and rx_datain ports of the channel instances to a single transceiver bank. if you do not assign pins to the tx_dataout and rx_datain ports, the quartus ii software chooses default pin assignments. when you compile the design, the quartus ii software combines multiple channel instances within the same transceiver block if the instances meet specific requirements. the following sections explain these requirements for different transceiver configurations. general requirements to combine channels when you create multiple altgx instances, the quartus ii software requires you to set identical values for the following parameters and signals to combine the altgx instances within the same transceiver block or in transceiver blocks on the same side of the device. the following sections describe these requirements. transmitter buffer voltage (v cch ) the stratix iv gx device provides you the option to select 1.4 v or 1.5 v for the v cch supply through the altgx megawizard plug-in manager. to combine the channel instances within the same transceiver block, the quartus ii software requires you to set the same v cch value in all the channel instances. 1 the data rate of the transmitter channel is limited based on the v cch value selected. f for the data rate restrictions, refer to the dc and switching characteristics chapter. transceiver analog power (v cca_l/r ) the stratix iv gx device contains two different power supply pins, vcca_l and vcca_r , that provide power to the pma blocks in all the transceiver channels on the left and right sides of the device, respectively. 3?4 chapter 3: configuring multiple protocols and data rates in a transceiver block general requirements to combine channels stratix iv device handbook volume 2 ? november 2009 altera corporation the stratix iv gx device provides you the option to select 2.5 v or 3.0 v for the vcca_l/r supply through the altgx megawizard plug-in manager. you must set the same vcca_l/r value for all the transceiver channel instances to enable the quartus ii software to place them in the transceiver blocks on the same side of the device. for example, if you have two altgx instances that you would like to place on the left side transceiver banks gxbl0 and gxbl1 , the vcca_l/r values in the two altgx instances must be the same. 1 the data rate of the transceiver channel is limited based on the v cca_l/r value selected. f for the data rate restrictions, refer to the dc and switching characteristics chapter. control signals this section contains information about the gxb_powerdown , reconfig_fromgxb, and reconfig_togxb ports. gxb_powerdown port the gxb_powerdown port is an optional port that you can enable in the altgx megawizard plug-in manager. if enabled, you must drive the gxb_powerdown port in the altgx instances from the same logic or the same input pin to enable the quartus ii software to assign them in the same transceiver block. reconfig_fromgxb and reconfig_togxb ports in the altgx megawizard plug-in manager, the reconfig_fromgxb and reconfig_togxb ports are enabled if you select one of the following options in the reconfig screen: analog controls (vod, pre-emphasis, manual equalization, eyeq) enable channel and transmitter pll reconfiguration offset cancellation for receiver channels (always enabled if the configuration is transmitter and receiver or receiver only ) 1 to combine multiple instances within the same transceiver block: the reconfig_fromgxb ports must be enabled in each instance and these ports must be connected to the same reconfig controller for example, consider that you want to place a receiver only and transmitter only instance in the same transceiver block. for the receiver only instance, the quartus ii software automatically enables the reconfig_fromgxb port. for the transmitter only instance, you must select the options in the reconfig screen (mentioned above) to enable the reconfig_fromgxb port. in the design, connect these ports from the transmitter only and receiver only instance to the same reconfig controller. f for more information about connecting these ports to the dynamic reconfiguration controller, refer to the ?connecting the altgx and altgx_reconfig instances? section of the stratix iv dynamic reconfiguration chapter. chapter 3: configuring multiple protocols and data rates in a transceiver block 3?5 sharing cmu plls ? november 2009 altera corporation stratix iv device handbook volume 2 calibration clock and power down each calibration block in a stratix iv gx device is shared by multiple transceiver blocks. if your design uses multiple transceiver blocks, depending on the transceiver banks selected, you must connect the cal_blk_clk and cal_blk_powerdown ports of all channel instances to the same input pin or logic. f for more information about the calibration block and transceiver banks that are connected to a specific calibration block, refer to the ?calibration blocks? section in the stratix iv transceiver architecture chapter. 1 asserting the cal_blk_powerdown port affects calibration on all transceiver channels connected to the calibration block. sharing cmu plls when you create multiple transceiver channel instances using cmu plls and intend to combine these instances in the same transceiver block, the quartus ii software checks whether a single cmu pll can be used to provide clock outputs for the transmitter side of the channel instances. if a single cmu pll is not sufficient, the quartus ii software attempts to combine the channel instances using two cmu plls. otherwise, the quartus ii software issues a fitter error. the following two sections describes the altgx instance requirements to enable the quartus ii software to share the cmu pll. multiple channels sharing a cmu pll to enable the quartus ii software to share the same cmu pll for multiple channels, the following parameters in the channel instantiations must be identical: ?base data rate? (the cmu pll is configured for this data rate) cmu pll bandwidth setting reference clock frequency input reference clock pin pll_powerdown port of the altgx instances must be driven from the same logic if the selected functional mode in one instance is (oif) cei phy interface or pci express (pipe), the other instance must have the same functional mode to share the cmu pll. for example, if you have two channels, one configured in basic mode and the other configured in (oif) cei phy interface mode at the same data rate, the quartus ii software does not share the same pll because the internal parameters for these two functional modes are different. each channel instance can have a different local divider setting. this is a useful option when you intend to run each channel within the transceiver block at different data rates that are derived from the same base data rate using the local divider values /1, /2, and /4. example 1 shows this design configuration. 3?6 chapter 3: configuring multiple protocols and data rates in a transceiver block sharing cmu plls stratix iv device handbook volume 2 ? november 2009 altera corporation example 1 consider an example design with four instances of receiver and transmitter configuration in the same transceiver block at various serial data rates. assume that each instance contains a channel and is driven from the same clock source and has the same cmu pll bandwidth settings. table 3?2 shows the configuration for example 1. for example 1, you can share a single cmu pll for all four channels because: one cmu pll can be configured to run at 4.25 gbps. each channel can divide the cmu pll clock output using the local divider and achieve the required data rates of 4.25 gbps, 2.125 gbps, and 1.0625 gbps. because each receiver channel has a dedicated cdr, the receiver side in each instance can be set up for these three data rates without any restrictions. to enable the quartus ii software to share a single cmu pll for all four channels, set the values shown in table 3?3 in the general screen of the altgx megawizard plug-in manager. tab le 3 ?2 . configuration for example 1 user-created instance name altgx megawizard plug-in manager settings number of channels configuration effective data rate inst0 1 receiver and transmitter 4.25 gbps inst1 1 receiver and transmitter 2.125 gbps inst2 1 receiver and transmitter 1.0625 gbps inst3 1 receiver and transmitter 4.25 gbps tab le 3 ?3 . altgx megawizard plug-in manager settings for example 1 instance general screen option setting inst0 what is the effective data rate? 4.25 gbps specify base data rate 4.25 gbps (1) inst1 what is the effective data rate? 2.125 gbps specify base data rate 4.25 gbps (1) inst2 what is the effective data rate? 1.0625 gbps specify base data rate 4.25 gbps (1) inst3 what is the effective data rate? 4.25 gbps specify base data rate 4.25 gbps (1) note to tab l e 3 ?3 : (1) the specify base data rate option is 4.25 gbps for all four instances. given that the cmu pll bandwidth setting and input reference clock are the same and that the pll_powerdown ports are driven from the same logic or pin, the quartus ii software shares a single cmu pll that runs at 4.25 gbps. chapter 3: configuring multiple protocols and data rates in a transceiver block 3?7 sharing cmu plls ? november 2009 altera corporation stratix iv device handbook volume 2 you can force the placement of transceiver channels to a specific transceiver block by assigning pins to tx_dataout and rx_datain . otherwise, the quartus ii software selects a transceiver bank. figure 3?1 and figure 3?2 show the scenario before and after the quartus ii software combines the transceiver channel instances. because the rx cdr is not shared between channels, only the cmu pll is shown. 1 each of the altgx instances has a pll_powerdown port. you must drive the pll_powerdown ports for all the instances from the same logic to enable the quartus ii software to share the same cmu pll. figure 3?1. altgx instances before compilation for example 1 altgx effective data rate: 4.25 gbps cmu pll base data rate: 4.25 gbps inst 0 altgx effective data rate: 2.125 gbps cmu pll base data rate: 4.25 gbps inst 1 altgx effective data rate: 1.0625 gbps cmu pll base data rate: 4.25 gbps inst 2 altgx effective data rate: 4.25 gbps cmu pll base data rate: 4.25 gbps inst 3 3?8 chapter 3: configuring multiple protocols and data rates in a transceiver block sharing cmu plls stratix iv device handbook volume 2 ? november 2009 altera corporation figure 3?2 show the scenario after the quartus ii software combines the transceiver channel instances. example 2 consider the example design shown in table 3?4 . when you have two instances with the same serial data rate but with different cmu pll data rates, the quartus ii software creates a separate cmu pll for the two instances. 1 even though the effective data rate of inst1 is 2.5 gbps (5 gbps/2 = 2.5 gbps), the same as inst0 , when you compile the design, the quartus ii software requires two cmu plls to provide clocks for the transmitter side of the two instances because their base data rates are different. in this example, you have the third instance, inst2, that requires a third cmu pll. therefore, the quartus ii software cannot combine the above three instances within the same transceiver block. figure 3?2. combined instances after compilation for example 1 transceiver block inst 0 effective data rate: 4.25 gbps tx loc div: /1 inst 1 inst 2 inst 3 effective data rate: 2.125 gbps tx loc div: /2 effective data rate: 1.0625 gbps tx loc div: /4 effective data rate: 4.25 gbps tx loc div: /1 cmu pll base data rate: 4.25 gbps tab le 3 ?4 . configuration for example 2 user-created instance name altgx megawizard plug-in manager settings number of channels configuration effective data rate base data rate inst0 1 receiver and transmitter 2.5 gbps 2.5 gbps inst1 1 receiver and transmitter 2.5 gbps 5 gbps inst2 1 receiver and transmitter 1 gbps 1 gbps chapter 3: configuring multiple protocols and data rates in a transceiver block 3?9 sharing atx plls ? november 2009 altera corporation stratix iv device handbook volume 2 sharing atx plls the quartus ii software allows you to share the same atx pll for multiple transceiver instances if the following requirements are met: the atx pll bandwidth in both instances are the same if the selected functional mode in one instance is (oif) cei phy interface or pci express (pipe), the other functional modes must be the same to share the atx pll. for example, if you have two channels, one configured in basic mode and the other configured in (oif) cei phy interface mode at the same data rate, the quartus ii software does not share the same pll because the internal parameters for these two functional modes are different. the base data rate and effective data rate values are the same. the pll_powerdown port in the instances are connected to the same logic. the instances are placed on the same side of the device. there is no contention on the n clock lines from the atx pll and the two instances. 1 for more information about n clocking, refer to the ?transmitter channel data path clocking? section in the stratix iv transceiver clocking chapter. combining receiver only channels you can selectively use the receiver in the transceiver channel by selecting the receiver only configuration in the what is the operating mode? option on the general screen of the altgx megawizard plug-in manager. you can combine receiver only channel instances of different configurations and data rates into the same transceiver block. because each receiver channel contains its own dedicated cdr, each receiver only instance (assuming one receiver channel per instance) can have a different data rate. 1 for the quartus ii software to combine the receiver only instances within the same transceiver block, you must connect gxb_powerdown (if used) for all the channel instances to the same logic or input pin. for more information, refer to ?general requirements to combine channels? on page 3?3 . 1 if your design contains a receiver only instance, the quartus ii software disables all the settings for the unused transmitter channel present in the same physical transceiver channel. therefore, the unused transmitter channel is always powered down in the hardware. 3?10 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transmitter channel and receiver channel instances stratix iv device handbook volume 2 ? november 2009 altera corporation combining transmitter channel and receiver channel instances you can create separate transmitter and receiver channel instances and assign the tx_dataout and rx_datain pins of the transmitter and receiver instances, respectively, to the same physical transceiver channel. this configuration is useful when you intend to run the transmitter and receiver channel at different serial data rates. to create separate transmitter and receiver channel instances, select the transmitter only and receiver only options in the operating mode ( general screen) of the altgx megawizard plug-in manager. multiple transmitter channel and receiver channel instances the quartus ii software allows you to combine multiple transmitter only and receiver only channel instances within the same transceiver block. based on the pin assignments, the quartus ii software combines the corresponding transmitter only and receiver only channels in the same physical channel. to enable the quartus ii software to combine the transmitter channel and receiver channel instances in the same transceiver block, follow the rules and requirements outlined in: ?general requirements to combine channels? on page 3?3 ?multiple channels sharing a cmu pll? on page 3?5 ?combining receiver only channels? on page 3?9 example 3 consider the example design shown in table 3?5 with four altgx instances. after you create the above instances, if you force the placement of the instances, as shown in table 3?6 , the quartus ii software combines inst0 and inst1 to physical channel 0, and inst2 and inst3 to physical channel 1. tab le 3 ?5 . four altgx instances for example 3 instance name configuration serial data rate input reference clock frequency inst0 transmitter only 3.125 bps 156.25 mhz inst1 receiver only 2.5 gbps 156.25 mhz inst2 transmitter only 1.25 gbps 125 mhz inst3 receiver only 2 gbps 125 mhz tab le 3 ?6 . forced placement of the instances for example 3 instance name physical channel pin assignments in the same transceiver block inst0 tx pin of channel 0 inst1 rx pin of channel 0 inst2 tx pin of channel 1 inst3 rx pin of channel 1 chapter 3: configuring multiple protocols and data rates in a transceiver block 3?11 combining transmitter channel and receiver channel instances ? november 2009 altera corporation stratix iv device handbook volume 2 figure 3?3 and figure 3?4 show the transceiver channel instances before and after compilation. figure 3?3. altgx transceiver channel instances before compilation for example 3 altgx effective data rate: 3.125 gbps cmu pll base data rate: 3.125 gbps inst 0 altgx rx cdr base data rate: 2.5 gbps inst 1 altgx effective data rate: 1.25 gbps cmu pll base data rate: 1.25 gbps inst 2 altgx rx cdr base data rate: 2 gbps inst 3 3?12 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver instances in multiple transceiver blocks stratix iv device handbook volume 2 ? november 2009 altera corporation figure 3?4 shows the transceiver channel instances after compilation. combining transceiver instances in multiple transceiver blocks the method to instantiate multiple transceiver channels using a single altgx instance was described in ?creating transceiver channel instances? on page 3?3 . the following section describes the method to instantiate multiple transceiver channels using multiple transceiver blocks. when you create a transceiver instance that has more than four transceiver channels (assuming that the instance is created in non-basic (pma direct) functional mode which requires regular channels), the quartus ii software attempts to combine the transceiver channels in multiple transceiver blocks. this is shown in the following examples. figure 3?4. combined transceiver instances after compilation for example 3 transceiver block inst 0 effective data rate: 3.25 gbps tx loc div: /1 inst 1 effective data rate: 2.5 gbps cmu pll base data rate: 3.125 gbps cmu pll base data rate: 1.25 gbps transceiver channel0 inst 2 tx channel effective data rate: 1.25 gbps tx loc div: /1 inst 3 effective data rate: 2 gbps transceiver channel1 tx channel rx channel rx channel chapter 3: configuring multiple protocols and data rates in a transceiver block 3?13 combining transceiver instances in multiple transceiver blocks ? november 2009 altera corporation stratix iv device handbook volume 2 example 4 consider the design example configuration shown in table 3?7 with two altgx instances. in this case, assuming that all the required parameters specified in ?multiple channels sharing a cmu pll? on page 3?5 are identical for inst0 and inst1 , the quartus ii software fits inst0 and inst1 in two transceiver blocks. figure 3?5 and figure 3?6 show the transceiver instances before and after compilation. tab le 3 ?7 . two altgx instances for example 4 instance name number of transceiver channels configuration serial data rate input reference clock inst0 7 receiver and transmitter 4.25 gbps 125 mhz from refclk0 inst1 1 receiver and transmitter 4.25 gbps 125 mhz from refclk0 (same as inst0 ) figure 3?5. transceiver channel instances before compilation for example 4 inst0 effective data rate: 4.25 gbps input clock frequency: 125 mhz n umber of channels: 7 inst1 effective data rate: 4.25 gbps input clock frequency: 125 mhz n umber of channels: 1 3?14 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver instances in multiple transceiver blocks stratix iv device handbook volume 2 ? november 2009 altera corporation figure 3?6 shows the transceiver instances after compilation. you can force the placement of the transceiver channels in specific transceiver banks by assigning pins to the tx_dataout and rx_datain ports of inst0 and inst1. even though inst0 instantiates seven transceiver channels, the altgx megawizard plug-in manager provides only a one-bit wide pll_inclk port for inst0 . in your design, provide only one clock input for the pll_inclk port. the quartus ii software uses two transceiver blocks to fit the seven channels and internally connects the input reference clock (connected to the pll_inclk port in your design) to the cmu plls of two transceiver blocks. figure 3?6. combined transceiver instances after compilation for example 4 transceiver block 0 ch3 of inst0 effective data rate: 4.25 gbps ch2 of inst0 effective data rate: 4.25 gbps cmu pll base data rate: 4.25 gbps effective data rate: 4.25 gbps ch1 of inst0 ch0 of inst0 effective data rate: 4.25 gbps transceiver block 1 effective data rate: 4.25 gbps ch0 of inst1 effective data rate: 4.25 gbps ch6 of inst0 cmu pll base data rate: 4.25 gbps effective data rate: 4.25 gbps ch5 of inst0 effective data rate: 4.25 gbps ch4 of inst0 chapter 3: configuring multiple protocols and data rates in a transceiver block 3?15 combining transceiver instances using pll cascade clocks ? november 2009 altera corporation stratix iv device handbook volume 2 1 for inst1 , the altgx megawizard plug-in manager provides a pll_inclk port. in this example, it is assumed that a single reference clock is provided for inst0 and inst1 . therefore, connect the pll_inclk port of inst0 and inst1 to the same input reference clock pin. this enables the quartus ii software to share a single cmu pll in transceiver block 1 that has three channels of inst0 and one channel of inst1 (shown as ch4, ch5, and ch6 in transceiver block 1 in figure 3?6 ). for the rx cdrs in inst0 , the altgx megawizard plug-in manager provides seven bits for the rx_cruclk port (if you do not select the train receiver cdr from pll_inclk option in the pll/ports screen). this allows separate input reference clocks to the rx cdrs of each channel. combining transceiver instances using pll cascade clocks the stratix iv gx transceiver has the ability to cascade the output of the general purpose plls ( pll_l and pll_r ) to the cmu plls, atx plls, and receiver cdrs. the left side plls can only be cascaded with the transceivers on the left side of the device. similarly, the right side plls can only be cascaded with the transceivers on the right side of the device. each side of the stratix iv gx device contains a pll cascade clock network; a single line network that connects the pll cascade clock to the transceiver block. this clock line is segmented to allow different pll cascade clocks to drive the transceiver cmu plls, atx plls, and rx cdrs. within the same segment, only a single pll_l/pll_r can drive these transceiver plls/cdrs. therefore, if you create two instances that use different plls for cascading, you cannot place these instances within the transceiver block. the segmentation locations differ based on the device family. f for more information about using the pll cascade clock and segmentation, refer to the ?dedicated left and right pll cascade lines network? section in the stratix iv transceiver clocking chapter. 3?16 chapter 3: configuring multiple protocols and data rates in a transceiver block combining channels configured in protocol functional modes stratix iv device handbook volume 2 ? november 2009 altera corporation combining channels configured in protocol functional modes this section describes how to combine channels for various protocol functional modes. combining channels in bonded functional modes this section describes the combination requirements in the two variations of bonded functional modes using transceiver pcs blocks. the two bonded functional modes are: ?bonded 4 functional mode? on page 3?16 ?examples of bonded 4 mode: basic mode with sub protocol set to 4 xaui pci express (pipe) mode with sub protocol set to gen1 4 or gen2 4. ?bonded x8 functional mode? on page 3?19 ?examples of bonded 8 mode: basic mode with sub protocol 8 pci express (pipe) mode with sub protocol 8 bonded 4 functional mode the combination requirements for basic x4, deterministic latency 4, and pci express (pipe) x4 functional modes (if pci express hard ip block is not used) are similar. in this mode, the transmitter channels are synchronized to reduce skew. the quartus ii software shares the control from physical transmitter channel 0 with the other transmitter channels in the transceiver block. therefore, when you an create an instance in this mode, the logical transmit channel 0 ( tx_dataout[0] in the instance) must be assigned by the physical channel location 0 in the transceiver block. the central clock divider block in the cmu0 channel forwards the high-speed serial and low-speed parallel clocks to the transmitter channels. f this clocking scheme is described in the ?bonded channel configurations? section of the stratix iv transceiver clocking chapter. because you used the central clock divider, the are two restrictions on the channel combinations: 1. if you configure channels in bonded 4 functional mode, the remaining transmitter channels (regular or cmu channels) within the transceiver block can be used only in basic (pma direct) 1 or n mode. chapter 3: configuring multiple protocols and data rates in a transceiver block 3?17 combining channels configured in protocol functional modes ? november 2009 altera corporation stratix iv device handbook volume 2 1 if pci express (pipe) functional mode uses the pci express hard ip block, the combination requirements are different. for more information, refer to ?combining channels using the pci express hard ip block with other channels? on page 3?23 . the receiver channels are clocked independently. therefore, you can configure the unused receiver channels within a transceiver block in any allowed configuration. examples of supported and unsupported combinations are shown in figure 3?7 . the cmu0 pll or cmu1 pll can drive the central clock divider block in the cmu0 channel. in cases where you use cmu1 pll for bonded 4 mode, the quartus ii software does not allow you to use cmu0 pll for any other configuration because part of the cmu0 channel (the central clock divider) is already used by the bonded 4 functional mode. using the remaining channels in basic (pma direct) 1 or n mode depends on the following conditions. 1. if cmu1 pll is available for clock generation, you can use the remaining transmitter channels in the transceiver block in basic (pma direct) 1 configuration. 2. if you want to configure the remaining transmitter channels at the same data rate as the bonded 4 functional mode, you can configure the remaining transmitter channels in basic (pma direct) 1 mode. the requirements are specified in ?sharing cmu plls? on page 3?5 and ?general requirements to combine channels? on page 3?3 . figure 3?7. examples of supported and unsupported configurations to combine instances in basic 4 mode transceiver block transceiver block instance 0 2 regular channels receiver and transmitter basic mode and 4 sub-protocol instance 1 2 regular channels receiver only (any functional mode) supported configuration instance 0 3 regular channels receiver and transmitter basic mode and 4 sub-protocol instance 1 1 cmu channel transmitter and receiver (basic [pma direct] xn functional mode) supported configuration transceiver block instance 0 2 regular channels receiver and transmitter basic mode and 4 sub-protocol instance 1 2 regular channels transmitter only (any mode other than basic [pma direct] mode) red: unsupported unsupported configuration 3?18 chapter 3: configuring multiple protocols and data rates in a transceiver block combining channels configured in protocol functional modes stratix iv device handbook volume 2 ? november 2009 altera corporation 3. if all the regular channels are configured in bonded 4 functional mode, you can configure the transmitter side of the cmu0 channel in basic (pma direct) n mode in single-width configuration only (double-width configuration is not supported). you can use the cmu1 channel in basic (pma direct) n single-width or double-width configuration. 1 this only applies to the transmitter side and not the receiver side of the cmu channel. 4. using the receiver side of the cmu channels depends on whether you use cmu1 pll or cmu0 pll to generate clocks for the bonded 4 functional mode. if the cmu pll within the corresponding cmu channel is not available to perform cdr functionality, you cannot configure it as a receiver. 5. if you use atx pll to generate clocks for the 4 bonded functional mode, you can use both the transmitter and receiver side of the cmu0 and cmu1 channels. you must satisfy the requirements specified in number 3. figure 3?8 shows a configuration in which all the transmitter channels in the transceiver block are used. 1 for xaui, the option to select atx pll is not available. chapter 3: configuring multiple protocols and data rates in a transceiver block 3?19 combining channels configured in protocol functional modes ? november 2009 altera corporation stratix iv device handbook volume 2 figure 3?8 shows the combination of basic/pci express (pipe) x4 functional mode with basic (pma direct) xn mode within the same transceiver block. bonded x8 functional mode bonded 8 functional mode is similar to bonded 4 functional mode except that the controls are shared from the physical channel 0 of the master transceiver block. the master is the lower of the two adjacent transceiver blocks selected for the 8 configuration. therefore, when you an create an instance in this mode, you must assign the logical transmit channel 0 ( tx_dataout[0] in the instance to the physical channel location 0 in the master transceiver block. f there are specific transceiver blocks that can be paired as master-slave in the 8 configuration. figure 3?8. basic 4 functional mode configuration when combining channels (note 4) notes to figure 3?8 : (1) you can configure this channel in basic (pma direct) single-width or double-width mode. (2) you can configure this channel only in basic (pma direct) single-width mode (3) the red lines represent the n top clock line, the blue lines represent the 4 clock line, and the black line represents the n bottom clock line. (4) to simplify the illustration, only the transmitter side is shown. pci express (pipe) 4 refers to pci express (pipe) with th e sub protocol set to gen1 x4 and gen2 x4 . atx pll atx pll tx3 - basic x4/ pci express (pipe) x4 tx2 - basic x4/ pci express (pipe) x4 tx1 - basic x4/ pci express (pipe) x4 tx0 - basic x4/ pci express (pipe) x4 cmu1 channel (pma direct xn mode) (1) cmu0 channel tx - basic (basic [pma direct] xn mdoe) (2) central clock divider x4 clock line (3) xn top clock line (3) xn bottom clock line 3?20 chapter 3: configuring multiple protocols and data rates in a transceiver block combining channels configured in protocol functional modes stratix iv device handbook volume 2 ? november 2009 altera corporation f the master is the adjacent lower transceiver block. for more information about location requirements, refer to the ?bonded channel configurations? section of the stratix iv transceiver clocking chapter. in basic 8 functional mode, you can select the number of channels to be less than 8 by setting the what is the number of channels? option on the general screen. in this instance, you can use the remaining transmitter channels only in basic (pma direct) 1 or n mode. in pci express (pipe) gen1 8 and gen2 8 functional modes, the number of regular channels used is always 8. the number of remaining transmitter channels (cmu channels or regular channels) in the two transceiver blocks available for use in basic (pma direct) 1 or n mode depends on whether the 8 functional mode uses cmu pll or atx pll, as described below. 1 if pci express (pipe) functional mode uses the pci express hard ip block, the combination requirements are different. for more information, refer to ?combining channels using the pci express hard ip block with other channels? on page 3?23 . 1 each receiver channel configured in basic 8 functional mode is clocked independently by the recovered clock from its receiver cdr.you can use the available receiver channels in any configuration. figure 3?9 shows examples of supported and unsupported configuration in basic 8 mode. when the eight regular channels are used up in bonded 8 functional mode: if atx pll is used to generate clocks for the 8 functional mode shown in figure 3?10 , you can use the four cmu channels (two from the master and slave transceiver block) in basic (pma direct) n mode. within basic (pma direct) n mode, you can configure the cmu0 channels in the master and slave transceiver block only in single-width mode (use the single-width mode option in the general screen). if a cmu1 channel or regular channels are available for use, you can use them in basic (pma direct) n mode in single-width or double-width configuration. figure 3?9. examples of supported and unsupported configurations to combine instances in basic 8 mode t w o adjacent transcei v er blocks t w o adjacent transcei v er blocks instance 0 6 channels receiv er and transmitter basic mode and 8 sub-protocol instance 1 2 channels receiv er only (any f unctional mode) su pported configu ration instance 0 6 channels receiv er and transmitter basic mode and 8 sub-protocol instance 1 2 channels transmitter only (any mode other than basic [pma direct] function mode) unsupported configuration red: unsupported t w o adjacent transcei v er blocks instance 0 6 channels receiv er and transmitter basic mode and 4 sub-protocol instance 1 1 channel transmitter and receiver (basic [pma direct] xn functional mode) supported configuration chapter 3: configuring multiple protocols and data rates in a transceiver block 3?21 combining channels configured in protocol functional modes ? november 2009 altera corporation stratix iv device handbook volume 2 figure 3?10. basic 8/pci express (pipe) 8 functional mode configuration when combining channels (atx pll) (note 4) notes to figure 3?10 : (1) you can configure this channel in basic (pma direct) single-width or double-width mode. (2) you can configure this channel only in basic (pma direct) single-width mode. (3) the red lines represent the n top clock line, the blue lines represent the 4 clock line, and the black line represents the n bottom clock line. (4) to simplify the illustration, only the transmitter side is shown. pci express (pipe) 8 refers to pci express (pipe) with th e sub protocol set to gen1 8 and gen2 8 . atx pll atx pll sla v e transcei v er block master transcei v er block tx0 - basic x8/ pci express (pipe) x8 tx1 - basic x8/ pci express (pipe) x8 tx2 - basic x8/ pci express (pipe) x8 tx3 - basic x8/ pci express (pipe) x8 cmu1 channel (basic [pma direct] xn mode) (1) cmu0 channel tx - (basic [pma direct] xn mode) (2) central clock divider tx4 - basic x8/ pci express (pipe) x8 tx5 - basic x8/ pci express (pipe) x8 tx6 - basic x8/ pci express (pipe) x8 tx7 - basic x8/ pci express (pipe) x8 cmu1 channel (pma direct xn mode) (1) cmu0 channel tx - (basic [pma direct] xn mode) (2) central clock divider xn top clock line (3) x4 clock line (3) xn bottom clock line (3) x4 clock line (3) xn bottom clock line (3) 3?22 chapter 3: configuring multiple protocols and data rates in a transceiver block combining channels configured in protocol functional modes stratix iv device handbook volume 2 ? november 2009 altera corporation if cmu pll is used to generate clocks for the 8 bonded functional mode, you can use the cmu0 channel in the slave transceiver block only in basic (pma direct) n mode in the single-width configuration. you can use the cmu1 channels in both the master and slave transceiver blocks in basic (pma direct) n mode in single- width or double-width configuration. figure 3?11 shows the basic 8 functional mode configuration for these combination restrictions when using cmu pll. figure 3?11. basic 8/pci express 8 functional mode configuration when combining channels (cmu pll) (note 4) notes to figure 3?11 : (1) you can configure this channel in basic (pma direct) single-width or double-width mode. (2) you can configure this channel only in basic (pma direct) single-width mode. (3) the red lines represent the n top clock line, the blue lines represent the 4 clock line, and the black line represents the n bottom clock line. (4) to simplify the illustration, only the transmitter side is shown. pci express (pipe) 8 refers to pci express (pipe) with th e sub protocol set to gen1 8 and gen2 8 . atx pll sla v e transcei v er block master transcei v er block tx1 - basic x8/ pci express (pipe) x8 tx0 - basic x8/ pci express (pipe) x8 tx2 - basic x8/ pci express (pipe) x8 tx3 - basic x8/ pci express (pipe) x8 cmu1 channel (basic [pma direct] xn mode) (1) cmu0 channel (used for clock generation) central clock divider tx4 - basic x8/ pci express (pipe) x8 tx5 - basic x8/ pci express (pipe) x8 tx6 - basic x8/ pci express (pipe) x8 tx7 - basic x8/ pci express (pipe) x8 cmu1 channel (basic [pma direct] xn mode) (1) cmu0 channel tx - (basic [pma direct] xn mode) (2) central clock divider xn top clock line (3) x4 clock line (3) xn bottom clock line (3) x4 clock line (3) chapter 3: configuring multiple protocols and data rates in a transceiver block 3?23 combining channels configured in protocol functional modes ? november 2009 altera corporation stratix iv device handbook volume 2 combining channels configured in deterministic latency mode the altgx megawizard plug-in manager provides deterministic latency mode with two variations (1 and 4) to eliminate uncertainty in the transceiver data path. this functional mode provides the enable phase frequency detector (pfd) feed back ? option in the pll/ports screen. if you select this option for 1, the low-speed parallel clock from the transmitter serializer is fed back to the pfd input of the cmu pll; for 4, the output of the low-speed parallel clock from the central clock divider is provided as feed back. for the 1 variation, one cmu pll is required for each transmitter channel in the instance. as a result, in 1 mode, you can configure only two channels within the transceiver block in this mode. the restrictions for deterministic latency mode in 4 mode are the same as that of the bonded x4 functional mode. for more information, refer to ?bonded 4 functional mode? on page 3?16 . combining channels using the pci express hard ip block with other channels the stratix iv gx device contains an embedded pci express hard ip block that performs the phymac, datalink, and transaction layer functionality specified by pci express (pipe) base specification 2.0. each pci express hard ip block is shared by two transceiver blocks. the pci express (pipe) compiler wizard provides you the options to configure the pci express hard ip block. when enabled, the transceiver channels associated with this block are also enabled. there are restrictions on combining transceiver channels with different functional and/or protocol modes (for example, basic mode) within two contiguous transceiver blocks with the channels that use the pci express hard ip block. the restrictions depend on the number of channels used (1 or 4) and the number of virtual channels (vcs) selected in the pci express (pipe) compiler megawizard plug-in manager. table 3?8 shows the restrictions. 1 when you use the pci express hard ip block, there are placement restrictions on the locations of the transceiver channels. f for these channel placement restrictions, refer to the pci express compiler user guide . tab le 3 ?8 . pci express hard ip block restrictions when combining transceiver channels with different functional and/or protocol modes (part 1 of 2) (note 1) , (2) , (7) pci express (pipe) configuration (pci express hard ip options enabled in the pcie compiler wizard) (3) transceiver block 0 (4) transceiver block 1 (5) link width lane (data interface width) virtual channel (vc) ch0 (6) ch1 ch2 ch3 ch4 ch5 ch6 ch7 1 64-bit 1 pcie 1 avail. avail. avail. avail. avail. avail. avail. 2 pcie 1 ? ? ? avail. avail. avail. avail. 4 64-bit 1 pcie 4 avail. avail. avail. avail. 2 pcie 4 avail. avail. avail. avail. 4 128-bit 1 pcie 4 avail. avail. avail. avail. 2 pcie 4 ? ? avail. avail. 3?24 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver channels with basic (pma direct) configuration stratix iv device handbook volume 2 ? november 2009 altera corporation f for more information about the pci express (pipe) compiler megacore functions and hard ip implementation, refer to the pci express compiler user guide. if you configure a transceiver channel in pci express (pipe) configuration and if an atx pll is used to provide clocks for the transmitter side of the channel, you can use the remaining transmitter channels within the same transceiver block only in basic (pma direct) 1 or n mode. combining transceiver channels with basic (pma direct) configuration in this configuration, the transmitter and receiver pcs blocks of a transceiver channel are bypassed and the transceiver channel can run at a maximum of 6.5 gbps. f for the data rate restrictions in basic (pma direct) mode, refer to the ?transceiver performance specifications? section in the dc and switching characteristics chapter. using the quartus ii software, you can configure the two cmu channels and regular transceiver channels in basic (pma direct) mode. the following sections describes the different scenarios for combining basic (pma direct) mode with other transceiver configurations. f for information about the fpga fabric-transceiver interface, refer to the ? non-bonded basic (pma direct) mode channel configurations? section in the stratix iv transceiver clocking chapter. 8 ? ? pcie 8 notes to ta bl e 3? 8 : (1) avail. indicates that the channels can be used in other configurations. (2) an em-dash (?) indicates that the channels are not available for use. (3) the cmu pll is used for the transmitter side of the channels in this table. (4) transceiver block 0?the master transceiver block that provides high-speed serial and low-speed parallel clocks in a pci express (pipe) 4 or 8 configuration. (5) transceiver block 1?the adjacent transceiver block that shares the same pci express hard ip block with transceiver block 0. (6) the physical channel 0 in the transceiver block. for more in formation about physical-to-logical channel mapping in pci expre ss (pipe) functional mode, refer to the ?8 channel configuration? section in the stratix iv transceiver clocking chapter in volume 2 of the stratix iv device handbook . (7) when you the use pci express (pipe) hard ip block, you cannot configure the cmu channels within the transceiver block as tra nsceiver channels. tab le 3 ?8 . pci express hard ip block restrictions when combining transceiver channels with different functional and/or protocol modes (part 2 of 2) (note 1) , (2) , (7) pci express (pipe) configuration (pci express hard ip options enabled in the pcie compiler wizard) (3) transceiver block 0 (4) transceiver block 1 (5) link width lane (data interface width) virtual channel (vc) ch0 (6) ch1 ch2 ch3 ch4 ch5 ch6 ch7 chapter 3: configuring multiple protocols and data rates in a transceiver block 3?25 combining transceiver channels with basic (pma direct) configuration ? november 2009 altera corporation stratix iv device handbook volume 2 combining multiple channels configured in basic (pma direct) 1 configurations when you configure a transceiver channel in basic (pma direct) 1 configuration, the quartus ii software requires one of the two cmu plls within the same transceiver block to provide high-speed clocks to the transmitter side of the channel (you cannot use the atx pll). therefore, within a transceiver block, you can only combine a maximum of five transceiver channels (using both transmitter and receiver) configured in basic (pma direct) 1 mode (one cmu channel to perform the clock multiplication unit functionality). you can configure the transmitter side of the cmu channel that uses its cmu pll for clock generation in basic (pma direct) x1 in single-width or double-width configuration, as shown in figure 3?17 on page 3?31 . there are multiple ways you can combine channels in basic (pma direct) 1 mode within the same transceiver block: ?multiple basic (pma direct) 1 configuration instances with one channel per instance? on page 3?25 ?one instance in basic (pma direct) 1 configuration with multiple transceiver channels? on page 3?25 ?combining multiple instances of tx only and rx only configurations in basic (pma direct) 1 mode? on page 3?28 ?combining channels configured in basic (pma direct) 1 with non-basic (pma direct) modes? on page 3?28 multiple basic (pma direct) 1 configuration instances with one channel per instance if you create multiple instances of basic (pma direct) 1 with one channel per instance, you can combine them within the same transceiver block. to achieve this combination, refer to the requirements specified in ?multiple channels sharing a cmu pll? on page 3?5 and ?general requirements to combine channels? on page 3?3 . note that one cmu pll within the transceiver block must provide a high-speed clock for the transmitter side of the channels. therefore, at least one cmu channel (that contains the cmu pll) within the transceiver block must be available to generate high-speed serial and low-speed parallel clocks for the channels configured in this mode. you can also place the individual instances in this configuration in separate transceiver blocks. for this placement, the quartus ii software enables one cmu pll per instance. one instance in basic (pma direct) 1 configuration with multiple transceiver channels in this case, if the number of channels selected in the instance is less than six, the quartus ii software, by default, combines these channels within the same transceiver block and uses one cmu pll to provides high-speed clocks. if the number of channels is six or more, the quartus ii software requires two transceiver blocks and two cmu plls, one from each transceiver block. the following two examples show the combinations of channels under two different conditions. 3?26 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver channels with basic (pma direct) configuration stratix iv device handbook volume 2 ? november 2009 altera corporation example 5 consider a design example configuration with a basic (pma direct) 1 instance with the number of channels set to 7 in the altgx megawizard plug-in manager. with this setting, the altgx megawizard plug-in manager provides 7 bits of gxb_powerdown, rx_analogreset , and pll_powerdown ports. in this case, the quartus ii software attempts to combine the five channels in the instance to one transceiver block and the remaining two channels to the second transceiver block, assuming that the gxb_powerdown and pll_powerdown ports for the five channels are driven from the same logic. figure 3?12 and figure 3?13 show the conditions before and after compilation. figure 3?12. logical view of the instance with seven channels before compilation for example 5 cmu pll inst0 number of channels = 7 receiv er and transmitter config u ration: basic (pma direct) x1 mode chapter 3: configuring multiple protocols and data rates in a transceiver block 3?27 combining transceiver channels with basic (pma direct) configuration ? november 2009 altera corporation stratix iv device handbook volume 2 figure 3?13 shows the conditions after compilation. in this example, the gxb_powerdown and pll_powerdown ports for channels 0 to 4 and channels 5 to 6 are driven from the same logic. if you connect each of the seven bits of the gxb_powerdown and pll_powerdown ports to different reset control logic, the quartus ii software requires seven transceiver blocks to combine the seven channels in the instance. figure 3?13. combined channels after compilation for example 5 transcei v er block0 transcei v er block1 cmu pll inst0: channel 0 inst0: channel 1 inst0: channel 2 inst0: channel 3 inst0: channel 4 inst0: channel 5 inst0: channel 6 rx tx rx tx rx tx rx tx rx tx rx tx rx tx cmu pll 3?28 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver channels with basic (pma direct) configuration stratix iv device handbook volume 2 ? november 2009 altera corporation combining multiple instances of tx only and rx only configurations in basic (pma direct) 1 mode the quartus ii software allows you to combine instances of tx only and rx only configurations in basic (pma direct) 1 mode. you can also combine tx only instances in non-basic (pma direct) 1 configuration (non-bonded only) and the rx only instance in basic (pma direct) configurations (and vice versa) in the same physical channel. the combination requirements of the instances in basic (pma direct) 1 configuration are similar to that of non-basic (pma direct) configuration. for more information, refer to the ?combining transmitter channel and receiver channel instances? on page 3?10 . combining channels configured in basic (pma direct) 1 with non-basic (pma direct) modes you can combine a transceiver channel instance configured in basic (pma direct) 1 configuration with instances set up in non-basic (pma direct) configurations (for example, gige and sdi within the same transceiver block). if the cmu pll configuration for the basic (pma direct) 1 configuration and the non-basic (pma direct) configuration instances meet the requirements specified in ?multiple channels sharing a cmu pll? on page 3?5 and ?general requirements to combine channels? on page 3?3 , the quartus ii software uses a single cmu pll for these two instances. in addition, to share the same cmu pll between the two instances, the channel reconfiguration option must not be enabled in the instance setup in non-basic (pma direct) configuration. example 6 consider the example design shown in table 3?9 for basic (pma direct) 1 and non-basic (pma direct) configurations at the same data rate. tab le 3 ?9 . basic (pma direct) 1 and non-basic (pma direct) configurations at the same data rate for example 6 instances configuration cmu pll base data rate transmitter channel effective data rate input reference clock frequency inst0 gige 1.25 gbps 1.25 g 125 mhz (assume refclk0 ) inst1 basic (pma direct) 1 (four channels) 1.25 gbps 1.25 g same as inst0 chapter 3: configuring multiple protocols and data rates in a transceiver block 3?29 combining transceiver channels with basic (pma direct) configuration ? november 2009 altera corporation stratix iv device handbook volume 2 figure 3?14 shows basic (pma direct) 1 and non-basic (pma direct) configurations before compilation. figure 3?15 shows basic (pma direct) 1 and non-basic (pma direct) configurations after compilation. figure 3?14. logical view of the instances in basic (pma direct) 1 and non-basic (pma direct) configurations before compilation for example 6 figure 3?15. combining basic (pma-direct) 1 and non-basic (pma direct) configurations after compilation for example 6 cmu pll (1.25 g) cmu pll (1.25 g) inst0: gige f unctional mode number of channels = 1 inst1: basic (pma direct) x1 mode number of channels = 4 transcei v er block cmu pll (1.25 g bps) inst0: gige channel inst1: channel 0 inst1: channel 1 inst1: channel 2 inst1: channel 3 rx tx rx tx rx tx rx tx rx tx 3?30 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver channels with basic (pma direct) configuration stratix iv device handbook volume 2 ? november 2009 altera corporation example 7 consider the example design shown in table 3?10 for basic (pma direct) 1 and non-basic (pma direct) configurations at different data rates. figure 3?16 shows basic (pma direct) 1 and non-basic (pma direct) configurations before compilation. 1 the data rate configurations of the two cmu plls are different. table 3?10. basic (pma direct) 1 and non-basic (pma direct) configurations at different data rates for example 7 instances configuration cmu pll base data rate transmitter channel effective data rate input reference clock frequency inst0 gige 1.25 gbps 1.25 gbps 125 mhz (assume refclk0 ) inst1 basic (pma direct) 1 (three channels in receiver and transmitter configuration) 2 gbps 2 gbps refclk1 inst2 basic (pma direct) 1 (one channel in transmitter only configuration) 2 gbps 2 gbps refclk1 figure 3?16. logical view of the basic (pma direct) 1 and non-basic (pma direct) configurations before compilation for example 7 cmu pll (1.25 gbps) cmu pll (2 gbps) inst0: gige f unctional mode number of channels = 1 inst1: basic (pma direct) x1 mode number of channels = 3 cmu pll (2 gbps) inst2: basic (pma direct) x1 mode number of channels = 1 chapter 3: configuring multiple protocols and data rates in a transceiver block 3?31 combining transceiver channels with basic (pma direct) configuration ? november 2009 altera corporation stratix iv device handbook volume 2 figure 3?17 shows basic (pma direct) 1 and non-basic (pma direct) configurations after compilation. key observations 1 to combine the these instances, two cmu plls are required due to the different data rates. therefore, two cmu channels must be available to enable their respective cmu plls. note that inst3 uses the transmit side of the cmu channel that uses the cmu pll for clock generation. figure 3?17. combining basic (pma direct) 1 and non-basic (pma direct) instances in a transceiver block after compilation for example 7 gxbr inst0: channel (gige) inst1: channel 0 inst1: channel 1 inst1: channel 2 rx tx rx tx rx tx rx tx inst3: tx cmu pll (2 gbps) cmu pll (1.25 g bps) 3?32 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver channels with basic (pma direct) configuration stratix iv device handbook volume 2 ? november 2009 altera corporation basic (pma direct) n configuration when you configure a transceiver channel in basic (pma direct) n configuration, you can enable the quartus ii software to use the n lines to provide clocks to the transmitter channels, as shown in figure 3?18 . the following are the possible sources driving the n clock lines: the cmu0 central divider within the cmu0 channel. only the cmu0 clock divider block can drive the n clock lines. either the cmu0 pll or cmu1 pll can drive the central clock divider block. f to understand the input clock connections to the central clock divider block, refer to the ?cmu0 channel? section in the stratix iv transceiver architecture chapter. the atx pll block channel placement in a basic (pma direct) n mode instance if you compile a design with a transceiver instance configured in basic (pma direct) xn mode, the quartus ii software, by default, places these channels contiguously. you can force the placement of the transceiver channels across multiple transceiver blocks on the same side of the device by assigning pins to the transmitter and receiver serial ports. the logical channel 0 of the basic (pma direct) n mode instance does not have to be assigned to the physical channel 0 of a transceiver block. the logical channel 0 of an instance with multiple channels is tx_dataout[0] or rx_datain[0] , which are the serial transmit and receive ports provided by the altgx megawizard plug-in manager. when you assign pins, you are not required to assign tx_dataout[0] to the location of physical channel 0 in the transceiver block to compile your design. this is not the case if you have a pci express (pipe) 4 configuration where tx_dataout[0] and rx_datain[0] must be assigned to physical channel 0 of the transceiver block. chapter 3: configuring multiple protocols and data rates in a transceiver block 3?33 combining transceiver channels with basic (pma direct) configuration ? november 2009 altera corporation stratix iv device handbook volume 2 figure 3?18 shows the different drivers of the n_top and n_bottom clock lines. figure 3?18. the n_top and n_bottom clock line connections xn_top transcei v er block gxbr2 channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel atx r1 pll block transcei v er block gxbr1 channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel atx r0 pll block transcei v er block gxbr0 channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel x1 cmu0 gxbr2 x1 cmu1 gxbr2 x4_gxbr2 x4_gxbr1 x4_gxbr0 xn_bottom x1 cmu1 gxbr1 x1 cmu1 gxbr0 x1 cmu0 gxbr1 x1 cmu0 gxbr0 3?34 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver channels with basic (pma direct) configuration stratix iv device handbook volume 2 ? november 2009 altera corporation examples of combining multiple instances of basic (pma direct) n modes the following section describes combining multiple transceiver channel instances in basic (pma direct) n mode. configuration examples include transceiver channels with different data rates, configurations in basic (pma direct) n mode with non-basic (pma direct) and atx pll, and unsupported configurations. example 8 consider the configuration for the two instances shown in table 3?11 when combining transceiver channels in basic (pma direct) n mode with different data rates. table 3?11. combining transceiver channels in basic (pma direct) n configuration with different data rates for example 8 user defined instance name number of channels effective data rate configuration inst 0 6 1.5 gbps receiver and transmitter inst 1 5 1.25 gbps receiver and transmitter chapter 3: configuring multiple protocols and data rates in a transceiver block 3?35 combining transceiver channels with basic (pma direct) configuration ? november 2009 altera corporation stratix iv device handbook volume 2 you can place channels within a given instance non contiguously as shown in figure 3?19 . figure 3?19. non-contiguous placements of channels using different cmu plls for example 8 note to figure 3?19 : (1) the red lines represent the n top clock line, the blue lines represent the 4 clock line, and the black lines represent the n bottom clock line. tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx gxbr1 x4 clock line (1) xn bottom clock line (1) xn top clock line (1) inst0: channel 0 inst0: channel 1 inst0: channel 2 inst0: channel 3 inst0: channel 4 gxbr0 inst1: channel 0 inst1: channel 1 inst1: channel 2 inst0: channel 5 inst1: channel 3 inst1: channel 4 transcei v er block 2 cmu0 pll base data rate 1.25 gbps cmu0 channel central clock divider cmu0 pll base data rate 1.5 gbps cmu0 channel central clock divider 3?36 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver channels with basic (pma direct) configuration stratix iv device handbook volume 2 ? november 2009 altera corporation key observations: note that channel 5 in inst0 is placed in transceiver block 1 and receives the high-speed clock through the n_top clock line. some of the channels in transceiver block 1 receive their high-speed clock from the n_bottom clock line. because the n_top and n_bottom lines are separate, this scenario is allowed. to understand the clock multiplexer on the n clock lines, refer to figure 3?18 on page 3?33 . combining channels configured in basic (pma direct) n configuration with non-basic (pma direct) configurations the quartus ii software only allows a combination of a transceiver channel instances configured in basic (pma direct) n mode with instances in non-basic (pma direct) configurations; for example, gige and sdi. example 9 consider the example design shown in table 3?12 for the two instances when combining a basic (pma direct) n configuration with a non-basic (pma direct) configuration using a cmu pll. table 3?12. combining basic (pma direct) n configuration with non-basic (pma direct) configuration using cmu pll for example 9 user defined instance name number of channels effective data rate configuration functional mode inst 0 9 1.5 gbps receiver and transmitter basic (pma direct) n inst 1 1 1.25 gbps receiver and transmitter gige chapter 3: configuring multiple protocols and data rates in a transceiver block 3?37 combining transceiver channels with basic (pma direct) configuration ? november 2009 altera corporation stratix iv device handbook volume 2 you can place these two instances in two transceiver blocks, as shown in figure 3?20 . figure 3?20. combining basic (pma direct) n configuration with non-basic (pma direct) configuration using cmu pll in two transceiver blocks for example 9 note to figure 3?20 : (1) the red lines represent the n top clock line, the blue lines represent the 4 clock line, and the black line represents the n bottom clock line. gxbr1 inst0:channel 1 inst0:channel 0 rx tx inst0:channel 1 rx tx inst0:channel 2 rx tx inst0:channel 3 rx tx inst0:channel 4 rx tx gxbr0 inst0:channel 1 inst0:channel 5 rx tx inst0:channel 6 rx tx inst0:channel 7 rx tx inst0:channel 8 rx tx inst1:channel 0 rx tx cmu pll (1.25 gbps) xn top clock line (1 ) x4 clock line (1) x1 clock line cmu0 pll cmu0 channel central clock divider 3?38 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver channels with basic (pma direct) configuration stratix iv device handbook volume 2 ? november 2009 altera corporation example 10 consider the example design shown in table 3?13 when combining a basic (pma direct) n configuration with a non-basic (pma direct) configuration using an atx pll. table 3?13. combining basic (pma direct) n configuration with non-basic (pma direct) configuration using atx pll for example 10 user defined instance name number of channels effective data rate configuration functional mode inst 0 10 1.5 gbps receiver and transmitter basic (pma direct) n configuration inst 1 15 gbps receiver and transmitter basic mode (pcs+pma) using atx pll chapter 3: configuring multiple protocols and data rates in a transceiver block 3?39 combining transceiver channels with basic (pma direct) configuration ? november 2009 altera corporation stratix iv device handbook volume 2 in this case, the atx pll provides the high-speed clock to the transmitter channel of inst 1 . therefore, you can combine 10 channels of inst 0 and one channel of inst 1 in two transceiver blocks, as shown in figure 3?21 figure 3?21. combining basic (pma direct) n configuration with non-basic (pma direct) configuration using an atx pll for example 10 (note 1) notes to figure 3?21 : (1) the atx pll provides the high-speed clock to channel 0 of inst1 . (2) the red lines represent the n top clock line, the blue lines represent the 4 clock line, and the black line represents the n bottom clock line. tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx x4 clock line (2) tx rx xn bottom clock line (2) gxbr1 inst0: channel 0 inst0: channel 1 inst0: channel 2 inst0: channel 3 inst0: channel 4 gxbr0 inst0: channel 5 inst0: channel 6 inst0: channel 7 inst0: channel 8 inst0: channel 9 inst1: channel 0 xn top clock line (2 ) cmu0 pll cmu0 channel central clock divider atx pll base data rate 5 gbps atx pll b lock central clock divider 3?40 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver channels with basic (pma direct) configuration stratix iv device handbook volume 2 ? november 2009 altera corporation you can also combine channels configured in basic (pma direct) n mode with bonded 4 and 8 functional modes. for example scenarios, refer to figure 3?8 on page 3?19 and figure 3?10 on page 3?21 . example 11 consider the unsupported placement design example shown figure 3?22 . the placement is unsupported because of the n_top clock line contention between the atx pll and the cmu0 pll in transceiver block 0. figure 3?22. unsupported placement due to n clock line contention for example 11 note to figure 3?22 : (1) the red lines represent the n top clock line and the blue lines represent the 4 clock line. gxbr1 inst0:channel 1 inst0:channel 0 rx tx inst0:channel 1 rx tx inst0:channel 2 rx tx inst0:channel 3 rx tx inst0:channel 4 rx tx gxbr0 inst0:channel 1 inst0:channel 5 rx tx inst0:channel 6 rx tx inst0:channel 8 rx tx inst0:channel 7 rx tx inst1:channel 0 rx tx inst0:channel 9 rx tx xn top clock line (1) atx pll r1 (5 gbps) x4 clock line (1) contention in u sing the clock line this channel cannot get its clock from the atx pll d u e to clock contention cmu0 pll cmu0 channel central clock divider chapter 3: configuring multiple protocols and data rates in a transceiver block 3?41 combination requirements when channel reconfiguration is enabled ? november 2009 altera corporation stratix iv device handbook volume 2 combination requirements when channel reconfiguration is enabled you can configure a transmitter channel to: switch to an alternate cmu pll present within the same transceiver block. switch to multiple tx plls (cmu or atx plls) that are present outside the transceiver block. f for more information about setting up the transceiver to enable one of these three options, refer to the stratix iv dynamic reconfiguration chapter. the section describes the combination requirements for an instance that is configured in one of the three options mentioned above with other instances. combination requirements when the use alternate cmu pll option is selected if you create a transceiver instance by selecting the use alternate cmu pll option, the quartus ii software uses two cmu plls. if you intend to combine other transmitter instances within the same transceiver block, the cmu plls must be shared between multiple instances. to enable the quartus ii software to share the cmu plls between these instances, you must: 1. select the user alternate cmu pll option in all the instances. 2. set the same pll logical reference index value for the similar plls between the two instances (similar plls are the ones that have the same data rate, input clock frequency, and bandwidth setting). 3. create a gxb tx pll reconfiguration group setting in the assignment editor and assign the same value for both instances. table 3?14 lists the assignment for the first instance (instance 1). table 3?15 lists the assignment for the second instance (instance 2). 1 ensure that the requirements specified in the ?general requirements to combine channels? on page 3?3 and ?sharing cmu plls? on page 3?5 sections are met. table 3?14. assignment for the first instance?instance 1 assignment setting to 3?42 chapter 3: configuring multiple protocols and data rates in a transceiver block combination requirements when channel reconfiguration is enabled stratix iv device handbook volume 2 ? november 2009 altera corporation example 12 shows the requirements. example 12 consider that you intend to run four channels within the transceiver block to switch between gige and sonet oc48 data rates. assume that by default two channels run at gige data rates and the other two channels run at sonet oc48 data rates. assume that instance1 with two channels running at gige data rate is created with the configuration, as shown in table 3?16 . create instance 2 with the following parameters to enable the quartus ii software to share cmu plls between the two instances. table 3?17 lists the required parameters to be set for instance 2 table 3?18 lists the assignment for the gxb tx pll reconfiguration group for instance 1 when you compile the design. table 3?16. combining requirements with the ?use alternate cmu pll? option enabled?instance 1 for example 12 pll data rate input reference clock pll logical reference index main pll 1.25 gbps 125 mhz 0 alternate pll 2.488 gbps 155.5 mhz 1 table 3?17. combining requirements with the ?use alternate cmu pll? option enabled?instance 2 for example 12 pll data rate input reference clock pll logical reference index main pll 2.488 gbps 155.5 mhz 1 alternate pll 1.25 gbps 125 mhz 0 table 3?18. assignment for the gxb tx pll reconfiguration group for instance 1 assignment setting to tx_dataout_instance1[0] note that the number of channels in this instance is 2. you can use any one of the channel port names within this instance for this assignment. assignment name gxb tx pll reconfiguration group setting value 6 chapter 3: configuring multiple protocols and data rates in a transceiver block 3?43 combination requirements when channel reconfiguration is enabled ? november 2009 altera corporation stratix iv device handbook volume 2 table 3?19 lists the assignment for the gxb tx pll reconfiguration group for instance 2 when you compile the design. key observations the main pll in instance 1 is configured for gige data rates because this is the data rate that you intend to run the first instance. the main pll in instance 2 is configured for sonet oc48 data rates because this is the data rate that you intend to run the second channel. note that the pll logical reference index values for similar plls in instance 1 and instance 2 are the same. the gxb tx pll reconfiguration group setting value for tx_dataout of instance 1 and instance 2 are the same. combination requirements when multiple tx plls are used this scenario describes transceiver configurations that have the use additional cmu/atx transmitter plls from outside the transceiver block option in the reconfig screen enabled. if you create a transceiver instance using the above option and would like to share the cmu plls or atx pll with other instances, ensure that you have met the following requirements: select the use additional cmu/atx transmitter plls from outside the transceiver block option in other instances. 1 the number of additional plls selected (in the how many additional plls are used option) can be different between instances. the pll logical reference index value of the similar plls that you intend to combine must be the same in all the instances considered. 1 similar plls are the ones that have the same data rate, input clock frequency, and bandwidth setting. table 3?19. assignment for the gxb tx pll reconfiguration group for instance 2 assignment setting to tx_dataout_instance2[1] you can use any one of the channel port names within this instance for this assignment. assignment name gxb tx pll reconfiguration group setting value 6 3?44 chapter 3: configuring multiple protocols and data rates in a transceiver block combination requirements when channel reconfiguration is enabled stratix iv device handbook volume 2 ? november 2009 altera corporation assign the same gxb tx pll reconfiguration group setting value for the tx_dataout ports of all the instances. this is explained in ?combination requirements when the use alternate cmu pll option is selected? on page 3?41 . ensure that the requirements specified in ?general requirements to combine channels? on page 3?3 , ?sharing cmu plls? on page 3?5 , and ?sharing atx plls? on page 3?9 are met. if you create an instance using the use additional cmu/atx transmitter plls from outside the transceiver block option and place your transmitter channels in one transceiver block (for example, ql1) and you use a cmu/atx pll from another transceiver block (for example, ql0), the channels (if used) in ql0 must be connected to the same reconfiguration controller as that of ql1. example 13 shows an instance using multiple plls. example 13 consider that the following 12-channel design is targeted for a three transceiver block per side device. the requirements for this design are: 1. four transceiver channels to switch independently between four protocol data rates (sonet oc48, fc 2g, gige, and otu1). 2. four transceiver channels to operate in sonet oc48 data rate. 3. four transceiver channels to operate in gige data rate. to implement step 1, you need four tx plls. place the four channels in the middle transceiver block (ql1?the left side was chosen for illustration purposes), and provide one cmu pll from ql0 for the sonet oc48 data rate and one cmu pll from ql2 for the gige data rate. use the two cmu plls from ql1 for the fc 2g and otu1 data rates. to implement step 2, note that the cmu pll in ql0 already provides the sonet oc48 data rate. therefore, use the four channels in ql0 to run the sonet oc48 data rate. to implement step 3, note that the cmu pll in ql2 already provides the gige data rate. therefore, use the four channels in ql2 to run the gige data rate. chapter 3: configuring multiple protocols and data rates in a transceiver block 3?45 combination requirements when channel reconfiguration is enabled ? november 2009 altera corporation stratix iv device handbook volume 2 figure 3?23 shows the configuration for example 13. figure 3?23. three transceiver block configuration for example 13 notes to figure 3?23 : (1) cmu channels are used for clock generation. (2) the red lines represent the n top clock line, the blue lines represent the 1 clock line, the black lines represent n bottom clock, the green lines represents the cmu1 channel, and the brown lines represent the cmu0 channel. tx3: gige tx2: gige cmu0 channel (gige) (1) tx1: gige tx0: gige tx3: fo u r data rates tx2: fo u r data rates cmu0 channel (fc 2g) (1) cmu1 channel (otu1) (1) tx1: fo u r data rates tx0: fo u r data rates tx3: sonet oc4 8 tx2: sonet oc4 8 tx1: sonet oc4 8 tx0: sonet oc4 8 cmu0 channel (sonet oc 48) (1) ql2 ql1 ql0 x1 clock line (2) x1 clock line (2) xn_top clock li xn_bottom clock line (2 3?46 chapter 3: configuring multiple protocols and data rates in a transceiver block combining transceiver channels when the adaptive equalization (aeq) is stratix iv device handbook volume 2 ? november 2009 altera corporation create three instances for steps 1, 2, and 3 with the following parameters: instance 1 select the use additional cmu/atx transmitter plls from outside the transceiver block option. number of additional plls: 3 ( table 3?20 ) instance 2 select the use additional cmu/atx transmitter plls from outside the transceiver block option. number of additional plls: 0 ( table 3?21 ) instance 3 select the use additional cmu/atx transmitter plls from outside the transceiver block option. number of additional plls: 0 ( table 3?22 ) for more information, refer to ?combination requirements when the use alternate cmu pll option is selected? on page 3?41 . combining transceiver channels when the adaptive equalization (aeq) is enabled to enable the aeq feature in a transceiver channel, select the enable adaptive equalization option in the reconfig screen of the altgx megawizard plug-in manager. when you select this option, the aeq_fromgxb and aeq_togxb ports are enabled. f for more information about initiating the aeq feature, refer to the ?adaptive equalization (aeq)? section in the stratix iv dynamic reconfiguration chapter. table 3?20. instance 1 for example 13 pll data rate pll logical reference index main pll fc 2g 0 pll1 otu1 1 pll2 gige 2 pll3 sonet oc48 3 table 3?21. instance 2 for example 13 pll data rate pll logical reference index main pll sonet oc48 3 table 3?22. instance 3 for example 13 pll data rate pll logical reference index main pll gige 2 chapter 3: configuring multiple protocols and data rates in a transceiver block 3?47 combining transceiver channels when the adaptive equalization (aeq) is enabled ? november 2009 altera corporation stratix iv device handbook volume 2 this section describes the requirements to combine transceiver channels when you enable the aeq feature. you are not required to enable aeq in all instances to combine them within the same transceiver block. when you instantiate the reconfiguration controller ( altgx_reconfig ), the aeq_fromgxb and aeq_togxb ports available depend on the setting in the what is the number of channels controlled by the reconfig controller option. in configurations where aeq is enabled on some of the transceiver channels that are connected to the same reconfiguration controller, the reconfiguration controller instance has additional aeq_fromgxb ports. to compile the design successfully, connect the unused aeq_fromgxb ports to 0. ?example 14? shows the configuration. example 14 consider that you have two altgx instances, instance 1 and instance 2 with one channel each. assume that only instance 1 has the enable adaptive equalization option enabled. because there are two instances, the starting channel numbers of instance 1 and instance 2 are spaced four apart (0 and 4, respectively). in the altgx_reconfig instance, set the what is the number of channels controlled by the reconfig controller option to 8 . the altgx_reconfig instance has 48 bits for the aeq_fromgxb port (24 bits per 4 channels). instance 1 has the aeq_fromgxb[23:0] port because aeq is enabled. instance 2 does not have this port. because instance 1 has the starting channel number of 0, connect aeq_fromgxb of instance 1 to aeq_fromgxb[23:0] of the altgx_reconfig instance and tie aeq_fromgxb[47:24] to 0. f for more information about setting this parameter, refer to the stratix iv dynamic reconfiguration chapter. figure 3?24 shows the required connection for the aeq_fromgxb port. 1 the top 24 bits of aeq_fromgxb are tied to 0. this is because the logical channel address of instance 1 starts at 4. therefore, the top 24 bits of aeq_fromgxb corresponds to instance 2. figure 3?24. required connection for the aeq_fromgxb port reconfig_fromgxb[33:0] aeq_fromgxb[47:0] reconfigu ration controller 24?h0 reconfig_fromgxb[16:0] aeq_fromgxb[23:0] reconfig_fromgxb[33:17] instance 1 instance 2 3?48 chapter 3: configuring multiple protocols and data rates in a transceiver block combination requirements for stratix iv gt devices stratix iv device handbook volume 2 ? november 2009 altera corporation combination requirements for stratix iv gt devices stratix iv gt devices allow configuring multiple protocols or data rates in the same transceiver block. for common protocols supported by both stratix iv gx and stratix iv gt devices, as well as for basic functional mode at data rates between 2.488 gbps and 8.5 gbps, stratix iv gt devices follow the same transceiver channel placement rules as stratix iv gx devices. placement rules for transceiver channels at 9.9 gbps to 10.3125 gbps you can use either the cmu pll or the 10g atx pll to generate transceiver clocks for channels configured at data rates between 9.9 gbps and 10.3125 gbps. if you use a 10g atx pll to generate transceiver clocks for any channel configured between 9.9 gbps and 10.3125 gbps within a transceiver block, the remaining channels in the same transceiver block must either be unused or must be configured at the same data rate and clocked by the same 10g atx pll. if you use a cmu pll to generate transceiver clocks for any channel configured between 8.5 gbps and 10.3125 gbps within a transceiver block, the remaining channels in the same transceiver block may be configured at a different data rate and clocked by another cmu pll or 6g atx pll. in this case, stratix iv gt devices follow the same transceiver channel placement rules as stratix iv gx devices. placing transceiver channels clocked by another pll in the same transceiver block as a 10g channel can result in higher transmitter output jitter on the 10g channel. the amount of additional jitter is pending characterization. chapter 3: configuring multiple protocols and data rates in a transceiver block 3?49 summary ? november 2009 altera corporation stratix iv device handbook volume 2 summary the following is a summary for configuring multiple protocols and data rates in a transceiver block: you can run each transceiver channel at independent data rates or in independent protocol functional modes. each transceiver block consists of two cmu plls that provide clocks to run the transmitter channels within the transceiver block. to enable the quartus ii software to combine multiple instances of transceiver channels within a transceiver block, follow the rules specified in ?general requirements to combine channels? on page 3?3 and ?sharing cmu plls? on page 3?5 . you can reset each cmu pll within a transceiver block using a pll_powerdown signal. for each transceiver instance, the altgx megawizard plug-in manager provides an option to select the pll_powerdown port. if you want to share the same cmu pll between multiple transceiver channels, connect the pll_powerdown ports of the instances and drive the signal from the same logic. if you enable the pci express (pipe) hard ip block using the pci express (pipe) compiler, the quartus ii software has certain requirements for using the remaining transceiver channels within the transceiver block in the other configurations. for more information, refer to ?combining channels using the pci express hard ip block with other channels? on page 3?23 . the quartus ii software supports two kinds of basic (pma direct) configurations (1 and n). if you use basic (pma direct) 1 configuration, you must use the cmu pll within the same transceiver block. document revision history table 3?23 shows the revision history for this chapter. table 3?23. document revision history (part 1 of 2) date and document version changes made summary of changes november 2009, v4.0 added ?sharing atx plls? on page 3?9 , ?combination requirements when channel reconfiguration is enabled? on page 3?41 , ?combining transceiver channels when the adaptive equalization (aeq) is enabled? on page 3?46 , and ?combination requirements for stratix iv gt devices? on page 3?48 . added figure 3?8 , figure 3?10 , figure 3?11 , figure 3?23 , and figure 3?24 . updated all other sections. added stratix iv gt information. updated graphics. minor text edits. ? 3?50 chapter 3: configuring multiple protocols and data rates in a transceiver block document revision history stratix iv device handbook volume 2 ? november 2009 altera corporation june 2009, v3.1 updated table 3?7. minor text edits. ? march 2009, v3.0 updated sections ?combining channels using the pci express hard ip block with other channels? on page 3?17, ?convention used? on page 3?21, ?pma direct mode restrictions? on page 3?22, ?multiple ?pma direct x1? configuration instances with one channel per instance? on page 3?22, ?combining multiple instances of tx only and rx only pma-direct x1 configurations? on page 3?26, ?combining transceiver channels with pma direct configuration? on page 3?21. updated table 3?7. updated figure 3?19. ? november 2008 v2.0 updated ?transmitter buffer voltage (vcch)? on page 3?2 added ?reconfig_fromgxb and reconfig_togxb ports? on page 3?3 updated figure 3?7 added ?basic x8 mode? on page 3?15 added figure 3?8 updated table 3?7 ? may 2008 v1.0 initial release. ? table 3?23. document revision history (part 2 of 2) ? november 2009 altera corporation stratix iv device handbook volume 2 4. reset control and power down stratix ? iv gx devices offer multiple reset signals to control transceiver channels and clock multiplier unit (cmu) phase-locked loops (plls) independently. the altgx transceiver megawizard ? plug-in manager provides individual reset signals for each channel instantiated in your design. it also provides one power-down signal for each transceiver block. this chapter includes the following sections: ?user reset and power-down signals? on page 4?1 ?transceiver reset sequences? on page 4?4 ?pma direct drive mode reset sequences? on page 4?23 ?dynamic reconfiguration reset sequences? on page 4?34 ?power down? on page 4?37 ?simulation requirements? on page 4?38 ?reference information? on page 4?39 figure 4?1 shows the reset control and power-down block for a stratix iv gx device. user reset and power-down signals each transceiver channel in the stratix iv gx device has individual reset signals to reset its physical coding sublayer (pcs) and physical medium attachment (pma) blocks. each cmu pll in the transceiver block has a dedicated reset signal. the transceiver block also has a power-down signal that affects all the channels and cmu plls in the transceiver block. figure 4?1. reset control and power-down block reset controller tx_digitalreset rx_digitalreset rx_analogreset pll_powerdown gxb_powerdown siv52004-4.0 4?2 chapter 4: reset control and power down user reset and power-down signals stratix iv device handbook volume 2 ? november 2009 altera corporation 1 all reset and power-down signals are asynchronous. table 4?1 lists the reset signals available for each transceiver channel. table 4?2 lists the power-down signals available for each cmu pll transceiver block. tab le 4 ?1 . transceiver channel reset signals signal altgx megawizard plug-in manager configurations description tx_digitalreset (1) transmitter only receiver and transmitter provides asynchronous reset to all digital logic in the transmitter pcs, including the xaui transmit state machine. the minimum pulse width for this signal is two parallel clock cycles. rx_digitalreset (1) receiver only receiver and transmitter resets all digital logic in the receiver pcs, including: xaui receiver state machines gige receiver state machines xaui channel alignment state machine bist-prbs verifier bist-incremental verifier the minimum pulse width for this signal is two parallel clock cycles. rx_analogreset receiver only receiver and transmitter resets the receiver cdr present in the receiver channel. the minimum pulse width is two parallel clock cycles. note to tab l e 4 ?1 : (1) assert this signal until the clocks coming out of the transmitter pll and receiver cdr are stabilized. stable parallel clocks are essential for proper operation of transmitter and receiver phase-compensation fifos in the pcs. tab le 4 ?2 . transceiver block power-down signals (part 1 of 2) signal description pll_powerdown (1) each transceiver block has two cmu plls. each cmu pll has this dedicated power-down signal. this signal powers down the cmu plls that provide high-speed serial and low-speed parallel clocks to the transceiver channels. gxb_powerdown (1) powers down the entire transceiver block. when this signal is asserted, this signal powers down: the pcs and pma in all the transceiver channels the cmu plls this signal operates independently from the other reset signals. this signal is common to the transceiver block. pll_locked a status signal. indicates the status of the transmitter pll. a high level?the transmitter pll is locked to the incoming reference clock frequency. rx_pll_locked a status signal. a high level?the receiver cdr is locked to the incoming reference clock frequency. chapter 4: reset control and power down 4?3 user reset and power-down signals ? november 2009 altera corporation stratix iv device handbook volume 2 f for more information about offset cancellation, refer to the stratix iv dynamic reconfiguration chapter . 1 if none of the channels is instantiated in a transceiver block, the quartus ? ii software automatically powers down the entire transceiver block. blocks affected by the reset and power-down signals table 4?3 lists the blocks that are affected by specific reset and power-down signals. rx_freqlocked a status signal. indicates the status of the receiver cdr lock mode. a high level?the receiver is in lock-to-data mode. a low level?the receiver cdr is in lock-to-reference mode. busy a status signal. an output from the altgx_reconfig block indicates the status of the dynamic reconfiguration controller. this signal remains low for the first reconfig_clk clock cycle after power up. it then gets asserted from the second reconfig_clk clock cycle. assertion on this signal indicates that the offset cancellation process is being executed on the receiver buffer as well as the receiver cdr. when this signal is de-asserted, it indicates that offset cancellation is complete. note to tab l e 4 ?2 : (1) the refclk ( refclk0 or refclk1 ) buffer is not powered down by this signal. tab le 4 ?2 . transceiver block power-down signals (part 2 of 2) signal description tab le 4 ?3 . blocks affected by reset and power-down signals (part 1 of 2) transceiver block rx_digitalreset rx_analogreset tx_digitalreset pll_powerdown gxb_powerdown cmu plls ? ? ? vv transmitter phase compensation fifo ??v ? v byte serializer ? ? v ? v 8b/10b encoder ? ? v ? v serializer ? ? v ? v transmitter buffer ? ? ? ? v transmitter xaui state machine ??v ? v receiver buffer ? ? ? ? v receiver cdr ? v ?? v receiver deserializer ? ? ? ? v receiver word aligner v ??? v receiver deskew fifo v ??? v receiver clock rate compensation fifo v ??? v receiver 8b/10b decoder v ??? v receiver byte deserializer v ??? v 4?4 chapter 4: reset control and power down transceiver reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation transceiver reset sequences you can configure transceiver channels in stratix iv gx devices in various configurations. in all functional modes except xaui functional mode, transceiver channels can be either bonded or non-bonded. in xaui functional mode, transceiver channels must be bonded. in pci express (pipe) functional mode, transceiver channels can be either bonded or non-bonded and need to follow a specific reset sequence. the two categories of reset sequences for stratix iv gx devices described in this chapter are: ?all supported functional modes except the pci express (pipe) functional mode? on page 4?5 ?describes the reset sequences in bonded and non-bonded configurations. ?pci express (pipe) functional mode? on page 4?20 ?describes the reset sequence for the initialization/compliance phase and the normal operation phase in pci express (pipe) functional modes. 1 the busy signal remains low for the first reconfig_clk clock cycle. it then gets asserted from the second reconfig_clk clock cycle. subsequent de-assertion of the busy signal indicates the completion of the offset cancellation process. this busy signal is required in transceiver reset sequences except for transmitter only channel configurations. refer to the reset sequences shown in figure 4?2 and the associated references listed in the notes for the figure. 1 altera strongly recommends adhering to these reset sequences for proper operation of the stratix iv gx transceiver. receiver byte ordering v ??? v receiver phase compensation fifo v ??? v receiver xaui state machine v ??? v bist verifiers v ??? v tab le 4 ?3 . blocks affected by reset and power-down signals (part 2 of 2) transceiver block rx_digitalreset rx_analogreset tx_digitalreset pll_powerdown gxb_powerdown chapter 4: reset control and power down 4?5 transceiver reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 figure 4?2 shows the transceiver reset sequences for stratix iv gx devices. all supported functional modes except the pci express (pipe) functional mode this section describes reset sequences for transceiver channels in bonded and non-bonded configurations. timing diagrams of some typical configurations are shown to facilitate proper reset sequence implementation. in these functional modes, you can set the receiver cdr either in automatic lock or manual lock mode. 1 in manual lock mode, the receiver cdr locks to the reference clock (lock-to-reference) or the incoming serial data (lock-to-data), depending on the logic levels on the rx_locktorefclk and rx_locktodata signals. with the receiver cdr in manual lock mode, you can either configure the transceiver channels in the stratix iv gx device in a non-bonded configuration or a bonded configuration. in a bonded configuration, for example in xaui mode, four channels are bonded together. figure 4?2. transceiver reset sequences chart notes to figure 4?2 : (1) refer to the timing diagram in figure 4?12 . (2) refer to the timing diagram in figure 4?3 . (3) refer to the timing diagram in figure 4?4 . (4) refer to the timing diagram in figure 4?5 . (5) refer to the timing diagram in figure 4?6 . (6) refer to the timing diagram in figure 4?7 . (7) refer to the timing diagram in figure 4?8 . (8) refer to the timing diagram in figure 4?9 . (9) refer to the timing diagram in figure 4?10 . (10) refer to the timing diagram in figure 4?11 . (11) refer to the timing diagram in figure 4?13 . (12) refer to the timing diagram in figure 4?16 . (13) refer to the timing diagram in figure 4?17 . (14) refer to the timing diagram in figure 4?18 . (15) refer to the timing diagram in figure 4?19 . transcei v er initialization reset sequences all su pported functional modes except pci express (pipe) and pma direct dri v e mode pci express (pipe) pma direct dri v e initialization/ compliance and normal operation phases (1) xn x1 ?transmitter only? channel (11) ?receiv er and transmitter? channel ?receiv er and transmitter? channel receiv er cdr in man u al lock mode (15) receiv er cdr in au tomatic lock mode (14) receiv er cdr in man u al lock mode (13) receiv er cdr in au tomatic lock mode (12) receiv er cdr in automatic lock mode (9) receiv er cdr in man ual lock mode (10) receiv er cdr in man ual lock mode (8) receiv er cdr in automatic lock mode (7) ?receiv er only? channel ?receiv er and transmitter? channel non-bonded bonded ?transmitter only? channel (2) ?transmitter only? channel (2) ?receiv er and t r ansmitter? channel receiv er cdr in automatic lock mode (3) receiv er cdr in man ual lock mode (4) receiv er cdr in man ual lock mode (6) receiv er cdr in automatic lock mode (5) dynamic reconfigu ration reset sequence to change the data rate of the transcei v er channel reset sequence to change the tx pll settings the transcei v er channel 4?6 chapter 4: reset control and power down transceiver reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation table 4?4 lists the lock-to-reference (ltr) and lock-to-data (ltd) controller lock modes for the rx_locktorefclk and rx_locktodata signals. bonded channel configuration in a bonded channel configuration, you can reset all the bonded channels simultaneously. examples of bonded channel configurations are the xaui, pci express (pipe), and basic 4 functional modes. in basic 4 functional mode, you can bond transmitter only channels together. in xaui mode, the receiver and transmitter channels are bonded. each of the receiver channels in this mode has its own output status signals, rx_pll_locked and rx_freqlocked . you must consider the timing of these signals in the reset sequence. table 4?5 lists the reset and power-down sequences for bonded configurations under the stated functional modes. tab le 4 ?4 . lock-to-reference and lock-to-data modes rx_locktorefclk rx_locktodata ltr/ltd controller lock mode 1 0 manual, ltr mode ? 1 manual, ltd mode 0 0 automatic lock mode tab le 4 ?5 . reset and power-down sequences for bonded channel configurations channel set up receiver cdr mode refer to transmitter only basic 4 ?transmitter only channel? on page 4?7 receiver and transmitter automatic lock mode for xaui functional mode ?receiver and transmitter channel?receiver cdr in automatic lock mode? on page 4?8 receiver and transmitter manual lock mode for xaui functional mode ?receiver and transmitter channel?receiver cdr in manual lock mode? on page 4?10 receiver and transmitter automatic lock mode for basic 8 functional mode ?receiver and transmitter channel?receiver cdr in automatic lock mode? on page 4?12 receiver and transmitter manual lock mode for basic 8 functional mode ?receiver and transmitter channel?receiver cdr in manual lock mode? on page 4?13 chapter 4: reset control and power down 4?7 transceiver reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 transmitter only channel this configuration contains only a transmitter channel. if you create a transmitter only instance in the altgx megawizard plug-in manager in basic 4 functional mode, use the reset sequence shown in figure 4?3 . as shown in figure 4?3 , perform the following reset procedure for the transmitter only channel configuration: 1. after power up, assert pll_powerdown for a minimum period of t pll_powerdown (the time between markers 1 and 2). 2. keep the tx_digitalreset signal asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 3. when the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), de-assert the tx_digitalreset signal (marker 4). at this point, the transmitter is ready for transmitting data. figure 4?3. sample reset sequence for four transmitter only channels note to figure 4?3 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. reset and power-down signals 12 4 output status signals 3 pll_powerdown tx_digitalreset pll_locked pll_powerdown (1) t 4?8 chapter 4: reset control and power down transceiver reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation receiver and transmitter channel?receiver cdr in automatic lock mode this configuration contains both a transmitter and receiver channel. for xaui functional mode, with the receiver cdr in automatic lock mode, use the reset sequence shown in figure 4?4 . figure 4?4. sample reset sequence for four receiver and transmitter channels?receiver cdr in automatic lock mode notes to figure 4?4 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltd _ a ut o duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. pll _ po w erdo w n tx _ digitalreset reset signals o u tp u t stat u s signals pll _ locked 12 3 4 7 7 rx _ analogreset 6 rx _ digitalreset 8 bu sy 5 two parallel clock cycles rx_freq locked[0] rx_freq locked[3] pll_powerdown (1) t ltd_auto (2) t chapter 4: reset control and power down 4?9 transceiver reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 as shown in figure 4?4 , perform the following reset procedure for the receiver cdr in automatic lock mode configuration: 1. after power up, assert pll_powerdown for a minimum period of t pll_powerdown (the time between markers 1 and 2). 2. keep the tx_digitalreset, rx_analogreset , and rx_digitalreset signals asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 3. after the transmitter pll locks, as indicated by the pll_locked signal going high, de-assert the tx_digitalreset signal. at this point, the transmitter is ready for data traffic. 4. for the receiver operation, after de-assertion of busy signal, wait for two parallel clock cycles to de-assert the rx_analogreset signal. after rx_analogreset is de-asserted, the receiver cdr of each channel starts locking to the receiver input reference clock. 5. wait for the rx_freqlocked signal from each channel to go high. the rx_freqlocked signal of each channel may go high at different times (indicated by the slashed pattern at marker 7). 6. in a bonded channel group, when the rx_freqlocked signals of all the channels has gone high, from that point onwards, wait for at least t ltd_ auto time for the receiver parallel clock to be stable, then de-assert the rx_digitalreset signal (marker 8). at this point, all the receivers are ready for data traffic. 4?10 chapter 4: reset control and power down transceiver reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation receiver and transmitter channel?receiver cdr in manual lock mode this configuration contains both a transmitter and receiver channel. for xaui functional mode, with the receiver cdr in manual lock mode, use the reset sequence shown in figure 4?5 . figure 4?5. sample reset sequence for four receiver and transmitter channels?receiver cdr in manual lock mode notes to figure 4?5 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltr _ lt d_ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (3) for t ltd _ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. pll _ po w erdo w n tx _digitalreset rx _analogreset rx _digitalreset reset signals o u tp u t stat u s signals pll _ locked 1 2 3 4 7 8 9 cdr control signals 8 6 7 8 8 bu sy 5 two parallel clock cycles rx_locktorefclk[0] rx_locktorefclk[3] rx_locktodata[0] rx_locktodata[3] rx_pll_locked[0] rx_pll_locked[3] pll_powerdown (1) t ltd_manual (3) t ltr_ltd_manual (2) t chapter 4: reset control and power down 4?11 transceiver reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 as shown in figure 4?5 , perform the following reset procedure for the receiver cdr in manual lock mode configuration: 1. after power up, assert pll_powerdown for a minimum period of t pll_powerdown (the time between markers 1 and 2). 2. keep the tx_digitalreset, rx_analogreset, rx_digitalreset , and rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 3. after the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), de-assert the tx_digitalreset signal (marker 4). for the receiver operation, after de-assertion of the busy signal, wait for two parallel clock cycles to de-assert the rx_analogreset signal. after the rx_analogreset signal is de-asserted, the receiver cdr of each channel starts locking to the receiver input reference clock because rx_locktorefclk is asserted. 4. wait for the rx_pll_locked signal from each channel to go high. the rx_pll_locked signal of each channel may go high at different times with respect to each other (indicated by the slashed pattern at marker 7). 5. in a bonded channel group, when the rx_pll_locked signal of all the channels have gone high, from that point onwards, wait for at least t ltr _ltd_man ual time, then de-assert rx_locktorefclk and assert rx_locktodata (marker 8). at this point, the receiver cdr of all the channels enters into lock-to-data mode and starts locking to the received data. 6. after asserting the rx_locktodata signal, wait for at least t ltd_ man ua l time before de-asserting rx_digitalreset (the time between markers 8 and 9). 4?12 chapter 4: reset control and power down transceiver reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation receiver and transmitter channel?receiver cdr in automatic lock mode this configuration contains both a transmitter and a receiver channel. for basic 8 functional mode, with the receiver cdr in automatic lock mode, use the reset sequence shown in figure 4?6 . as shown in figure 4?6 , perform the following reset procedure for the receiver cdr in automatic lock mode: 1. after power up, assert pll_powerdown for a minimum period of t pll_powerdown (the time between markers 1 and 2). 2. keep the tx_digitalreset, rx_analogreset , and rx_digitalreset signals asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 3. after the transmitter pll locks, as indicated by the pll_locked signal going high, de-assert the tx_digitalreset signal. at this point, the transmitter is ready for data traffic. 4. for the receiver operation, after de-assertion of the busy signal, wait for two parallel clock cycles to de-assert the rx_analogreset signal. after rx_analogreset is de-asserted, the receiver cdr of each channel starts locking to the receiver input reference clock. figure 4?6. sample reset sequence for eight receiver and transmitter channels?receiver cdr in automatic lock mode notes to figure 4?6 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltd _ a ut o duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. pll_ po w erdo w n tx _digitalreset reset signals o u tp u t stat u s signals pll _ locked 12 3 4 7 7 rx_analogreset 6 rx _digitalreset 8 bu sy 5 two parallel clock cycles rx_freq locked[0] rx_freq locked[8] pll_powerdown (1) t ltd_auto (2) t chapter 4: reset control and power down 4?13 transceiver reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 5. wait for the rx_freqlocked signal from each channel to go high. the rx_freqlocked signal of each channel may go high at different times (indicated by the slashed pattern at marker 7). 6. in a bonded channel group, when the rx_freqlocked signals of all the channels have gone high, from that point onwards, wait for at least t ltd_auto time for the receiver parallel clock to stabilize, then de-assert the rx_digitalreset signal (marker 8). at this point, all the receivers are ready for data traffic. receiver and transmitter channel?receiver cdr in manual lock mode this configuration contains both a transmitter and receiver channel. for basic 8 functional mode, with the receiver cdr in manual lock mode, use the reset sequence shown in figure 4?7 . figure 4?7. sample reset sequence for eight receiver and transmitter channels?receiver cdr in manual lock mode notes to figure 4?7 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltr _ lt d_ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (3) for t ltd _ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. pll _ po w erdo w n tx _digitalreset rx _analogreset rx _digitalreset reset signals o u tp u t stat u s signals pll _ locked 12 3 4 7 8 9 cdr control signals 8 6 7 8 8 bu sy 5 two parallel clock cycles rx_locktorefclk[0] rx_locktorefclk[3] rx_locktodata[0] rx_locktodata[3] rx_pll_locked[0] rx_pll_locked[7] pll_powerdown (1) t ltd_manual (3) t ltr_ltd_manual (2) t 4?14 chapter 4: reset control and power down transceiver reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation as shown in figure 4?7 , perform the following reset procedure for the receiver cdr in manual lock mode: 1. after power up, assert pll_powerdown for a minimum period of t pll_powerdown (the time between markers 1 and 2). 2. keep the tx_digitalreset, rx_analogreset, rx_digitalreset , and rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 3. after the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), de-assert the tx_digitalreset signal (marker 4). for the receiver operation, after de-assertion of the busy signal, wait for two parallel clock cycles to de-assert the rx_analogreset signal. after the rx_analogreset signal is de-asserted, the receiver cdr of each channel starts locking to the receiver input reference clock because rx_locktorefclk is asserted. 4. wait for the rx_pll_locked signal from each channel to go high. the rx_pll_locked signal of each channel may go high at different times with respect to each other (indicated by the slashed pattern at marker 7). 5. in a bonded channel group, when the rx_pll_locked signal of all the channels has gone high, from that point onwards, wait for at least t ltr_ ltd_ manua l time, then de-assert rx_locktorefclk and assert rx_locktodata (marker 8). at this point, the receiver cdr of all the channels enters into lock-to-data mode and starts locking to the received data. 6. de-assert rx_digitalreset at least t ltd_ man ua l time (the time between markers 8 and 9) after asserting the rx_locktodata signal. non-bonded channel configuration in non-bonded channels, each channel in the altgx megawizard plug-in manager instance contains its own tx_digitalreset, rx_analogreset, rx_digitalreset, rx_pll_locked , and rx_freqlocked signals. you can reset each channel independently. for example, if there are four non-bonded channels, the altgx megawizard plug-in manager provides four each of the following signals: tx_digitalreset, rx_analogreset , rx_digitalreset, rx_pll_locked , and rx_freqlocked. table 4?6 lists the reset and power-down sequences for one channel in a non-bonded configuration under the stated functional modes. tab le 4 ?6 . reset and power-down sequences for bonded channel configurations (part 1 of 2) channel set up receiver cdr mode refer to transmitter only basic 4 ?transmitter only channel? on page 4?15 receiver only automatic lock mode ?receiver only channel?receiver cdr in automatic lock mode? on page 4?15 receiver only manual lock mode ?receiver only channel?receiver cdr in manual lock mode? on page 4?16 chapter 4: reset control and power down 4?15 transceiver reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 1 follow the same reset sequence for all the other channels in the non-bonded configuration. transmitter only channel this configuration contains only a transmitter channel. if you create a transmitter only instance in the altgx megawizard plug-in manager, use the same reset sequence shown in figure 4?3 on page 4?7 . receiver only channel?receiver cdr in automatic lock mode this configuration contains only a receiver channel. if you create a receiver only instance in the altgx megawizard plug-in manager with the receiver cdr in automatic lock mode, use the reset sequence shown in figure 4?8 . receiver and transmitter automatic lock mode ?receiver and transmitter channel?receiver cdr in automatic lock mode? on page 4?17 receiver and transmitter manual lock mode ?receiver and transmitter channel?receiver cdr in manual lock mode? on page 4?19 tab le 4 ?6 . reset and power-down sequences for bonded channel configurations (part 2 of 2) channel set up receiver cdr mode refer to figure 4?8. sample reset sequence of receiver only channel?receiver cdr in automatic lock mode note to figure 4?8 : (1) for t ltd _ a ut o duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. reset signals rx _ analogreset 2 o u tp u t stat u s signals rx _ fre q locked 3 rx _ digitalreset 4 bu sy 1 two parallel clock cycles ltd_auto (1) t 4?16 chapter 4: reset control and power down transceiver reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation as shown in figure 4?8 , perform the following reset procedure for the receiver in cdr automatic lock mode: 1. after power up, wait for the busy signal to be de-asserted. 2. de-assert the rx_analogreset signal. 3. keep the rx_digitalreset signal asserted during this time period. after you de-assert the rx_analogreset signal, the receiver cdr starts locking to the receiver input reference clock. 4. wait for the rx_freqlocked signal to go high. 5. when rx_freqlocked goes high (marker 3), from that point onwards, wait for at least t ltd_auto , then de-assert the rx_digitalreset signal (marker 4). at this point, the receiver is ready to receive data. receiver only channel?receiver cdr in manual lock mode this configuration contains only a receiver channel. if you create a receiver only instance in the altgx megawizard plug-in manager with receiver cdr in manual lock mode, use the reset sequence shown in figure 4?9 . figure 4?9. sample reset sequence of receiver only channel?receiver cdr in manual lock mode notes to figure 4?9 : (1) for t ltr _ lt d duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltd _ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. rx _ analogreset rx _ digitalreset reset signals o u tp u t stat u s signals rx _ locktorefclk 2 4 5 cdr control signals rx_pll_locked 3 rx _ locktodata 4 bu sy 1 two parallel clock cycles ltd_manual (2) t ltr_ltd_manual (1) t chapter 4: reset control and power down 4?17 transceiver reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 as shown in figure 4?9 , perform the following reset procedure for the receiver cdr in manual lock mode: 1. after power up, wait for the busy signal to be asserted. 2. keep the rx_digitalreset and rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted during this time period. 3. after de-assertion of the busy signal, de-assert the rx_analogreset signal. the receiver cdr then starts locking to the receiver input reference clock because the rx_locktorefclk signal is asserted. 4. wait for at least t ltr_ ltd_ man ua l time (the time between markers 3 and 4) after the rx_pll_locked signal goes high and then de-assert the rx_locktorefclk signal. at the same time, assert the rx_locktodata signal (marker 4). at this point, the receiver cdr enters lock-to-data mode and the receiver pll starts locking to the received data. 5. de-assert rx_digitalreset at least t ltd_ man ua l (the time between markers 4 and 5) after asserting the rx_locktodata signal. receiver and transmitter channel?receiver cdr in automatic lock mode this configuration contains both a transmitter and a receiver channel. if you create a receiver and transmitter instance in the altgx megawizard plug-in manager with the receiver cdr in automatic lock mode, use the reset sequence shown in figure 4?10 . figure 4?10. sample reset sequence of receiver and transmitter channel?receiver cdr in automatic lock mode notes to figure 4?10 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltd _ a ut o duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. pll _ po w erdo w n tx _ digitalreset rx _ analogreset reset signals o u tp u t stat u s signals pll _ locked 12 3 4 6 rx _ fre q locked 7 rx _ digitalreset 8 busy 5 two parallel clock cycles pll_powerdown (1) t ltd_auto (2) t 4?18 chapter 4: reset control and power down transceiver reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation as shown in figure 4?10 , perform the following reset procedure for the receiver in cdr automatic lock mode: 1. after power up, assert pll_powerdown for a minimum period of t pll_powerdown (the time between markers 1 and 2). 2. keep the tx_digitalreset, rx_analogreset , and rx_digitalreset signals asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 3. after the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), de-assert tx_digitalreset . for receiver operation, wait for the busy signal to be de-asserted, after which rx_analogreset is de-asserted. after you de-assert rx_analogreset , the receiver cdr starts locking to the receiver input reference clock. 4. wait for the rx_freqlocked signal to go high (marker 7). 5. after the rx_freqlocked signal goes high, wait for at least t lt d _ au t o , then de-assert the rx_digitalreset signal (marker 8). at this point, the transmitter and receiver are ready for data traffic. chapter 4: reset control and power down 4?19 transceiver reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 receiver and transmitter channel?receiver cdr in manual lock mode this configuration contains both a transmitter and receiver channel. if you create a receiver and transmitter instance in the altgx megawizard plug-in manager with the receiver cdr in manual lock mode, use the reset sequence shown in figure 4?11 . figure 4?11. sample reset sequence of receiver and transmitter channel?receiver cdr in manual lock mode notes to figure 4?11 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltr _ lt d_ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (3) for t ltd _ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. pll _ po w erdo w n tx _digitalreset rx _analogreset rx _digitalreset reset signals o u tp u t stat u s signals pll _ locked rx_pll_locked rx _ locktorefclk 12 3 4 6 7 8 9 cdr control signals rx _ locktodata 8 bu sy 5 two parallel clock cycles pll_powerdown (1) t ltd_manual (3) t ltr_ltd_manual (2) t 4?20 chapter 4: reset control and power down transceiver reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation as shown in figure 4?11 , perform the following reset procedure for the receiver in manual lock mode: 1. after power up, assert pll_powerdown for a minimum period of t pll_powerdown (the time between markers 1 and 2). 2. keep the tx_digitalreset, rx_analogreset, rx_digitalreset , and rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 3. after the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), de-assert tx_digitalreset . for receiver operation, wait for the busy signal to be de-asserted. at this point rx_analogreset is de-asserted. when rx_analogreset is de-asserted, the receiver cdr starts locking to the receiver input reference clock because rx_locktorefclk is asserted. 4. wait for at least t ltr_ ltd_ man ua l (the time between markers 7 and 8) after the rx_pll_locked signal goes high, then de-assert the rx_locktorefclk signal. at the same time, assert the rx_locktodata signal (marker 8). at this point, the receiver cdr enters lock-to-data mode and the receiver cdr starts locking to the received data. 5. de-assert rx_digitalreset at least t ltd_ man ua l (the time between markers 8 and 9) after asserting the rx_locktodata signal. pci express (pipe) functional mode you can configure pci express (pipe) functional mode with or without the receiver clock rate compensation fifo in the stratix iv gx device. the reset sequence remains the same whether or not you use the receiver clock rate compensation fifo. chapter 4: reset control and power down 4?21 transceiver reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 pci express (pipe) reset sequence pci express (pipe) protocol consists of an initialization/compliance phase and a normal operation phase. the reset sequences for these two phases are described based on the timing diagram in figure 4?12 . pci express (pipe) initialization/compliance phase after the device is powered up, a pci express (pipe)-compliant device goes through the compliance phase during initialization. in this phase, the pci express (pipe) protocol requires the system to be operating at gen1 data rate. the rx_digitalreset signal must be de-asserted during this compliance phase to achieve transitions on the pipephydonestatus signal, as expected by the link layer. the rx_digitalreset signal is de-asserted based on the assertion of the rx_freqlocked signal. figure 4?12. reset sequence of pci express (pipe) functional mode notes to figure 4?12 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) the minimum t1 and t2 period is 4 s. (3) the minimum t3 period is two parallel clock cycles. pll _ po w erdo w n tx _ digitalreset rx _ analogreset rx _ digitalreset reset / po w er do w n signals o u tp u t stat u s signals pll _locked rx _ pll _locked 12 3 4 6 7 8 t1 (2) rx _ fre q locked 9 initialization / compliance phase normal operation phase t2 (2) ignore receive data 10 11 12 13 t3 (3) bu sy 5 two parallel clock cycles pll_powerdown (1) t 4?22 chapter 4: reset control and power down transceiver reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation during the initialization/compliance phase, do not use the rx_freqlocked signal to trigger a de-assertion of the rx_digitalreset signal. instead, perform the following reset sequence: 1. after power up, assert pll_powerdown for a minimum period of t pll_powerdown (the time between markers 1 and 2). keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 2. when the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), de-assert tx_digitalreset . for a receiver operation, wait for the busy signal to be de-asserted. rx_analogreset is then de-asserted. after rx_analogreset is de-asserted, the receiver cdr starts locking to the receiver input reference clock. 3. when the receiver cdr locks to the input reference clock, as indicated by the rx_pll_locked signal going high at marker 7 in figure 4?12 , de-assert the rx_digitalreset signal (marker 8). after de-asserting rx_digitalreset , the pipephydonestatus signal transitions from the transceiver channel to indicate the status to the link layer. depending on its status, pipephydonestatus helps with the continuation of the compliance phase. after successful completion of this phase, the device enters into the normal operation phase. pci express (pipe) normal phase for the normal pci express (pipe) phase: 1. after completion of the initialization/compliance phase, during the normal operation phase at the gen1 data rate, when the rx_freqlocked signal is de-asserted (marker 10 in figure 4?12 ), wait for the rx_pll_locked signal assertion signifying the lock-to-reference clock. 2. wait for the rx_freqlocked signal to go high again. in this phase, the received data is valid (not electrical idle) and the receiver cdr locks to the incoming data. proceed with the reset sequence after assertion of the rx_freqlocked signal. 3. after the rx_freqlocked signal goes high, wait for at least 4 s before asserting rx_digitalreset (marker 12 in figure 4?12 ) for two parallel receive clock cycles so that the receiver phase compensation fifo is initialized. 4. during normal operation, after you speed-negotiate to the gen2 data rate, asserting the rx_digitalreset signal causes the pci express (pipe) rate switch circuitry to switch the transceiver to the gen1 data rate. data from the transceiver block is not valid from the time the rx_freqlocked signal goes low (marker 10 in figure 4?12 ) to the time rx_digitalreset is de-asserted (marker 13 in figure 4?12 ). the pld logic ignores the data during this period (between markers 10 and 13 in figure 4?12 ). 1 you can configure the stratix iv gx device in 1, 4, and 8 pci express (pipe) configurations. the reset sequence described in ?pci express (pipe) reset sequence? on page 4?21 applies to all these multi-lane configurations. chapter 4: reset control and power down 4?23 pma direct drive mode reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 pma direct drive mode reset sequences stratix iv gx devices provide a pma direct mode in which all pcs blocks, including the phase compensation fifos, are bypassed in both the transmitter and receiver channel data paths. in this mode, the pma block in the transmitter and receiver channels directly interface with the fpga fabric. in pma direct drive mode, you can configure the transceiver channels as a single channel or in bonded configurations. basic single- and double-width functional modes support bonding of pma functional blocks across all transceiver channels on the same side of the device. 1 the tx_digitalreset and rx_digitalreset signals are not available because there are no pcs blocks available in this mode. table 4?7 lists the reset and power-down sequences for pma direct drive n functional mode. tab le 4 ?7 . reset and power-down sequences for pma direct drive n configurations channel set up functional mode refer to transmitter only with no pll_l/r basic (pma direct) drive 4 ?transmitter only channel with no pll_l/r? on page 4?24 transmitter only with a pll_l/r manual lock mode ?transmitter only channel with a pll_l/r? on page 4?25 receiver and transmitter automatic lock mode for basic (pma direct) drive n mode ?receiver and transmitter channel set-up?receiver cdr in automatic lock mode? on page 4?27 receiver and transmitter manual lock mode for basic (pma direct) drive n mode ?receiver and transmitter channel set-up?receiver cdr in manual lock mode? on page 4?29 4?24 chapter 4: reset control and power down pma direct drive mode reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation basic (pma direct) drive n mode when bonding n channels in a basic (pma direct) drive mode configuration, you can reset all bonded channels simultaneously. transmitter only channel with no pll_l/r an example reset sequence timing diagram of four transmitter only channels in basic (pma direct) drive 4 functional mode with no pll_l/r is shown in figure 4?13 . as shown in figure 4?13 , perform the following reset procedure for the transmitter only channel in basic (pma direct) drive functional 4 mode with no pll_l/r: 1. after power up, assert pll_powerdown for a minimum of t pll_powerdown (the time between markers 1 and 2). 2. when the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), the transmitter is ready to accept parallel data from the fpga fabric and subsequently transmitting serial data reliably. figure 4?13. reset sequence timing in basic (pma direct) drive 4 mode note to figure 4?13 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. 12 ouput status si g nals 3 pll_po w erdo wn pll_locked reset and power-down si gnals pll_powerdown (1) t chapter 4: reset control and power down 4?25 pma direct drive mode reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 transmitter only channel with a pll_l/r the basic (pma direct) mode configuration that requires a pll_l/r is one where each channel in pma-direct mode is identical. figure 4?14 shows a simple set up of identical channels. identical channels have the following same configuration: same effective data rate. having the same transmitter local clock divider settings in each channel same fpga fabric-to-transceiver interface data path width. the transmitter channels must receive the high-speed clock from the same pll (either cmu pll or atx pll). figure 4?15 shows an example reset sequence timing diagram of four transmitter only channels in basic (pma direct) drive -x4 functional mode with a pll_l/r. as shown in figure 4?15 , perform the following reset procedure for the transmitter only channel in basic (pma direct) drive functional mode with a pll_l/r configuration: 1. after power up, assert pll_powerdown for a minimum of t pll_powerdown (the time between markers 1 and 2). 2. after the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), wait for the locked signal to be asserted. the locked signal is an output of the pll_l/r. 3. after the pll_l/r locks, as indicated by the locked signal going high (marker 4), the transmitter is ready to accept parallel data from the fpga fabric and subsequently transmitting serial data reliably. figure 4?14. identical channels transmitter channels in basic (pma direct) mode ch0 (2.5 gbps) ch1 (2.5 gbps) ch2 (2.5 gbps) ch3 (2.5 gbps) transmitter side user logic in the fpga fa b ric left and right pll (altpll) locked c0 tx_datain[9:0] pll_locked tx_clko ut inclk0 refclk cmu channel configured for clock generation (2.5 gbps) high-speed serial clock 4?26 chapter 4: reset control and power down pma direct drive mode reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation figure 4?15. reset sequence timing diagram of four transmitter-only channels in basic (pma direct) drive 4 functional mode note to figure 4?15 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. 12 3 4 reset and po w er-do wn signals pll_po w erdo wn output status signals pll_locked locked (o utput of pll_l/r) keep the tx side user logic under reset until this point pll_powerdown (1) t chapter 4: reset control and power down 4?27 pma direct drive mode reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 receiver and transmitter channel set-up?receiver cdr in automatic lock mode this configuration contains both a transmitter and receiver channel. for pma direct drive n mode, with the receiver cdr in automatic lock mode, use the reset sequence shown in figure 4?16 . in this example, n = 4. figure 4?16. reset sequence with cdr in automatic lock mode notes to figure 4?16 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltd _ a ut o duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. reset and power down si g nals ouput status si g nals 12 3 6 6 5 4 two parallel clock cycles 5 valid parallel data into fpga fabric 7 bu sy pll_locked pll_po w erdo wn rx_analogreset[0] rx_analogreset[3] rx_freq locked[0] rx_freq locked[3] rx_dataout[63:0] pll_powerdown (1) t ltd_auto (2) t 4?28 chapter 4: reset control and power down pma direct drive mode reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation as shown in figure 4?16 , perform the following reset procedure for the receiver and transmitter channel in pma direct drive 4 double-width configuration with cdr in automatic lock mode: 1. after power up, assert pll_powerdown for a minimum period of 1 pll_powerdown (the time between markers 1 and 2). 2. keep the rx_analogreset signal asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 3. when the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), the transmitter is ready to accept parallel data from the fpga fabric and transmitting serial data reliably. 4. for the receiver operation, after de-assertion of the busy signal, wait for two parallel clock cycles to de-assert the rx_analogreset signals of each channel. after rx_analogreset is de-asserted, the receiver cdr of each channel starts locking to the receiver input reference clock. 5. wait for the rx_freqlocked signal from each channel to go high. the rx_freqlocked signal of each channel may go high at different times (as indicated by the slashed pattern at marker 6). 6. in a pma direct drive 4 double-width configuration, when the rx_freqlocked signals of all the channels has gone high (marker 6), from that point onwards, wait for at least t lt d _ a ut o (marker 7) for the receiver parallel clock to become stable. at this point, all the receivers are ready for transferring valid parallel data into the fpga fabric (until this time, altera recommends that the user logic that processes this data be under reset). chapter 4: reset control and power down 4?29 pma direct drive mode reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 receiver and transmitter channel set-up?receiver cdr in manual lock mode this configuration contains both a transmitter and receiver channel. for pma direct drive n mode, with receiver cdr in manual lock mode, use the reset sequence shown in figure 4?17 . in this example, n = 4. figure 4?17. reset sequence with cdr in manual lock mode notes to figure 4?17 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltr _ lt d_ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (3) for t ltd _ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. reset and power down si g nals ouput status si g nals 12 3 6 7 cdr control si g nals 7 5 6 7 7 4 two parallel clock cycles 5 valid parallel data into fpga fabric 8 pll_po w erdo wn pll_locked bu sy rx_analogreset[3] rx_analogreset[0] rx_locktorefclk[0] rx_locktorefclk[3] rx_locktodata[0] rx_locktodata[3] rx_pll_locked[0] rx_pll_locked[3] rx_dataout[63:0] pll_powerdown (1) t ltr_ltd_manual (2) t ltd_manual (3) t 4?30 chapter 4: reset control and power down pma direct drive mode reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation as shown in figure 4?17 , perform the following reset procedure for the receiver and transmitter channel in pma direct drive 4 double-width configuration with cdr in manual lock mode: 1. after power up, assert pll_powerdown for a minimum period of t pll_powerdown (the time between markers 1 and 2). 2. keep the rx_analogreset and rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 3. when the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), the transmitter is ready to accept parallel data from the fpga fabric and transmitting serial data reliably. 4. for the receiver operation, after de-assertion of the busy signal (marker 4), wait for two parallel clock cycles to de-assert the rx_analogreset signal. after the rx_analogreset signal is de-asserted, the receiver cdr of each channel starts locking to the receiver input reference clock because rx_locktorefclk is asserted. 5. wait for the rx_pll_locked signal from each channel to go high. the rx_pll_locked signal of each channel may go high at different times with respect to each other (indicated by the slashed pattern at marker 6). 6. in a pma direct drive 4 double-width configuration, when the rx_pll_locked signal of all the channels has gone high, from that point onwards, wait for at least t ltr _ltd_man ual , then de-assert rx_locktorefclk and assert rx_locktodata (marker 7). at this point, the receiver cdr of all the channels enters into lock-to-data mode and starts locking to the received data. 7. after assertion of the rx_locktodata signal, from that point onwards, wait for at least t ltd_ma nual (marker 8) for the receiver parallel clock to become stable. at this point, all the receivers are ready for transferring valid parallel data into the fpga fabric (until this time, altera recommends that the user logic that processes this data be under reset). basic (pma direct) drive x1 mode the following timing diagram examples are used to describe the reset and power down sequences for basic (pma direct) drive mode without bonding between the transceiver channels. table 4?8 lists the reset and power-down sequences for basic (pma direct) drive 1 functional mode. tab le 4 ?8 . reset and power-down sequences for basic (pma direct) drive 1 configurations channel set up functional mode refer to receiver and transmitter automatic lock mode for basic (pma direct) drive 1 mode ?receiver and transmitter channel set-up?receiver cdr in automatic lock mode? on page 4?31 receiver and transmitter manual lock mode for basic (pma direct) drive 1 mode ?receiver and transmitter channel set-up?receiver cdr in manual lock mode? on page 4?33 chapter 4: reset control and power down 4?31 pma direct drive mode reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 receiver and transmitter channel set-up?receiver cdr in automatic lock mode this configuration contains both a transmitter and receiver channel. for basic (pma direct) drive 1 mode, with receiver cdr in automatic lock mode, use the reset sequence shown in figure 4?18 . in this example, four channels are configured in this mode. figure 4?18. reset sequence with cdr in automatic lock mode notes to figure 4?18 : (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltd _ a ut o duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. reset and power down si g nals ouput status si g nals 12 3 4 6 bu sy 5 two parallel clock cycles 6 5 3 valid parallel data into fpga fabric 7 pll_po w erdo wn[0] pll_po w erdo wn[3] rx_analogreset[0] rx_analogreset[3] pll_locked[0] pll_locked[3] rx_freq locked[0] rx_freq locked[3] rx_dataout[63:0] pll_powerdown (1) t tld_auto (2) t 4?32 chapter 4: reset control and power down pma direct drive mode reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation as shown in figure 4?18 , perform the following reset procedure for the receiver and transmitter channel in basic (pma direct) drive double-width configuration, non-bonded with cdr in automatic lock mode: 1. after power up, assert pll_powerdown of each channel for a minimum period of t pll_powerdown (the time between markers 1 and 2). 2. keep the rx_analogreset signal of each channel asserted during this time period. after you de-assert the pll_powerdown signal on all channels, the transmitter pll of each channel starts locking to the transmitter input reference clock. 3. when the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), the transmitters are ready for accepting parallel data from the fpga fabric and subsequently transmitting serial data reliably. 4. for the receiver operation, after de-assertion of the busy signal, wait for two parallel clock cycles to de-assert the rx_analogreset signals of each channel. after rx_analogreset is de-asserted, the receiver cdr of each channel starts locking to the receiver input reference clock. 5. wait for the rx_freqlocked signal from each channel to go high. the rx_freqlocked signal of each channel may go high at different times (indicated by the slashed pattern at marker 6). 6. in a basic (pma direct) drive double-width configuration without bonding between channels, when the rx_freqlocked signals of all the channels have gone high (marker 6), from that point onwards, wait for at least t ltd_ auto (marker 7) for the receiver parallel clock to become stable. at this point, all the receivers are ready for transferring valid parallel data into the fpga fabric (until this time, altera recommends that the user logic that processes this data be under reset). chapter 4: reset control and power down 4?33 pma direct drive mode reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 receiver and transmitter channel set-up?receiver cdr in manual lock mode this configuration contains both a transmitter and receiver channel. for basic (pma direct) drive 1 mode, with receiver cdr in manual lock mode, use the reset sequence shown in figure 4?19 . in this example, four channels are configured in this mode. figure 4?19. reset sequence with cdr in manual lock mode notes to figure 4?19 (1) for t pll_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltr _ lt d_ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (3) for t ltd _ m an ua l duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. reset and power down si g nals ouput status si g nals 12 3 6 7 cdr control si g nals 7 5 6 7 7 bu sy 4 two parallel clock cycles 5 valid parallel data into fpga fabric 8 pll_locked pll_po w erdo wn[0] pll_po w erdo wn[3] rx_analogreset[0] rx_analogreset[3] rx_locktorefclk[0] rx_locktorefclk[3] rx_locktodata[0] rx_locktodata[3] rx_pll_locked[0] rx_pll_locked[3] rx_dataout[63:0] pll_powerdown (1) t ltr_ltd_manual (2) t ltd_manual (3) t 4?34 chapter 4: reset control and power down dynamic reconfiguration reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation as shown in figure 4?19 , perform the following reset procedure for the receiver and transmitter channel in basic (pma direct) drive double-width configuration, non-bonded with cdr in manual lock mode: 1. after power up, assert pll_powerdown of each channel for a minimum period of t pll_powerdown (the time between markers 1 and 2). 2. keep the rx_analogreset and rx_locktorefclk signals of each channel asserted and the rx_locktodata signals de-asserted during this time period. after you de-assert the pll_powerdown signal, the transmitter pll starts locking to the transmitter input reference clock. 3. when the transmitter pll locks, as indicated by the pll_locked signal going high (marker 3), the transmitters are ready to accept parallel data from the fpga fabric and subsequently transmitting serial data reliably. 4. for the receiver operation, after de-assertion of the busy signal (marker 4), wait for two parallel clock cycles to de-assert the rx_analogreset signal of each channel. after the rx_analogreset signal is de-asserted, the receiver cdr of each channel starts locking to the receiver input reference clock because rx_locktorefclk is asserted. 5. wait for the rx_pll_locked signal from each channel to go high. the rx_pll_locked signal of each channel may go high at different times with respect to each other (indicated by the slashed pattern at marker 6). 6. in a basic (pma direct) drive double-width configuration without bonding between channels, when the rx_pll_locked signal of all the channels has gone high, from that point onwards, wait for at least t lt r _ lt d _ m a n u a l , then de-assert rx_locktorefclk and assert rx_locktodata (marker 7). at this point, the receiver cdr of all the channels enters into lock-to-data mode and starts locking to the received data. 7. after assertion of the rx_locktodata signal, from that point onwards, wait for at least t ltd_ma nual (marker 8) for the receiver parallel clock to be stable. at this point, all the receivers are ready for transferring valid parallel data into the fpga fabric (until this time, altera recommends that the user logic that processes this data be reset). dynamic reconfiguration reset sequences when using dynamic reconfiguration in data rate divisions in tx or channel and tx cmu pll select/reconfig modes, use the following reset sequences. reset sequence when using dynamic reconfiguration with the ?data rate division in tx? option use the example reset sequence shown in figure 4?20 when you use the dynamic reconfiguration controller to change the data rate of the transceiver channel. in this example, dynamic reconfiguration is used to dynamically reconfigure the data rate of the transceiver channel configured in basic 1 mode with the receiver cdr in automatic lock mode. chapter 4: reset control and power down 4?35 dynamic reconfiguration reset sequences ? november 2009 altera corporation stratix iv device handbook volume 2 as shown in figure 4?20 , perform the following reset procedure when using the dynamic reconfiguration controller to change the configuration of the transmitter channel: 1. after power up and properly establishing that the transmitter is operating as desired, write the desired new value for the data rate in the appropriate register (in this example, rate_switch_ctrl[1:0] ) and subsequently assert the write_all signal (marker 1) to initiate the dynamic reconfiguration. f for more information, refer to the stratix iv dynamic reconfiguration chapter. 2. assert the tx_digitalreset signal. 3. as soon as write_all is asserted, the dynamic reconfiguration controller starts to execute its operation. this is indicated by the assertion of the busy signal (marker 2). 4. after the completion of dynamic reconfiguration, the busy signal is de-asserted (marker 3). 5. lastly, tx_digitalreset can be de-asserted to continue with the transmitter operation (marker 4). figure 4?20. reset sequence when using the dynamic reconfiguration controller to change the data rate of the transceiver channel reset and control si g nals ouput status si g nals bu sy 2 1 new value 3 4 1 tx_digitalreset rate_s w itch_ctrl[1:0] w rite_all 4?36 chapter 4: reset control and power down dynamic reconfiguration reset sequences stratix iv device handbook volume 2 ? november 2009 altera corporation reset sequence when using dynamic reconfiguration with the ?channel and tx pll select/reconfig? option use the example reset sequence shown in figure 4?21 when you are using the dynamic reconfiguration controller to change the tx pll settings of the transceiver channel. in this example, the dynamic reconfiguration is used to dynamically reconfigure the data rate of the transceiver channel configured in basic 1 mode with receiver cdr in automatic lock mode. figure 4?21. reset sequence when using the dynamic reconfiguration controller to change the tx pll settings of the transceiver channel note to figure 4?21 : (1) for t ltd _ a ut o duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. reset and control si g nals 4 ouput status si g nals 7 8 bu sy 2 five parallel clock cycles 1 new value 3 6 1 1 1 5 tx_digitalreset rx_analogreset rx_digitalreset reconfig_mode_sel[2:0] w rite_all channel_reconfig_done rx_freq locked ltd_auto (1) t chapter 4: reset control and power down 4?37 power down ? november 2009 altera corporation stratix iv device handbook volume 2 as shown in figure 4?21 , perform the following reset procedure when using the dynamic reconfiguration controller to change the configuration of the transceiver channel: 1. after power up and establishing that the transceiver is operating as desired, write the desired new value in the appropriate registers (including reconfig_mode_sel[2:0] ) and subsequently assert the write_all signal (marker 1) to initiate the dynamic reconfiguration. f for more information, refer to the stratix iv dynamic reconfiguration chapter. 2. assert the tx_digitalreset, rx_analogreset , and rx_digitalreset signals. 3. as soon as write_all is asserted, the dynamic reconfiguration controller starts to execute its operation. this is indicated by the assertion of the busy signal (marker 2). 4. wait for the assertion of the channel_reconfig_done signal (marker 4) that indicates the completion of dynamic reconfiguration in this mode. 5. after assertion of the channel_reconfig_done signal, de-assert tx_digitalreset (marker 5) and wait for at least five parallel clock cycles to de-assert the rx_analogreset signal (marker 6). 6. lastly, wait for the rx_freqlocked signal to go high. after rx_freqlocked goes high (marker 7), wait for t ltd_auto to de-assert the rx_digitalreset signal (marker 8). at this point, the receiver is ready for data traffic. power down the quartus ii software automatically selects the power-down channel feature, which takes effect when you configure the stratix iv gx device. all unused transceiver channels and blocks are powered down to reduce overall power consumption. the gxb_powerdown signal is an optional transceiver block signal. it powers down all transceiver channels and all functional blocks in the transceiver block. the minimum pulse width for this signal is 1 s. after power up, if you use the gxb_powerdown signal, wait for de-assertion of the busy signal, then assert the gxb_powerdown signal for a minimum of 1 s. lastly, follow the sequence shown in figure 4?22 . the de-assertion of the busy signal indicates proper completion of the offset cancellation process on the receiver channel. 4?38 chapter 4: reset control and power down simulation requirements stratix iv device handbook volume 2 ? november 2009 altera corporation simulation requirements the following are simulation requirements: the gxb_powerdown port is optional. in simulation, if the gxb_powerdown port is not instantiated, you must assert the tx_digitalreset, rx_digitalreset, and rx_analogreset signals appropriately for correct simulation behavior. if the gxb_powerdown port is instantiated, and the other reset signals are not used, you must assert the gxb_powerdown signal for at least one parallel clock cycle for correct simulation behavior. you can de-assert the rx_digitalreset signal immediately after the rx_freqlocked signal goes high to reduce the simulation run time. it is not necessary to wait for t ltd_ aut o (as suggested in the actual reset sequence). the busy signal is de-asserted after about 20 parallel reconfig_clk clock cycles in order to reduce simulation run time. for silicon behavior in hardware, you can follow the reset sequences described in the previous pages. in pci express (pipe) mode simulation, you must assert the tx_forceelecidle signal for at least one parallel clock cycle before transmitting normal data for correct simulation behavior. figure 4?22. sample reset sequence of four receiver and transmitter channels-receiver cdr in automatic lock mode with the optional gxb_powerdown signal notes to figure 4?22 : (1) for t gxb_powerdown duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. (2) for t ltd _ a ut o duration, refer to the dc and switching characteristics chapter in the ?stratix iv device datasheet? section. o u tp u t stat u s signals 4 5 6 7 8 3 2 bu sy 1 gxb_powerdown (1) t ltd_auto (2) t reset/po w er do wn signals gxb_po w erdo wn pll_po w erdo wn tx_digitalreset rx_analogreset rx_digitalreset pll_locked rx_freq locked chapter 4: reset control and power down 4?39 reference information ? november 2009 altera corporation stratix iv device handbook volume 2 reference information for more information about some useful reference terms used in this chapter, refer to the links listed in table 4?9 . tab le 4 ?9 . reference information terms used in this chapter useful reference points automatic lock mode page 4?8 basic (pma direct) drive x1 mode page 4?30 basic (pma direct) drive xn mode page 4?24 bonded channel configuration page 4?6 busy page 4?3 dynamic reconfiguration reset sequences page 4?34 gxb_powerdown page 4?2 ltd page 4?6 ltr page 4?6 manual lock mode page 4?10 non-bonded channel configuration page 4?14 pci express (pipe) page 4?21 pll_locked page 4?2 pll_powerdown page 4?2 rx_analogreset page 4?2 rx_digitalreset page 4?2 rx_freqlocked page 4?3 rx_pll_locked page 4?2 tx_digitalreset page 4?2 4?40 chapter 4: reset control and power down document revision history stratix iv device handbook volume 2 ? november 2009 altera corporation document revision history table 4?10 shows the revision history for this chapter. table 4?10. document revision history date and document version changes made summary of changes november 2009, v4.0 added tab le 4 ?1 , ta bl e 4? 2, tab le 4 ?5 , table 4?6 , tab le 4 ?7 , and ta ble 4? 8 . added the ?reference information? section. updated all figures (except figure 1). changed ?pll_powerdown? to ?pll_powerdown? throughout. minor text edits. updated all figures (except figure 1, figure 2, and figure 14) and all sections so they use the same terms that are found in the dc and switching characteristics chapter in the stratix iv device datasheet section. june 2009, v3.1 added new ? transmitter only channel with a pll_l/r? section. updated the ?transmitter only channel with no pll_l/r? and ?transmitter only channel? sections. minor text edits. ? march 2009, v3.0 added: ?pma direct drive mode reset sequences? ?dynamic reconfiguration reset sequences? ? november 2008, v2.0 added chapter to the stratix iv device handbook .? ? march 2010 altera corporation stratix iv device handbook volume 2 5. stratix iv dynamic reconfiguration stratix ? iv gx and gt transceivers allow you to dynamically reconfigure different portions of the transceivers without powering down any part of the device. this chapter describes and provides examples about the different modes available for dynamic reconfiguration. you can use the altgx_reconfig instance to reconfigure the physical medium attachment (pma) controls, functional blocks, clock multiplier unit (cmu) phase-locked loops (plls), receiver clock data recovery (cdr), and input reference clocks of a transceiver channel. additionally, you can monitor the receiver eye width, implement decision feedback control, and achieve adaptive equalization (aeq) control with dynamic reconfiguration. this chapter contains the following sections: ?glossary of terms? on page 5?1 ?dynamic reconfiguration controller architecture? on page 5?3 ?quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration? on page 5?4 ?dynamic reconfiguration modes implementation? on page 5?12 ?dynamic reconfiguration controller port list? on page 5?78 ?error indication during dynamic reconfiguration? on page 5?91 ?dynamic reconfiguration duration? on page 5?92 ?dynamic reconfiguration (altgx_reconfig instance) resource utilization? on page 5?95 ?functional simulation of the dynamic reconfiguration process? on page 5?96 ?dynamic reconfiguration examples? on page 5?96 glossary of terms table 5?1 lists the terms used in this chapter: tab le 5 ?1 . glossary of terms used in this chapter (part 1 of 2) ter m d es cri pt ion aeq control logic adaptive equalization control logic is soft ip that you can enable in the dynamic reconfiguration controller. aeq hardware adaptive equalization hardware is circuitry that you can enable in the receiver portion of the transceivers. altgx_reconfig instance dynamic reconfiguration controller instance generated by the altgx_reconfig megawizard ? plug-in manager. altgx instance transceiver instance generated by the altgx megawizard plug-in manager. siv52005-3.1 5?2 chapter 5: stratix iv dynamic reconfiguration glossary of terms stratix iv device handbook volume 2 ? march 2010 altera corporation alternate cmu transmitter pll refers to one of the two cmu plls within one transceiver block. channel and transmitter pll select/reconfig mode refers to the following dynamic reconfiguration modes: cmu pll reconfiguration channel and cmu pll reconfiguration channel reconfiguration with transmitter pll select central control unit reconfiguration logical channel addressing used whenever the concept of logical channel addressing is explained. this term does not refer to the logical_channel_address port available in the altgx_reconfig megawizard plug-in manager. logical reference index refers to the logical identification value that you must set up for the transmitter plls used in the design. you can use a set up value of 0, 1, 2 or 3 in the reconfiguration settings screen of the altgx megawizard plug-in manager. logical tx pll refers to the logical reference index value of the transmitter plls stored in the memory initialization file ( .mif ). main pll refers to the transmitter pll configured in the general screen of the altgx megawizard plug-in manager. memory initialization file, also known as .mif when you enable .mif generation in your design, a file with the .mif extension is generated. this file contains information about the various altgx megawizard plug-in manager options that you set. each word in the .mif is 16 bits wide. the dynamic reconfiguration controller writes information from the .mif into the transceiver channel, but only when you use a reconfiguration mode that supports .mif -based reconfiguration. pma controls represents analog controls ( voltage output differential [ v od ], pre-emphasis , and manual equalization ) as displayed in both the altgx and altgx_reconfig megawizard plug-in managers. pma-only channels channels configured in basic (pma direct) functional mode. regular transceiver channel refers to a transmitter channel, a receiver channel, or a duplex channel that has both pma and physical coding sublayer (pcs) blocks. tab le 5 ?1 . glossary of terms used in this chapter (part 2 of 2) ter m d es cri pt ion chapter 5: stratix iv dynamic reconfiguration 5?3 dynamic reconfiguration controller architecture ? march 2010 altera corporation stratix iv device handbook volume 2 dynamic reconfiguration controller architecture the dynamic reconfiguration controller is a soft ip that utilizes fpga-fabric resources. you can use only one controller per transceiver block. you cannot use the dynamic reconfiguration controller to control multiple stratix iv devices or any off-chip interfaces. figure 5?1 shows a conceptual view of the dynamic reconfiguration controller architecture. for a detailed description of the inputs and outputs of the altgx_reconfig instance, refer to ?dynamic reconfiguration controller port list? on page 5?78 . 1 you can use only one altgx_reconfig instance per transceiver block. you may use a single altgx_reconfig instance with multiple transceiver blocks. figure 5?1. dynamic reconfiguration controller note to figure 5?1 : (1) the pma control ports consist of the v od , pre-emphasis, dc gain, and manual equalization controls. (2) for more information, refer to table 5?16 on page 5?78 . cmu pll reconfig control logic data rate switch control logic offset cancellation control logic channel reconfig with tx pll select control logic channel and cmu pll reconfig control logic rate_s witch_ctrl[1:0](tx only) reconfig_data[15:0] logical_tx_pll_sel reconfig_address_o ut[6:0] rate_s witch_out_[1:0] (tx only) reset_reconfig_address eyeq control logic aeq control logic central control unit reconfig logic ctrl_ write ctrl_ waitrequest aeq_fromgxb[] altgx_reconfig mega wizard plug-in manager altgx_reconfig instance (dynamic reconfigu ration controller) reconfig_clk read w rite_all pma control ports (1) logical_tx_pll_sel_en logical_channel_address[] rx_tx_du plex_sel[] ctrl_read ctrl_address[15:0] ctrl_ writedata[15:0] reconfig_mode_sel[] aeq_togxb[] ctrl_readdata[15:0] reconfig_address_en channel_reconfig_done error bu sy data v alid reconfig_togx b[3:0] reconfig_fromgxb[] altgx mega wizard plug-in manager altgx instances parallel to serial con v erter addr data address translation pma controls reconfig logic reconfig_address[5:0] (2) 5?4 chapter 5: stratix iv dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic stratix iv device handbook volume 2 ? march 2010 altera corporation quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration stratix iv gx devices provide two megawizard plug-in manager interfaces to support dynamic reconfiguration?altgx and altgx_reconfig. altgx megawizard plug-in manager use the altgx megawizard plug-in manager to enable dynamic reconfiguration settings for the transceiver instances. f for more information, refer to the ?reconfiguration settings? section of the altgx transceiver setup guide chapter. the reconfig_clk clock requirements for the altgx instance you must connect the reconfig_clk port to the altgx instance in all the configurations using the dynamic reconfiguration feature. table 5?2 lists the source clock for the offset cancellation circuit in the altgx instance, based on its configuration. select the reconfig_clk frequency based on the altgx configuration shown in table 5?3 . this clock must be a free-running clock sourced from an i/o clock pin. do not use dedicated transceiver refclk pins or any clocks generated by transceivers. 1 altera recommends that you drive the reconfig_clk signal on a global clock resource. this clock must be a free-running clock sourced from an i/o clock pin. do not use dedicated transceiver refclk pins or any clocks generated by transceivers. tab le 5 ?2 . source clock for the offset cancellation circuit in the altgx instance source clock for the offset cancellation circuit (1) altgx configurations reconfig_clk receiver only and transmitter only reconfig_clk receiver and transmitter fixedclk pci express (pipe) note to figure 5?2 : (1) the clock source used for offset cancellation must be a free running clock that is not derived from the pll as this clock is required for offset cancellation at power up. tab le 5 ?3 . reconfig_clk settings for the altgx instance altgx instance configuration reconfig_clk frequency range (mhz) receiver and transmitter 37.5 to 50 receiver only 37.5 to 50 transmitter only and pci express (pipe) 2.5 (1) to 50 note to figure 5?3 : (1) the source clock for the offset cancellation circuit in the altgx instance must be faster than 37.5 mhz. offset cancellation is not required for transmitters and is accomplished using a fixed clock in pci express (pipe) mode. chapter 5: stratix iv dynamic reconfiguration 5?5 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? march 2010 altera corporation stratix iv device handbook volume 2 altgx_reconfig megawizard plug-in manager use the altgx_reconfig megawizard plug-in manager to instantiate the dynamic reconfiguration controller. f for more information, refer to the stratix iv altgx_reconfig megafunction user guide . the reconfig_clk clock requirements for the altgx_reconfig instance you must connect the reconfig_clk input port of the altgx_reconfig instance to the same clock that is connected to the reconfig_clk input port of the altgx instance. table 5?3 on page 5?4 lists the range of frequency values allowed for the reconfig_clk input port for receiver only , receiver and transmitter , and transmitter only configuration modes of the altgx instance. based on the altgx configurations ( receiver only , transmitter only , and receiver and transmitter ) controlled by the altgx_reconfig instance, select the fastest reconfig_clk frequency value. this satisfies both the offset cancellation control for the receiver channels and the dynamic reconfiguration of the transmitter and receiver channels. interfacing altgx and altgx_reconfig instances to dynamically reconfigure the transceiver channel, you must understand the concepts related to interfacing the transceivers with the dynamic reconfiguration controller. these concepts are: ?logical channel addressing? on page 5?5 ?total number of channels option in the altgx_reconfig instance? on page 5?10 ?connecting the altgx and altgx_reconfig instances? on page 5?11 logical channel addressing the dynamic reconfiguration controller identifies a transceiver channel by using the logical channel address. the what is the starting channel number? option in the altgx megawizard plug-in manager allows you to set the logical channel address of all the channels within the altgx instance. for channel reconfiguration with transmitter pll select mode, the logical channel addressing concept extends to transmitter plls. for more information, refer to ?logical channel addressing when using additional plls? on page 5?52 . the following sections describe the concept of logical channel addressing for altgx instances configured with: regular transceiver channels (pcs and pma channels) pma-only channels a combination of pma-only channels and regular transceiver channels 5?6 chapter 5: stratix iv dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic stratix iv device handbook volume 2 ? march 2010 altera corporation logical channel addressing of regular transceiver channels for a single altgx instance connected to the dynamic reconfiguration controller, set the starting channel number to 0 . the logical channel addresses of the first channel within the altgx instance is 0. the logical channel addresses of the remaining channels increment by one. for multiple altgx instances connected to the dynamic reconfiguration controller, set the starting channel number of the first instance to 0 . for the starting channel number for the following altgx instances, you must set the next multiple of four. the logical channel address of channels within each altgx instance increment by one. figure 5?2 shows how to set the starting channel number for multiple altgx instances controlled by a single dynamic reconfiguration controller, where both altgx instances have regular transceiver channels. figure 5?2. logical channel addressing of regular transceiver channels notes to figure 5?2 : (1) for more information, refer to ?total number of channels option in the altgx_reconfig instance? on page 5?10 . (2) reconfig_fromgxb[50:0] = { reconfig_fromgxb 2[16:0], reconfig_fromgxb 1[33:0]}. altgx instance 1 five regular transceiver channels basic functional mode starting channel number = 0 altgx instance 2 two regular transceiver channels basic functional mode starting channel number = 8 channel 1 (logical channel address = 9) reconfig_togxb[3:0] channel 0 (logical channel address = 0) channel 1 (logical channel address = 1) channel 2 (logical channel address = 2 channel 3 (logical channel address = 3) channel 4 (logical channel address = 4) channel 0 (logical channel address = 8) reconfig_fromgxb 1[33:0] reconfig_fromgxb 2[16:0] set the what is the number of channels controlled by the reconfig controller? option to 12 (1) reconfig_fromgxb[50:0] (2) altgx_reconfig instance 1 chapter 5: stratix iv dynamic reconfiguration 5?7 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? march 2010 altera corporation stratix iv device handbook volume 2 logical channel addressing of pma-only channels 1 cmu channels are always pma-only channels. the regular transceiver channels can be optionally configured as pma-only channels. set the starting channel number for the pma-only channels in the what is the starting channel number? option in the altgx megawizard plug-in manager. for a single altgx instance connected to the dynamic reconfiguration controller, set the starting channel number to 0 . the logical channel address of the first channel in the altgx instance is 0. the logical channel addresses of the pma-only channels within the same altgx instance increment in multiples of four (unlike the logical channel addressing of regular transceiver channels that are not configured in basic [pma direct] functional mode, where the logical channel address increments in steps of one within the same altgx instance). for multiple altgx instances connected to the dynamic reconfiguration controller, set the starting channel number of the first instance to 0 . you must set the next multiple of four as the starting channel number for the remaining altgx instances. figure 5?3 shows how to set the starting channel number for multiple altgx instances controlled by a single dynamic reconfiguration controller, where both altgx instances have pma-only channels. for more information about the what is the number of channels controlled by the reconfig controller? option, refer to ?total number of channels option in the altgx_reconfig instance? on page 5?10 . 1 when pma-only channel reconfiguration involves a transmitter pll, you also must account for the logical channel address of the pll used. if there are four channels in basic [pma direct] n functional mode, each channel requires a logical channel address ( 0, 4, 8, 12 ), and the transmitter pll used requires an address ( 16). 5?8 chapter 5: stratix iv dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic stratix iv device handbook volume 2 ? march 2010 altera corporation figure 5?3. logical channel addressing of pma-only channels note to figure 5?3 : (1) reconfig_fromgxb[203:0] = { reconfig_fromgxb 2[67:0], reconfig_fromgxb 1[135:0]}. starting channel n u m b er = 0 altgx_reconfig instance 1 reconfig_togxb[3:0] channel 0 (logical channel address = 0) set the what is the number of channels controlled by the reconfig controller? option to 48 reconfig_fromgxb 1[135:0] reconfig_fromgxb 2[67:0] reconfig_fromgxb[203:0] (1) altgx instance 1 basic (pma direct) configuration channel 1 (logical channel address = 4) channel 2 (logical channel address = 8) channel 3 (logical channel address = 12) channel 4 (logical channel address = 16) channel 5 (logical channel address = 20) channel 6 (logical channel address = 24) channel 7 (logical channel address = 28) starting channel n u m b er = 32 altgx instance 2 basic (pma direct) configuration channel 0 (logical channel address = 32) channel 1 (logical channel address = 36 channel 2 (logical channel address = 40) channel 3 (logical channel address = 44) chapter 5: stratix iv dynamic reconfiguration 5?9 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? march 2010 altera corporation stratix iv device handbook volume 2 logical channel addressing?combination of regular transceiver channels and pma-only channels for a combination of regular transceiver channels and pma-only channels, there must be at least two different altgx instances connected to the same dynamic reconfiguration controller. this is because you cannot have a combination of regular transceiver channels and pma-only channels within the same altgx instance. set the starting channel number in the first altgx instance 1 to 0 . if you have configured altgx instance 1 with regular transceiver channels, the logical channel addresses of the remaining channels increment in steps of one. set the starting channel number of the following altgx instance 2 as the next multiple of four. if you have configured altgx instance 2 with pma-only channels, the logical channel addresses of the remaining channels increment in steps of four. figure 5?42 in ?example 1? on page 5?96 shows how to set the starting channel number for multiple altgx instances controlled by a single dynamic reconfiguration controller, where one altgx instance has pma-only channels and the other altgx instance has regular transceiver channels. table 5?18 in ?example 1? on page 5?96 lists an example scenario where the logical channel address of both the pma-only channels and regular transceiver channels is set based on the starting channel number. for more information, refer to ?example 1? on page 5?96 . highest possible logical channel address table 5?4 lists the highest possible logical channel address assigned to a transceiver channel in a stratix iv device. the maximum number of transceiver channels in the largest stratix iv device is 48 (24 transceiver channels located in four transceiver blocks on the right side of the device and 24 transceiver channels located in four transceiver blocks on the left side of the device). you can individually configure these 48 transceiver channels as 48 transmitter only and 48 receiver only channels. you achieve this by using 48 transmitter only altgx instances and 48 receiver only altgx instances in your design. 5?10 chapter 5: stratix iv dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic stratix iv device handbook volume 2 ? march 2010 altera corporation the highest logical channel address is assigned to the receiver only channel in the 96 th altgx instance; therefore, the setting is 380. 1 the highest possible logical channel address assigned to a transceiver channel in a stratix iv device is the same whether the channel is a regular transceiver channel or a pma-only channel. total number of channels option in the altgx_re config inst ance you can connect every dynamic reconfiguration controller in a design to either a single altgx instance or to multiple altgx instances. depending on the number of channels within each of these altgx instances, you must set the total number of channels controlled by the dynamic reconfiguration controller in the altgx_reconfig megawizard plug-in manager. based on this information, the reconfig_fromgxb and logical_channel_address input ports vary in width. use the following steps to determine the number of channels: 1. determine the highest logical channel address among all the transceiver instances connected to the same dynamic reconfiguration controller. for more information, refer to ?logical channel addressing? on page 5?5 . 2. round the logical channel address value to the next higher multiple of four. 3. use this value to set the what is the number of channels controlled by the reconfig controller? option. for more information, refer to ?example 1? on page 5?96 . tab le 5 ?4 . highest possible logical channel address 96 altgx instances altgx_reconfig instance altgx megawizard plug-in manager setting altgx instance 1 altgx instance 2 altgx_reconfig instance 1: controls all 96 altgx instances. what is the number of channels? in the general screen 48 48 what is the starting channel number? in the reconfig screen tx instance 1: 0 tx instance 2: 4 . . . . . . tx instance 48: 188 rx instance 1: 192 rx instance 2: 196 . . . . . . rx instance 48: 380 chapter 5: stratix iv dynamic reconfiguration 5?11 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? march 2010 altera corporation stratix iv device handbook volume 2 connecting the altgx and altgx_reconfig instances there are two ways to connect the altgx_reconfig instance to the altgx instance in your design: single dynamic reconfiguration controller?you can use a single altgx_reconfig instance to control all the altgx instances in your design. figure 5?2 on page 5?6 shows a block diagram of a single dynamic reconfiguration controller in a design. multiple dynamic reconfiguration controllers?your design can have multiple altgx_reconfig instances but you can use only one altgx_reconfig instance per transceiver block, as shown in figure 5?4 . in the dynamic reconfiguration interface, you must connect the reconfig_fromgxb and reconfig_togxb signals between the altgx_reconfig instance and the altgx instance to successfully complete the dynamic reconfiguration process. make the following connections: connect the reconfig_fromgxb input port of the altgx_reconfig instance to the reconfig_fromgxb output ports of all the altgx instances controlled by the altgx_reconfig instance. connect the reconfig_fromgxb port of the altgx instance whose starting channel number is 0, to the lowest significant bit of the reconfig_fromgxb input port of the altgx_reconfig instance. connect the reconfig_fromgxb port of the altgx instance with the next highest starting channel number to the following bits of the reconfig_fromgxb of the altgx_reconfig instance, and so on. connect the same reconfig_togxb ports of all the altgx instances controlled by the altgx_reconfig instance to the reconfig_togxb output port of the altgx_reconfig instance. the reconfig_togxb output port is fixed to 3bits. figure 5?4. multiple dynamic reconfiguration controllers in a design altgx instance 1 altgx_reconfig instance 1 reconfig_fromgx b [n:0] reconfig_togx b [3:0] altgx instance 2 altgx_reconfig instance 2 reconfig_fromgx b [n:0] reconfig_togx b [3:0] 5?12 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation connecting reconfig_fromgxb for the regular transceiver channels figure 5?3 on page 5?8 shows how to connect the reconfig_fromgxb output port of the altgx instance to the reconfig_fromgxb input port of the altgx_reconfig instance for regular transceiver channels. table 5?18 in ?example 1? on page 5?96 describes how to connect the reconfig_fromgxb port for regular transceiver channels. connecting reconfig_fromgxb for the pma-only channels figure 5?3 on page 5?8 shows how to connect the reconfig_fromgxb output port of the altgx instance to the reconfig_fromgxb input port of the altgx_reconfig instance for pma-only channels. table 5?18 in ?example 1? on page 5?96 describes how to connect the reconfig_fromgxb port for pma-only channels. dynamic reconfiguration modes implementation the modes available for dynamically reconfiguring the stratix iv transceivers are: ?pma controls reconfiguration mode details? on page 5?12 ?transceiver channel reconfiguration mode details? on page 5?19 channel and cmu pll reconfiguration ( .mif based) channel reconfiguration with transmitter pll select ( .mif based) cmu pll reconfiguration ( .mif based) central control unit reconfiguration ( .mif based) data rate division in transmitter ?offset cancellation feature? on page 5?66 ?eyeq? on page 5?69 ?adaptive equalization (aeq)? on page 5?74 ?dynamic reconfiguration controller port list? on page 5?78 the following sections describe each of these modes in detail. pma controls reconfiguration mode details you can dynamically reconfigure the following pma controls for both regular transceiver channels and pma-only channels: pre-emphasis settings equalization settings dc gain settings voltage output differential (v od ) settings pma controls reconfiguration is available for all supported transceiver configurations (altgx configurations). chapter 5: stratix iv dynamic reconfiguration 5?13 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 the following section describes how to connect the transceiver channels (the altgx instance) to the dynamic reconfiguration controller (the altgx_reconfig instance) to dynamically reconfigure the pma controls. the pma control ports for the altgx_reconfig megawizard plug-in manager are available in the analog controls screen. you can select the pma control ports you want to reconfigure. for example, to use tx_vodctrl to write new v od settings or to use tx_vodctrl_out to read the existing v od settings. dynamically reconfiguring pma controls you can dynamically reconfigure the pma controls of a transceiver channel using three methods: reconfiguring the pma controls of a specific transceiver channel. for more information, refer to ?method 1?using the logical_channel_address port? on page 5?13 . dynamically reconfiguring the pma controls of the transceiver channels without using the logical_channel_address port (where all transceiver channels are reconfigured). if you use this method, the pma controls of all the transceiver channels connected to the dynamic reconfiguration controller are reconfigured. for more information, refer to ?method 2?using the same control signals for all channels? on page 5?15 . dynamically reconfiguring the pma controls of the transceiver channels without using the logical_channel_address port (where only the pma controls of the transceiver channels are reconfigured). if you use this method, each channel has its own pma control port. based on the value set at the ports, the pma controls of the corresponding transceiver channels are reconfigured. for more information, refer to ?method 3?using individual control signals for each channel? on page 5?17 . for the above three methods, you can additionally use the rx_tx_duplex_sel[1:0] port transmitter and receiver parameters. for more information, refer to ?dynamic reconfiguration controller port list? on page 5?78 . method 1?using the logical_channel_address port using method 1, you can dynamically reconfigure the pma controls of a transceiver channel by using the logical_channel_address port without affecting the remaining active channels. enable the logical_channel_address port by selecting the use 'logical_channel_address' port for analog controls reconfiguration option in the analog controls screen of the altgx_reconfig megawizard plug-in manager. 1 this method is applicable only for a design where the dynamic reconfiguration controller controls more than one channel. when using method 1, the selected pma control write and read ports remain fixed in width, regardless of the number of channels controlled by the altgx_reconfig instance. to observe the width of the pma control ports, refer to the altgx_reconfig megawizard plug-in manager. 5?14 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation the value you set at the pma control ports is only written into the specified transceiver channel. 1 ensure that the busy signal is low before you start a write or read transaction. the busy output status signal is asserted high when the dynamic reconfiguration controller is occupied writing or reading the pma control values. when the write or read transaction has completed, the busy signal goes low. write transaction figure 5?5 shows the write transaction waveform when using method 1. in this example, the number of channels connected to the dynamic reconfiguration controller is four. therefore, the logical_channel_address port is 2 bits wide. also, to initiate the write transaction, you must assert the write_all signal for one reconfig_clk cycle. figure 5?5. method 1?write transaction waveform reconfig_clk rx_tx_duplex_sel [1:0] write_all 2?b00 2?b10 (transmitter portion only) 2?b01 (second channel of the altgx instance) 2?b00 3?b00 3?b11 busy tx_vodctrl [2:0] logical_address_channel [1:0] chapter 5: stratix iv dynamic reconfiguration 5?15 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 read transaction in this example, you want to read the existing v od values from the transmit v od control registers of the transmitter portion of a specific channel controlled by the altgx_reconfig instance. for this example, the number of channels connected to the dynamic reconfiguration controller is four. therefore, the logical_channel_address port is 2 bits wide. also, to initiate the read transaction, assert the read signal for one reconfig_clk clock cycle. after the read transaction has completed, the data_valid signal is asserted. figure 5?6 shows the read transaction waveform. 1 simultaneous write and read transactions are not allowed. method 2?using the same control signals for all channels to use method 2, enable the use the same control signal for all channels option in the analog controls screen of the altgx_reconfig megawizard plug-in manager. using method 2, you can write the same pma control value into all the transceiver channels connected to the dynamic reconfiguration controller. the pma control write ports remain fixed in width irrespective of the number of channels controlled by the altgx_reconfig instance. the pma control read ports increase in width based on the number of channels controlled by the altgx_reconfig instance. figure 5?6. method 1?read transaction waveform reconfig_clk rx_tx_duplex_sel [1:0] read 2?b00 2?b10 (transmitter portion only) 2?b01 (second channel of the altgx instance) 2?b00 3?b000 3?b001 3?bxxx busy tx_vodctrl [2:0] logical_address_channel [1:0] data_valid 5?16 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation write transaction assume that you have enabled tx_vodctrl in the altgx_reconfig megawizard plug-in manager to reconfigure the v od of the transceiver channels. figure 5?7 shows the write transaction to reconfigure the v od . read transaction if you want to read the existing values from a specific channel connected to the altgx_reconfig instance, observe the corresponding byte positions of the pma control output port after the read transaction is complete. for example, if the number of channels controlled by the altgx_reconfig instance is two, tx_vodctrl_out is 6 bits wide ( tx_vodctrl_out[2:0] corresponds to channel 1 and tx_vodctrl_out[5:3] corresponds to channel 2). figure 5?8 shows how to read the v od values of the second channel. figure 5?7. method 2?write transaction waveform reconfig_clk rx_tx_duplex_sel [1:0] write_all 2?b00 2?b10 (transmitter portion only) 3?b00 3?b11 busy tx_vodctrl [2:0] chapter 5: stratix iv dynamic reconfiguration 5?17 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 figure 5?8 shows the read transaction waveform. the transmit v od settings written in channels 1 and 2 prior to the read transaction are 3'b001 and 3'b010, respectively. 1 simultaneous write and read transactions are not allowed. method 3?using individual control signals for each channel you can optionally used method 3 to individually reconfigure the pma controls of each transceiver channel. when you disable the use the same control signal for all channels option, the pma control ports for the write transaction are also separate for each channel. for example, if you have two channels, tx_vodctrl is 6 bits wide ( tx_vodctrl[2:0] corresponds to channel 1 and tx_vodctrl[5:3] corresponds to channel 2). the width of the pma control ports for a read transaction are always separate for each channel (the same as the pma control ports, as explained in ?method 2?using the same control signals for all channels? on page 5?15 .) figure 5?8. method 2?read transaction waveform note to figure 5?8 : (1) to read the current v od values in channel 2, observe the values in tx_vodctrl_out[5:3] . reconfig_clk rx_tx_duplex_sel [1:0] read 2?b00 2?b10 (transmitter portion only) 6?bxxxxxx 6?b010001 6?b000000 busy tx_vodctrl [5:0] (1) data_valid 5?18 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation write transaction in this method, the pma controls are written into all the channels connected to the dynamic reconfiguration controller. therefore, to write to a specific channel: 1. retain the stored values of the other active channels using a read transaction. 2. set the new value at the bits corresponding to the specific channel. 3. perform a write transaction. for example, assume that the number of channels controlled by the altgx_reconfig instance is two, tx_vodctrl in this case is 6 bits wide ( tx_vodctrl[2:0] corresponds to channel 1 and tx_vodctrl[5:3] corresponds to channel 2). follow these steps: 1. if you want to dynamically reconfigure the pma controls of only channel 2 with a new value, first perform a read transaction to retrieve the existing pma control values from tx_vodctrl_out[5:0] . take tx_vodctrl_out[2:0] and provide this value in tx_vodctrl[2:0] to the write in channel 1. by doing so, channel 1 is overwritten with the same value. 2. perform a write transaction. this ensures that the new values are written only to channel 2, while channel 1 remains unchanged. figure 5?9 shows a write transaction waveform using method 3. 1 simultaneous write and read transactions are not allowed. figure 5?9. method 3?write transaction waveform note to figure 5?9 : (1) for this example, the number of channels controlled by the dynamic reconfiguration controller (altgx_reconfig instance) is two and that the tx_vodctrl control port is enabled. reconfig_clk (1) rx_tx_duplex_sel [1:0] write_all 2?b00 2?b10 (transmitter portion only) 6?b000011 6?b000000 busy tx_vodctrl [5:0] chapter 5: stratix iv dynamic reconfiguration 5?19 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 read transaction the read transaction in method 3 is identical to that in method 2. refer to ?read transaction? on page 5?16 . transceiver channel reconfiguration mode details table 5?5 lists the supported configurations for the various transceiver channel reconfiguration modes available in the altgx_reconfig megawizard plug-in manager. memory initialization file (.mif) as listed in table 5?5 , all the dynamic reconfiguration modes with a check mark in the ? .mif requirement? column use memory initialization files to reconfigure the transceivers. these .mifs contain the valid settings, in the form of words, required to reconfigure the transceivers. to understand using .mifs , it is helpful to understand these two concepts: how to generate a .mif ??the quartus ii software generates .mifs when you provide the appropriate project settings and then compiles an altgx instance. for more information, refer to ?quartus ii settings to enable .mif generation? on page 5?20 . how is a .mif used between the altgx_reconfig instance and the altgx instance??the quartus ii software provides a design flow called the user memory initialization file flow. for more information, refer to ?.mif-based design flow? on page 5?22 . tab le 5 ?5 . transceiver channel reconfiguration modes and .mif requirements dynamic reconfiguration mode supported configurations .mif requirements to from channel and cmu pll reconfiguration all configurations of regular transceiver channels all configurations of regular transceiver channels v basic (pma direct) 1 configuration basic (pma direct) 1 configuration v basic (pma direct) n configuration basic (pma direct) n configuration v channel reconfiguration with transmitter pll select non-bonded configurations of regular transceiver channels non-bonded configurations of regular transceiver channels v basic (pma direct) 1 configuration basic (pma direct) 1 configuration v basic (pma direct) n configuration basic (pma direct) n configuration v central control unit reconfiguration 4 bonded mode 4 bonded mode v 8 bonded mode 8 bonded mode v data rate division in transmitter all transmitter only configurations of regular transceiver channels all transmitter only configurations of regular transceiver channels (1) ? note to tab l e 5 ?5 : (1) because the transmitter local divider is not available for bonded mode channels, data rate division is supported for non-bon ded channels only. 5?20 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation quartus ii settings to enable .mif generation the .mif is not generated by default in a quartus ii compilation. to generate a .mif , you must enable the following quartus ii software settings: 1. on the assignments menu, select settings ( figure 5?10 ). 2. select fitter settings , then choose more settings ( figure 5?11 ). figure 5?10. step 1 to enable .mif generation figure 5?11. step 2 to enable .mif generation chapter 5: stratix iv dynamic reconfiguration 5?21 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 3. in the option box of the more fitter settings page, set the generate gxb reconfig mif option to on ( figure 5?12 ). the .mif is generated in the assembler stage of the compilation process. however, for any change in the design or the above settings, the quartus ii software runs through the fitter stage before starting the assembler stage. a .mif is generated for every altgx instance defined in the top-level rtl file. the quartus ii software creates the .mif under the project_dir>/reconfig_mif folder. the file name is based on the altgx instance name ( 5?22 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation 1 if you have to generate .mifs for many configurations, method 1 takes more time to complete. method 2: 1. in the top-level design, instantiate all the different configurations of the altgx instantiation for which the .mif is required. 2. connect the appropriate clock inputs of all the altgx instantiations. 3. generate the .mif . the .mifs are generated for all the altgx configurations. 1 this method requires special attention when generating the .mif . refer to the following: the different altgx instantiations must have the appropriate logical reference clock index option values. the clock inputs for each instance must be connected to the appropriate clock source. when you generate the .mif , use the proper naming convention for the files so you know the configuration supported by the .mif . .mif-based design flow the .mif -based design flow involves writing the contents of the .mif to the transceiver channel or cmu pll. to reconfigure the transceiver channel or cmu pll, you must configure the required settings for the transceiver channel or cmu pll in the altgx megawizard plug-in manager and compile the altgx instance. the dynamic reconfiguration controller requires that you write these configured settings through the .mif into the transceiver channel or cmu pll (using the write_all and reconfig_data[15:0] signals). the maximum possible size of the .mif is 59 words. each word contains legal register settings of the transceiver channel stored in 16 bits. reconfig_address_out[5:0] provides the address (location) of the 16-bit word in the .mif . table 5?6 lists the .mif size depending on the altgx configuration. you can store these .mifs in the on-chip or off-chip memory. tab le 5 ?6 . .mif size for the altgx configuration altgx configuration .mif size in words (1) pma direct mode duplex ( receiver and transmitter ) + central control unit 60 33 duplex ( receiver and transmitter )5 5 2 7 receiver only 37 14 transmitter only 19 15 note to tab l e 5 ?6 : (1) each word in the .mif is 16 bits wide. chapter 5: stratix iv dynamic reconfiguration 5?23 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 applying a .mif in the user design store the .mif in on-chip or off-chip memory and connect it to the dynamic reconfiguration controller, as shown in figure 5?13 . when applying a . mif in the user design, be sure to: use the ram: 1-port megafunction to instantiate a memory block. choose the size of the memory block based on the size of the .mif generated. instantiate the .mif in the memory block. 1 whenever a .mif is applied to a channel, the pma controls for that channel is set to the default settings chosen in the altgx instance used for .mif generation. reduced .mif reconfiguration this mode is available only for the .mif -based transceiver channel reconfiguration modes. this is an optional feature that allows faster reconfiguration and faster simulation time. for example, if you intend to make minor changes to the transceiver channel, this might involve a change of only a few words in the .mif . figure 5?13. .mif instantiation in the user design gige .mif sonet oc48 ram sonet oc48 .mif reconfigu ration user logic altgx_reconfig instance altgx instances gige channel sonet oc48 channel gige ram 5?24 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation here is an example of changing only the termination setting: assume that the only word difference is word address 32. instead of loading the entire .mif , you can use altgx_diffmifgen.exe to generate a new .mif . this new .mif only has the modified words. the new .mif is 22 bits wide, compared with the 16 bits wide in the regular .mif . there are 6 bits of address in addition to 16 bits of data. chapter 5: stratix iv dynamic reconfiguration 5?25 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 channel reconfiguration classifications table 5?7 lists the classification for channel and cmu pll reconfiguration mode. 1 in addition to the categories mentioned, you can also choose to reconfigure both the data rate and functional mode of a transceiver channel. 1 for the following sections, assume that the transceiver channel has the receiver and transmitter configuration in the altgx megawizard plug-in manager, unless specified as transmitter only or receiver only . blocks reconfigured in channel and cmu pll reconfiguration mode the blocks that are reconfigured by this dynamic reconfiguration mode are the pcs and pma blocks of a transceiver channel, the local divider settings of the transmitter and receiver channel, and the cmu pll. tab le 5 ?7 . channel reconfiguration classifications data rate reconfiguration functional mode reconfiguration by reconfiguring the cmu pll connected to the transceiver channel. by selecting the alternate cmu pll in the transceiver block to supply clocks to the transceiver channel. every transmitter channel has one local clock divider. similarly, every receiver channel has one local clock divider. you can reconfigure the data rate of a transceiver channel by reconfiguring these local clock dividers to 1, 2, or 4. when you reconfigure these local clock dividers, ensure that the functional mode of the transceiver channel supports the reconfigured data rate. use this feature to reconfigure the existing functional mode of the transceiver channel to a totally different functional mode. there is no limit to the number of functional modes you can reconfigure the transceiver channel to if the various clocks involved support the transition. for more information about core clocks, refer to ?clocking/interface options? on page 5?30 . 5?26 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation figure 5?14 shows the functional blocks that you can dynamically reconfigure using the channel and cmu pll reconfiguration mode. 1 channel reconfiguration from either a transmitter only configuration to a receiver only configuration or vice versa is not allowed. altgx megawizard plug-in manager setup for channel and cmu pll reconfiguration mode to reconfigure the transceiver channel and cmu pll, set up the altgx megawizard plug-in manager using the following steps: 1. select the channel and transmitter pll reconfiguration option in the modes screen under the reconfiguration settings tab. 2. if you want to reconfigure the data rate of the transceiver channel by reconfiguring the cmu pll, provide the new data rate you want the cmu pll to run at in the general screen. 3. if you want to reconfigure the data rate of the transceiver channel by switching to the alternate cmu pll within the same transceiver block, select the use alternate cmu transmitter pll option in the modes screen. for more information, refer to the ?using the alternate cmu transmitter pll? on page 5?27 . 4. provide the number of input reference clocks available for the cmu pll in the how many input clocks? option of the corresponding pll screen. the maximum number of input reference clocks allowed is 10. for more information, refer to ?guidelines for specifying the input reference clocks? on page 5?61 . figure 5?14. channel and cmu pll reconfiguration in a transceiver block fu ll d u plex transcei v er channel tx channel rx channel refclk0 refclk1 cmu channel cmu0 pll cmu1 pll local divider tx pma + tx pcs rx pma + rx pcs rx cdr blocks that can be reconfigured in channel and cmu pll reconfigu ration mode clock m ux logical tx pll select clock m ux clock m ux chapter 5: stratix iv dynamic reconfiguration 5?27 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 5. provide the starting channel number in the modes screen. for more information, refer to ?logical channel addressing? on page 5?5 . 6. provide the logical reference index of the cmu pll in the what is the pll logical reference index? option in the corresponding pll screen. for more information, refer to ?selecting the logical reference index of the cmu pll? on page 5?29 . 7. provide the identification of the input reference clock used by the cmu pll in the corresponding pll screens. 8. set up the clocking/interface options. for more information, refer to ?clocking/interface options? on page 5?30 . 9. set up the channel interface options. for more information, refer to ?fpga fabric-transceiver channel interface selection? on page 5?36 . using the alternate cmu transmitter pll to reconfigure the cmu pll during run time, you need the flexibility to select one of the two cmu plls of a transceiver block. consider that the transceiver channel is listening to cmu0 pll and that you want to the reconfigure cmu0 pll, as shown in figure 5?15 . figure 5?15. reconfiguring the cmu0 pll fu ll d u plex transcei v er channel tx channel rx channel local divider acti v e connections main pll logical_tx_pll value = 1 alternate pll logical_tx_pll value = 0 1 0 un u sed connections cmu channels refclk0 refclk1 156.25 mhz 125 mhz 6.25 gbps cmu0 pll 2.5 gbps cmu1 pll logical tx pll select clock m ux 6.25 gbps rx cdr 6.25 gbps tx pma + tx pcs 6.25 gbps rx pma + rx pcs clock m ux clock m ux 5?28 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation you can select cmu0 pll by specifying its identity in the altgx megawizard plug-in manager. this identification is referred to as the logical tx pll value. this value provides a logical identification to cmu0 pll and associates it with a transceiver channel without requiring the knowledge of its physical location. in the altgx megawizard plug-in manager, the transmitter pll configuration set in the general screen is called the main pll. when you provide the alternate pll with a logical tx pll value (for example, 0), the main pll automatically takes the complement value 1. the logical tx pll value for the main pll is stored along with the other transceiver channel information in the generated .mif . 1 the main pll corresponds to the cmu pll configuration set in the general screen of the altgx megawizard plug-in manager. the alternate pll corresponds to the cmu pll configuration set in the alt pll screen. chapter 5: stratix iv dynamic reconfiguration 5?29 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 selecting the logical reference index of the cmu pll in figure 5?16 , transceiver channel 1 listens to cmu0 pll of the transceiver block. similarly, transceiver channel 2 listens to cmu1 pll of the transceiver block. to direct the altgx_reconfig instance to dynamically reconfigure cmu0 pll, specify its logical reference index (the identity of a transmitter pll). similarly, to direct the altgx_reconfig instance to dynamically reconfigure cmu1 pll instead, provide the logical reference index of cmu1 pll. the allowed values for the logical reference index of the cmu plls within a transceiver block are 0 or 1. similarly, the transmitter plls outside the transceiver block can also be assigned a logical reference index value. for more information, refer to ?selecting the pll logical reference index for additional plls? on page 5?53 . figure 5?16. logical reference index of cmu plls in a transceiver block (note 1) note to figure 5?16 : (1) after the device powers up, the busy signal remains low for the first reconfig_clk cycle. fu ll d u plex transcei v er channel 1 tx channel 1 cmu channels full duplex transceiver channel 2 rx cdr tx pma + tx pcs tx channel 2 logical tx pll select rx channel 2 2.5 gbps 2.5 gbps 2.5 gbps local divider clock mux refclk0 refclk1 156.25 mhz 125 mhz 6.25 gbps cmu0 pll 2.5 gbps cmu1 pll rx channel 1 logical tx pll select clock m ux 6.25 gbps rx cdr 6.25 gbps rx pma + rx pcs 6.25 gbps tx pma + tx pcs local divider clock m ux clock m ux rx pma + rx pcs 5?30 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation 1 the logical reference index of cmu0 pll within a transceiver block is always the complement of the logical reference index of cmu1 pll within the same transceiver block. 1 this logical reference index value is stored as logical tx pll , along with the other transceiver channel settings in the .mif . clocking/interface options the following describes the clocking/interface options. the core clocking setup describes the transceiver core clocks that are the write and read clocks of the transmit phase compensation fifo and the receive phase compensation fifo, respectively. core clocking is classified as transmitter core clocking and receiver core clocking. transmitter core clocking refers to the clock that is used to write the parallel data from the fpga fabric into the transmit phase compensation fifo. you can use one of the following clocks to write into the transmit phase compensation fifo: tx_coreclk ?you can use a clock of the same frequency as tx_clkout from the fpga fabric to provide the write clock to the transmit phase compensation fifo. if you use tx_coreclk , it overrides the tx_clkout options in the altgx megawizard plug-in manager. tx_clkout ?the quartus ii software automatically routes tx_clkout to the fpga fabric and back into the transmit phase compensation fifo. 1 the clocking/interface screen is not available for pma-only channels. option 1: share a single transmitter core clock between transmitters enable this option if you want tx_clkout of the first channel (channel 0) of the transceiver block to provide the write clock to the transmitter phase compensation fifos of the remaining channels in the transceiver block. this option is typically enabled when all the channels of a transceiver block are of the same functional mode and data rate and are reconfigured to the identical functional mode and data rate. consider the following scenario: four regular transceiver channels configured at 3 gbps and in the same functional mode. channel and cmu pll reconfiguration mode is enabled in the altgx_reconfig megawizard plug-in manager. you want to reconfigure all four regular transceiver channels to 1.5 gbps and vice versa. option 1 is applicable in this scenario because it saves clock resources. chapter 5: stratix iv dynamic reconfiguration 5?31 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 figure 5?17 shows the sharing of channel 0?s tx_clkout between all four regular channels of a transceiver block. option 2: use the respective channel transmitter core clocks enable this option if you want the individual transmitter channel tx_clkout signals to provide the write clock to their respective transmit phase compensation fifos. this option is typically enabled when each transceiver channel is reconfigured to a different functional mode using channel reconfiguration. consider the following scenario: four regular transceiver channels configured at 3 gbps and different functional modes. channel and cmu pll reconfiguration mode is enabled in the altgx_reconfig megawizard plug-in manager. you want to reconfigure each of the four regular transceiver channels to different data rates and different functional modes. option 2 is applicable in this scenario because the design requires all four regular transceiver channels to be reconfigured to different data rates and functional modes. each channel can be reconfigured to a different functional mode using the channel and cmu pll reconfiguration mode. figure 5?17. option 1 for transmitter core clocking (channel and cmu pll reconfiguration mode) tx0 (3 gbps/1.5 gbps) tx1 (3 gbps/1.5 gbps) tx2 (3 gbps/1.5 gbps) tx3 (3 gbps/1.5 gbps) rx3 rx2 rx1 rx0 cmu1 pll cmu0 pll fpga fa b ric transcei v er block tx_clko ut[0] lo w -speed parallel clock generated b y the tx0 local di v ider (tx_clkout[0]) high-speed serial clock generated b y the cmu0 pll 5?32 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation figure 5?18 shows how each transmitter channel?s tx_clkout signal provides a clock to the transmit phase compensation fifos of the respective transceiver channels. receiver core clocking refers to the clock that is used to read the parallel data from the receiver phase compensation fifo into the fpga fabric. you can use one of the following clocks to read from the receive phase compensation fifo: rx_coreclk ?you can use a clock of the same frequency as rx_clkout from the fpga fabric to provide the read clock to the receive phase compensation fifo. if you use rx_coreclk , it overrides the rx_clkout options in the altgx megawizard plug-in manager. rx_clkout ?the quartus ii software automatically routes rx_clkout to the fpga fabric and back into the receive phase compensation fifo. 1 the clocking/interface screen is not available for pma-only channels. figure 5?18. option 2 for transmitter core clocking (channel and cmu pll reconfiguration mode) tx0 (3 gbps/1.5 gbps) tx1 (3 gbps/6 gbps) tx2 (3 gbps/1.5 gbps) tx3 (3 gbps) rx0 rx1 rx2 rx3 cmu1 pll cmu0 pll fpga fa b ric transcie v er block high-speed serial clock generated b y the cmu0 pll tx_clko ut[0] tx_clko ut[1] tx_clko ut[2] tx_clko ut[3] lo w -speed parallel clock generated b y the local div ider of the transceiv er chapter 5: stratix iv dynamic reconfiguration 5?33 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 option 1: share a single transmitter core clock between receivers enable this option if you want tx_clkout of the first channel (channel 0) of the transceiver block to provide the read clock to the receive phase compensation fifos of the remaining receiver channels in the transceiver block. this option is typically enabled when all the channels of a transceiver block are in a basic or protocol configuration with rate matching enabled and are reconfigured to another basic or protocol configuration with rate matching enabled. consider the following scenario: four regular transceiver channels configured to basic 2 gbps functional mode with rate matching enabled. channel and cmu pll reconfiguration mode is enabled in the altgx_reconfig megawizard plug-in manager. you want to reconfigure all four regular transceiver channels to 3.125 gbps configuration with rate matching enabled. option 1 is applicable in this scenario. figure 5?19 shows the sharing of channel 0?s tx_clkout between all four channels of a transceiver block. figure 5?19. option 1 for receiver core clocking (channel and cmu pll reconfiguration mode) high-speed serial clock generated b y the cmu0 pll low -speed parallel clock generated b y the tx0 local di vider (tx_clkout[0]) high-speed serial clock generated b y the cmu1 pll fpga fa bric transcei v er block tx_clko ut[0] tx0 (2 gbps) rx0 tx1 (2 gbps) tx2 (2 gbps) tx3 (2 gbps) rx1 rx2 rx3 cmu1 pll cmu0 pll fo ur regu lar transceiv er channels configured at basic 2g with rate matching and set up to s witch to 3.125 g bps with rate matching 5?34 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation option 2: use the respective channel transmitter core clocks enable this option if you want the individual transmitter channel?s tx_clkout signal to provide the read clock to its respective receive phase compensation fifo. this option is typically enabled when all the transceiver channels have rate matching enabled with different data rates and are reconfigured to another basic or protocol functional mode with rate matching enabled. consider the following scenario: tx0/rx0: you want to dynamically reconfigure basic 1 gbps configuration with rate matching enabled to basic 2 gbps configuration with rate matching enabled. tx1/rx1: you want to dynamically reconfigure basic 4 gbps configuration with rate matching enabled to basic 1 gbps configuration with rate matching enabled. tx2/rx2 and tx3/rx3: you want to dynamically reconfigure basic 3.125 gbps configuration with rate matching enabled to 1 gbps configuration with rate matching and vice versa. channel and cmu pll reconfiguration mode is enabled in the altgx_reconfig megawizard plug-in manager. option 2 is applicable because the design requires the individual transceiver channels to be reconfigured with different data rates to another basic or protocol functional mode with rate matching. therefore, each channel can be reconfigured to another basic or protocol functional mode with rate matching enabled and a different data rate. chapter 5: stratix iv dynamic reconfiguration 5?35 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 figure 5?20 shows the respective tx_clkout of each channel clocking the respective channels of a transceiver block. option 3: use the respective channel receiver core clocks enable this option if you want the individual channel?s rx_clkout signal to provide the read clock to its respective receive phase compensation fifo. this option is typically enabled when the channel is reconfigured from a basic or protocol configuration with or without rate matching to another basic or protocol configuration with or without rate matching. consider the following scenario: tx1/rx1: gige configuration to sonet/sdh oc48 configuration. tx2/rx2: basic 2.5 gbps configuration with rate matching disabled to basic 1.244 gbps configuration with rate matching disabled. channel and cmu pll reconfiguration mode is enabled in the altgx_reconfig megawizard plug-in manager option 3 is applicable in this scenario. figure 5?20. option 2 for receiver core clocking (channel and cmu pll reconfiguration mode) high-speed serial clock generated b y the cmu0 pll high-speed serial clock generated b y the cmu1 pll fpga fa bric transcei v er block tx_clko ut[0] tx_clko ut[1] tx_clko ut[2] rx0 rx1 rx2 rx3 tx0 (2 gbps/1 gbps) tx1 (4 gbps/1 gbps) tx2 (3.125 gbps/1 gbps) tx3 (2 gbps) cmu1 pll cmu0 pll lo w -speed parallel clock generated b y the local div ider of the transceiv er 5?36 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation figure 5?21 shows the respective rx_clkout of each channel clocking the respective receiver channels of a transceiver block. fpga fabric-transceiver channel interface selection this section describes the altgx megawizard plug-in manager settings related to the fpga fabric-transceiver channel interface data width when you select and activate channel and cmu pll reconfiguration mode. you need to set up the fpga fabric-transceiver channel interface data width when functional mode reconfiguration involves: changes in the fpga fabric-transceiver channel data width or enabling and disabling the static pcs blocks of the transceiver channel you can set up the fpga fabric-transceiver channel interface data width by enabling the channel interface option in the modes screen. enable the channel interface option if the reconfiguration if the reconfigured channel has: changed fpga fabric-transceiver channel interface data width or changed input control signals and output status signals figure 5?21. option 3 for receiver core clocking (channel and cmu pll reconfiguration mode) high-speed serial clock generated b y the cmu0 pll high-speed serial clock generated b y the cmu1 pll fpga fa bric transcei v er block rx_clko ut[0] rx_clko ut[1] rx1 rx0 tx0 (2 gbps) tx1 (2 gbps) cmu1 pll cmu0 pll low-speed parallel clock generated by the local divider of the transceiver chapter 5: stratix iv dynamic reconfiguration 5?37 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 there are two signals available when you enable the channel interface option: tx_datainfull ?the width of this input signal depends on the number of channels you set up in the general screen. it is 44 bits wide per channel. this signal is available only for transmitter only and receiver and transmitter configurations. this port replaces the existing tx_datain port. rx_dataoutfull ?the width of this output signal depends on the number of channels you set up in the general screen. it is 64 bits wide per channel. this signal is available only for receiver only and receiver and transmitter configurations. this port replaces the existing rx_dataout port. 1 in addition to these two ports, you can select the necessary control and status signals for the reconfigured channel in the clocking/interface screen. f for more information about control and status signals, refer to the ?transceiver port lists? section in the stratix iv gx transceiver architecture chapter. these control and status signals are not applicable in basic (pma direct) functional mode. table 5?8 lists the signals not available when you enable the channel interface option. the quartus ii software has legal checks for the connectivity of tx_datainfull and rx_dataoutfull and the various control and status signals you enable in the clocking/interface screen. for example, the quartus ii software allows you to select and connect the pipestatus and powerdn signals. it assumes that you are planning to switch to and from pci express (pipe) functional mode. table 5?9 describes the tx_datainfull[43:0] fpga fabric-transceiver channel interface signals. tab le 5 ?8 . control and status signals not applicable in basic (pma direct) mode with the channel interface option enabled fpga fabric-receiver interface fpga fabric-transmitter interface rx_dataout tx_datain rx_syncstatus tx_ctrlenable rx_patterndetect tx_forcedisp rx_a1a2sizeout tx_dispval rx_ctrldetect rx_errdetect rx_disperr 5?38 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation tab le 5 ?9 . tx_datainfull[43:0] fpga fabric-transceiver channel interface signal descriptions (part 1 of 2) (note 1) fpga fabric-transceiver channel interface description transmit signal description (based on stratix iv gx supported fpga fabric-transceiver channel interface widths) 8-bit fpga fabric-transceiver channel interface tx_datainfull[7:0] : 8-bit data ( tx_datain ) the following signals are used only in 8b/10b modes: tx_datainfull[8] : control bit ( tx_ctrlenable ) tx_datainfull[9] transmitter force disparity compliance (pci express [pipe]) ( tx_forcedisp ) in all modes except pci express (pipe). for pci express (pipe) mode, ( tx_forcedispcompliance ) is used. tx_datainfull[10] : forced disparity value ( tx_dispval ) 10-bit fpga fabric-transceiver channel interface tx_datainfull[9:0] : 10-bit data ( tx_datain ) 16-bit fpga fabric-transceiver channel interface with pcs-pma set to 16/20 bits two 8-bit data ( tx_datain ) tx_datainfull[7:0] - tx_datain (lsbyte) and tx_datainfull[18:11] - tx_datain (msbyte) the following signals are used only in 8b/10b modes: tx_datainfull[8] - tx_ctrlenable (lsb) and tx_datainfull[19] - tx_ctrlenable (msb) force disparity enable tx_datainfull[9] - tx_forcedisp (lsb) and tx_datainfull[20] - tx_forcedisp (msb) force disparity value tx_datainfull[10] - tx_dispval (lsb) and tx_datainfull[21] - tx_dispval (msb) 16-bit fpga fabric-transceiver channel interface with pcs-pma set to 8/10 bits two 8-bit data ( tx_datain ) tx_datainfull[7:0] - tx_datain (lsbyte) and tx_datainfull[29:22] - tx_datain (msbyte) the following signals are used only in 8b/10b modes: two c on tro l bit s ( tx_ctrlenable ) tx_datainfull [8] - tx_ctrlenable (lsb) and tx_datainfull [30] - tx_ctrlenable (msb) force disparity enable for non-pipe: tx_datainfull[9] - tx_forcedisp (lsb) and tx_datainfull[31] - t x _forcedisp (msb) for pci express (pipe): tx_datainfull[9] - tx_forcedispcompliance (lsb) and tx_datainfull[31] - tx_forcedispcompliance (msb) force disparity value tx_datainfull[10] - tx_dispval (lsb) and tx_datainfull[32] - tx_dispval (msb) chapter 5: stratix iv dynamic reconfiguration 5?39 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 20-bit fpga fabric-transceiver channel interface with pcs-pma set to 20 bits two 1 0-b it data ( tx_datain ) tx_datainfull[9:0] - tx_datain (lsbyte) and tx_datainfull[20:11] - tx_datain (msbyte) 20-bit fpga fabric-transceiver channel interface with pcs-pma set to 10 bits two 1 0-b it data ( tx_datain ) tx_datainfull[9:0] - tx_datain (lsbyte) and tx_datainfull[31:22] - tx_datain (msbyte) 32-bit fpga fabric-transceiver channel interface with pcs-pma set to 16/20 bits four 8-bit data ( tx_datain ) tx_datainfull[7:0] - tx_datain (lsbyte) and tx_datainfull[18:11] tx_datainfull[29:22] tx_datainfull[40:33] - tx_datain (msbyte) the following signals are used only in 8b/10b modes: four control bits ( tx_ctrlenable ) tx_datainfull[8] - tx_ctrlenable (lsb) and tx_datainfull[19] tx_datainfull[30] tx_datainfull[41] - tx_ctrlenable (msb) force disparity enable ( tx_forcedisp ) tx_datainfull [9]- tx_forcedisp (lsb) and tx_datainfull[20] tx_datainfull[31] tx_datainfull[42] - tx_forcedisp (msb) force disparity value ( tx_dispval ) tx_datainfull[10] - tx_dispval (lsb) and tx_datainfull[21] tx_datainfull[32] tx_datainfull[43] - tx_dispval (msb) 40-bit fpga fabric-transceiver channel interface with pcs-pma set to 20 bits four 10-bit data ( tx_datain ) tx_datainfull[9:0] - tx_datain (lsbyte) and tx_datainfull[20:11] tx_datainfull[31:22] tx_datainfull[42:33] - tx_datain (msbyte) note to tab l e 5 ?9 : (1) for all transceiver-related ports, refer to the ?transceiver port lists? section in the stratix iv transceiver architecture chapter. tab le 5 ?9 . tx_datainfull[43:0] fpga fabric-transceiver channel interface signal descriptions (part 2 of 2) (note 1) fpga fabric-transceiver channel interface description transmit signal description (based on stratix iv gx supported fpga fabric-transceiver channel interface widths) 5?40 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation table 5?10 describes the tx_dataoutfull[63:0] fpga fabric-transceiver channel interface signals. table 5?10. rx_dataoutfull[63:0] fpga fabric-transceiver channel interface signal descriptions (part 1 of 7) fpga fabric-transceiver channel interface description receive signal description (based on stratix iv gx supported fpga fabric-transceiver channel interface widths) 8-bit fpga fabric-transceiver channel interface the following signals are used in 8-bit 8b/10b modes: rx_dataoutfull[7:0] : 8-bit decoded data ( rx_dataout ) rx_dataoutfull[8] : control bit ( rx_ctrldetect ) rx_dataoutfull[9] : code violation status signal ( rx_errdetect ) rx_dataoutfull [10]: rx_syncstatus rx_dataoutfull[11] : disparity error status signal ( rx_disperr ) rx_dataoutfull[12] : pattern detect status signal ( rx_patterndetect ) rx_dataoutfull[13] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pci express (pipe)/pcie modes. rx_dataoutfull[14] : rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pci express (pipe)/pcie modes. rx_dataoutfull[14:13] : pci express (pipe)/pcie mode ( rx_pipestatus ) rx_dataoutfull[15] : 8b/10b running disparity indicator ( rx_runningdisp ) the following signals are used in 8-bit sonet/sdh mode: rx_dataoutfull[7:0] : 8-bit un-encoded data ( rx_dataout ) rx_dataoutfull[8] : rx_a1a2sizeout rx_dataoutfull[10] : rx_syncstatus rx_dataoutfull[11] : reserved rx_dataoutfull[12] : rx_patterndetect 10-bit fpga fabric-transceiver channel interface rx_dataoutfull[9:0] : 10-bit un-encoded data ( rx_dataout ) rx_dataoutfull[10] : rx_syncstatus rx_dataoutfull[11] : 8b/10b disparity error indicator ( rx_disperr ) rx_dataoutfull[12] : rx_patterndetect rx_dataoutfull[13] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pci express (pipe)/pcie modes rx_dataoutfull[14] : rate match fifo insertion status indicator (rx_rmfifodatainserted) in non-pci express (pipe)/pcie modes rx_dataoutfull[15] : 8b/10b running disparity indicator ( rx_runningdisp ) chapter 5: stratix iv dynamic reconfiguration 5?41 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 16-bit fpga fabric-transceiver channel interface with pcs-pma set to 16/20 bits two 8-bit unencoded data ( rx_dataout ) rx_dataoutfull[7:0] - rx_dataout (lsbyte) and rx_dataoutfull[23:16] - rx_dataout (msbyte) the following signals are used in 16-bit 8b/10b modes: two control bits rx_dataoutfull[8] - rx_ctrldetect (lsb) and rx_dataoutfull[24] - rx_ctrldetect (msb) two receiver error detect bits rx_dataoutfull[9] - rx_errdetect (lsb) and rx_dataoutfull[25] - rx_errdetect (msb) two receiver sync status bits rx_dataoutfull [10] - rx_syncstatus (lsb) and rx_dataoutfull[26] - rx_syncstatus (msb) two receiver disparity error bits rx_dataoutfull [11] - rx_disperr (lsb) and rx_dataoutfull[27] - rx_disperr (msb) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[28] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull [45]: rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pci express (pipe)/pcie modes rx_dataoutfull[14] and rx_dataoutfull [46]: rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pci express (pipe)/pcie modes two 2-bit pci express (pipe) status bits rx_dataoutfull[14:13] - rx_pipestatus (lsb) and rx_dataoutfull[30:29] - rx_pipestatus (msb) rx_dataoutfull[15] and rx_dataoutfull[47] : 8b/10b running disparity indicator ( rx_runningdisp ) table 5?10. rx_dataoutfull[63:0] fpga fabric-transceiver channel interface signal descriptions (part 2 of 7) fpga fabric-transceiver channel interface description receive signal description (based on stratix iv gx supported fpga fabric-transceiver channel interface widths) 5?42 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation 16-bit fpga fabric-transceiver channel interface with pcs-pma set to 8/10 bits two 8-bit data rx_dataoutfull[7:0] - rx_dataout (lsbyte) and rx_dataoutfull[39:32] - rx_dataout (msbyte) the following signals are used in 16-bit 8b/10b mode: two control bits rx_dataoutfull[8] - rx_ctrldetect (lsb) and rx_dataoutfull[40] - rx_ctrldetect (msb) two receiver error detect bits rx_dataoutfull[9] - rx_errdetect (lsb) and rx_dataoutfull[41] - rx_errdetect (msb) two receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[42] - rx_syncstatus (msb) two receiver disparity error bits rx_dataoutfull[11] - rx_disperr (lsb) and rx_dataoutfull[43] - rx_disperr (msb) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[44] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull[45] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pci express (pipe)/pcie modes rx_dataoutfull[14] and rx_dataoutfull[46] : rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pci express (pipe)/pcie modes two 2-bit pci express (pipe) status bits rx_dataoutfull[14:13] - rx_pipestatus (lsb) and rx_dataoutfull[46:45] - rx_pipestatus (msb) rx_dataoutfull [15] and rx_dataoutfull[47] : 8b/10b running disparity indicator ( rx_runningdisp ) table 5?10. rx_dataoutfull[63:0] fpga fabric-transceiver channel interface signal descriptions (part 3 of 7) fpga fabric-transceiver channel interface description receive signal description (based on stratix iv gx supported fpga fabric-transceiver channel interface widths) chapter 5: stratix iv dynamic reconfiguration 5?43 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 16-bit fpga fabric-transceiver channel interface with pcs-pma set to 8/10 bits (continued) the following signals are used in 16-bit sonet/sdh mode: two 8-bit data rx_dataoutfull[7:0] - rx_dataout (lsbyte) and rx_dataoutfull[39:32] - rx_dataout (msbyte) two receiver alignment pattern length bits rx_dataoutfull[8] - rx_a1a2sizeout (lsb) and rx_dataoutfull[40] - rx_a1a2sizeout (msb) two receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[42] - rx_syncstatus (msb) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[44] - rx_patterndetect (msb) 20-bit fpga fabric-transceiver channel interface with pcs-pma set to 20 bits two 10-bit data ( rx_dataout ) rx_dataoutfull[9:0] - rx_dataout (lsbyte) and rx_dataoutfull[25:16] - rx_dataout (msbyte) wo receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[26] - rx_syncstatus (msb) rx_dataoutfull[11] and rx_dataoutfull [27]: 8b/10b disparity error indicator ( rx_disperr ) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[28] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull[29] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pci express (pipe)/pcie modes rx_dataoutfull[14] and rx_dataoutfull[30] : rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pci express (pipe)/pcie modes rx_dataoutfull[15] and rx_dataoutfull[31] : 8b/10b running disparity indicator ( rx_runningdisp ) table 5?10. rx_dataoutfull[63:0] fpga fabric-transceiver channel interface signal descriptions (part 4 of 7) fpga fabric-transceiver channel interface description receive signal description (based on stratix iv gx supported fpga fabric-transceiver channel interface widths) 5?44 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation 20-bit fpga fabric-transceiver channel interface with pcs-pma set to 10 bits two 10-bit data rx_dataoutfull[9:0] - rx_dataout (lsbyte) and rx_dataoutfull[41:32] - rx_dataout (msbyte) two receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[42] - rx_syncstatus (msb) rx_dataoutfull[11] and rx_dataoutfull[43] : 8b/10b disparity error indicator ( rx_disperr ) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[44] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull[45] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pci express (pipe)/pcie modes rx_dataoutfull[14] and rx_dataoutfull[46] : rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pci express (pipe)/pcie modes rx_dataoutfull[15] and rx_dataoutfull[47] : 8b/10b running disparity indicator ( rx_runningdisp ) table 5?10. rx_dataoutfull[63:0] fpga fabric-transceiver channel interface signal descriptions (part 5 of 7) fpga fabric-transceiver channel interface description receive signal description (based on stratix iv gx supported fpga fabric-transceiver channel interface widths) chapter 5: stratix iv dynamic reconfiguration 5?45 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 32-bit mode four 8-bit un-encoded data ( rx_dataout ) rx_dataoutfull[7:0] - rx_dataout (lsbyte) rx_dataoutfull[23:16] rx_dataoutfull[39:32] rx_dataoutfull[55:48] - rx_dataout (msbyte) the following signals are used in 32-bit 8b/10b mode: four control data bits ( rx_dataout ) rx_dataoutfull[8] - rx_ctrldetect (lsb) rx_dataoutfull[24] rx_dataoutfull[40] rx_dataoutfull[56] - rx_ctrldetect (msb) four receiver error detect bits rx_dataoutfull[9] - rx_errdetect (lsb) rx_dataoutfull[25] rx_dataoutfull[41] rx_dataoutfull[57] - rx_errdetect (msb) four receiver pattern detect bits rx_dataoutfull [10]- rx_syncstatus (lsb) and rx_dataoutfull[26] rx_dataoutfull[42] rx_dataoutfull[58] - rx_syncstatus (msb) four receiver disparity error bits rx_dataoutfull[11] - rx_disperr (lsb) rx_dataoutfull[27] rx_dataoutfull[43] rx_dataoutfull[59] - rx_disperr (msb) four receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) rx_dataoutfull[28] rx_dataoutfull[44] rx_dataoutfull[60] - rx_patterndetect (msb) rx_dataoutfull[13] , rx_dataoutfull[29] , rx_dataoutfull[45] and rx_dataoutfull[61] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pci express (pipe)/pcie modes rx_dataoutfull[14] , rx_dataoutfull[30] , rx_dataoutfull[46] , and rx_dataoutfull[62] : rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pci express (pipe)/pcie modes table 5?10. rx_dataoutfull[63:0] fpga fabric-transceiver channel interface signal descriptions (part 6 of 7) fpga fabric-transceiver channel interface description receive signal description (based on stratix iv gx supported fpga fabric-transceiver channel interface widths) 5?46 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation 32-bit mode (continued) rx_dataoutfull[15] , rx_dataoutfull[31] , rx_dataoutfull[47] , and rx_dataoutfull[63] : 8b/10b running disparity indicator ( rx_runningdisp ) the following signals are used in 32-bit sonet/sdh scrambled backplane mode: four control data bits ( rx_dataout ) rx_dataoutfull[7:0] - rx_dataout (lsbyte) rx_dataoutfull[23:16] rx_dataoutfull[39:32] rx_dataoutfull[55:48] - rx_dataout (msbyte) rx_dataoutfull[8] , rx_dataoutfull[24], rx_dataoutfull[40] , and rx_dataoutfull[56] : four rx_a1a2sizeout four receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) rx_dataoutfull[26] rx_dataoutfull[42] rx_dataoutfull[58] - rx_syncstatus (msb) four receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) rx_dataoutfull[28] rx_dataoutfull[44] rx_dataoutfull[60] - rx_patterndetect (msb) 40-bit mode four 10-bit control data bits ( rx_dataout ) rx_dataoutfull[9:0] - rx_dataout (lsbyte) r x_dataoutfull[25:16] rx_dataoutfull[41:32] rx_dataoutfull[57:48] - rx_dataout (msbyte) four receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) rx_dataoutfull[26] rx_dataoutfull[42] rx_dataoutfull[58] - rx_syncstatus (msb) four receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) rx_dataoutfull[28] rx_dataoutfull[44] rx_dataoutfull[60] - rx_patterndetect (msb) table 5?10. rx_dataoutfull[63:0] fpga fabric-transceiver channel interface signal descriptions (part 7 of 7) fpga fabric-transceiver channel interface description receive signal description (based on stratix iv gx supported fpga fabric-transceiver channel interface widths) chapter 5: stratix iv dynamic reconfiguration 5?47 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 altgx_reconfig megawizard plug-in manager setup for channel and cmu pll reconfiguration mode to setup channel and cmu pll reconfiguration mode in the altgx_reconfig megawizard plug-in manager, use the following steps: 1. in the reconfiguration settings screen, set the what is the number of channels controlled by the reconfig controller? option. for more information, refer to ?total number of channels option in the altgx_reconfig instance? on page 5?10 . 2. in the reconfiguration settings screen, select the channel and tx pll select/reconfig option. the following control signals are always available when you enable the channel and tx pll select/reconfig option: channel_reconfig_done reconfig_address_out[5:0] the following ports are optional and available for selection in the channel and tx pll reconfiguration screen: reset_reconfig_address reconfig_address_en logical_tx_pll_sel and logical_tx_pll_sel_en ?for more information about these two ports, refer to ?guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en ports? on page 5?59 . rx_tx_duplex_sel[1:0] channel and cmu pll reconfiguration operation in channel reconfiguration, only a write transaction can occur; no read transactions are allowed. in the example shown in figure 5?22 , the altgx_reconfig controls two channels. therefore, the logical_channel_address signal is 2 bits wide. also, the transceiver channel is configured in basic mode with the receiver and transmitter configuration. you can optionally choose to trigger write_all once by selecting the continuous write operation in the altgx_reconfig megawizard plug-in manager. the quartus ii software then continuously writes all the words required for reconfiguration. 5?48 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation figure 5?22 shows a .mif write transaction when using channel and cmu pll reconfiguration mode. for guidelines regarding re-using .mifs , specifying input reference clocks, or using logical_tx_pll_sel ports, refer to ?special guidelines? on page 5?57 . f for more information about reset, refer to the ?reset sequence when using dynamic reconfiguration with the channel and tx pll select/reconfig option? section in the reset control and power down chapter. channel reconfiguration with transmitter pll select mode details you can reconfigure the data rate of a transceiver channel by switching between a maximum of four transmitter plls. you can select between the following transmitter plls cmu plls present in a transceiver block cmu plls present in other transceiver blocks atx plls outside the transceiver block figure 5?22. .mif write transaction in channel and cmu pll reconfiguration mode notes to figure 5?22 : (1) the logical_channel_address port is set to 2?b01 to reconfigure the second transceiver channel. (2) the rx_tx_duplex_sel[1:0] port is set to 2?b00 to match the receiver and transmitter configuration of the specified transceiver channel. addr0 addr1 1st 16 bits don?t care addr0 addr54 don?t care 3?b101 2?b00 2?b01 reconfig_mode_sel[2:0] logical_channel_address[1:0] rx_tx_du plex_sel[1:0] reconfig_clk w rite_all bu sy reconfig_address_out[5:0] reconfig_address_en reconfig_data[15:0] channel_reconfig_done 2nd 16 bits 55th 16 bits chapter 5: stratix iv dynamic reconfiguration 5?49 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 you can use the channel reconfiguration with transmitter pll select mode along with the cmu pll reconfiguration mode, only if it is a cmu pll and not an atx pll. you can first reconfigure the second cmu pll to the desired data rate using cmu pll reconfiguration mode. then use channel reconfiguration with transmitter pll select mode to reconfigure the transceiver channel to listen to the second cmu pll. for more information about supported configurations, refer to ?transceiver channel reconfiguration mode details? on page 5?19 and ?memory initialization file (.mif)? on page 5?19 . 1 channel reconfiguration with transmitter pll select mode is not applicable to regular transceiver channels in bonded mode configurations (4 and 8). for guidelines regarding re-using .mifs , specifying input reference clocks, or using logical_tx_pll_sel ports, refer to ?special guidelines? on page 5?57 . f for more information about reset, refer to the ?reset sequence when using dynamic reconfiguration with the channel and tx pll select/reconfig option? section in the reset control and power down chapter. blocks reconfigured in the channel reconfigur ation with transmitter pll select mode the blocks reconfigured in this mode have two types of multiplexers. when you switch between the cmu plls within the same transceiver block, the multiplexer that is reconfigured is within the transceiver block. it is located in the transmitter channel path. 5?50 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation figure 5?23 shows the multiplexers that you can dynamically reconfigure using channel reconfiguration with transmitter pll select mode. figure 5?23. channel reconfiguration with transmitter pll select in a transceiver block note to figure 5?23 : (1) depending on the mode you select, pcs may or may not be present. fu ll d u plex transcei v er channel tx channel rx channel cmu channels refclk0 refclk1 cmu0 pll cmu1 pll logical tx pll select clock m ux local divider rx cdr tx pma + tx pcs clock m ux clock m ux clock m ux rx pma + rx pcs (1) chapter 5: stratix iv dynamic reconfiguration 5?51 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 figure 5?24 shows the multiplexers that are reconfigured when you switch to an additional pll that is outside the transceiver block. figure 5?24. multiplexers that are reconfigured when you switch to an additional pll transcei v er block gxbr0 transcei v er block gxbr1 transcei v er block gxbr2 xn_top x1 cmu0 gxbr0 x1 cmu1 gxbr0 x4_gxbr0 x1 cmu0 gxbr1 x1 cmu1 gxbr1 x4_gxbr1 x1 cmu0 gxbr2 x1 cmu1 gxbr2 x4_gxbr2 xn_bottom atx r1 pll block atx r0 pll block channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel 5?52 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation altgx megawizard plug-in manager setup for channel reconfiguration with transmitter pll select mode follow steps 1, 2, 4, 7, 8, and 9 described in ?altgx megawizard plug-in manager setup for channel and cmu pll reconfiguration mode? on page 5?26 . in addition to these steps, you must also set up the following: multi-pll settings the use additional cmu/atx transmitter plls from outside the transceiver block option allows you select a maximum of four transmitter plls. specify the number of additional plls required for the altgx instance in the modes screen. based on this number, the quartus ii software opens up the corresponding pll screens (for example, pll 1 and pll 2 ). the pll set up in the general screen is always the main pll and the settings are available in the main pll screen. similarly, the pll settings for the additional plls are available in the corresponding pll1 screen, pll 2 screen, and so on. additional plls also include the cmu plls within the same transceiver block. for example, you can select the atx pll as the main pll, and three additional plls as follows: pll 1? cmu0 pll of the same transceiver block pll 2? cmu1 pll of the same transceiver block pll 3? cmu0 pll/ cmu1 pll of another transceiver block. the quartus ii software differentiates between the cmu plls of the same transceiver block and the transmitter plls outside the transceiver block based on the use central clock divider to drive the transmitter channels using 4/n lines option. if this option is enabled, the transmitter pll is outside the transceiver block. similarly, if this option is disabled, the transmitter pll is one of the cmu plls within the same transceiver block. logical channel addressing when using additional plls the logical channel addressing of the transceiver channel is the same as described in ?logical channel addressing? on page 5?5 so long as you are only using the cmu plls within the same transceiver block. in the case of additional plls (when transmitter plls are outside the transceiver block), the additional plls also have their own logical channel address. this affects the starting channel number of the following altgx instances connected to the dynamic reconfiguration controller, if any. therefore, you must take into account the logical channel address of transmitter plls outside the transceiver block when setting the total number of channels controlled by the reconfig controller option in the altgx_reconfig instance. when you select the use central clock divider to drive the transmitter channels using 4/n lines option for an additional pll, you can see its logical channel address value at the bottom of the corresponding pll screen. chapter 5: stratix iv dynamic reconfiguration 5?53 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 selecting the pll logical reference index for additional plls the pll logical reference index of additional plls outside the transceiver block can only be 2 or 3. when you enable the use central clock divider to drive the transmitter channels using 4/n lines option for an additional pll, you can only select between 2 or 3 as the pll logical reference index. disable the use central clock divider to drive the transmitter channels using 4/n lines option for an additional pll, the additional pll is one of the cmu plls within the same transceiver block. therefore, the pll logical reference index is either 0 or 1. for more information about the pll logical reference index of cmu plls within the same transceiver block, refer to ?selecting the logical reference index of the cmu pll? on page 5?29 . altgx_reconfig megawizard plug-in manager setup for channel reconfiguration with transmitter pll select mode for more information, refer to the ?altgx_reconfig megawizard plug-in manager setup for channel and cmu pll reconfiguration mode? on page 5?47 . channel reconfiguration with transmitter pll select operation read transactions are not allowed in this mode. figure 5?25 shows a .mif write transaction when dynamically reconfiguring a transceiver channel. the .mif write transaction in channel reconfiguration with transmitter pll select mode remains the same except the reconfig_mode_sel[2:0] value and the difference in the number of .mif words used. in this example, the transceiver channel is configured in receiver and transmitter configuration. therefore, the .mif size is 8. you can optionally choose to trigger write_all once by selecting the continuous write operation in the altgx_reconfig megawizard plug-in manager. the quartus ii software then continuously writes all the words required for reconfiguration. 5?54 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation for guidelines regarding re-using .mifs , specifying input reference clocks, or using logical_tx_pll_sel ports, refer to ?special guidelines? on page 5?57 . f for more information about reset, refer to the ?reset sequence when using dynamic reconfiguration with the channel and tx pll select/reconfig option? section in the reset control and power down chapter. cmu pll reconfiguration mode details use this mode to reconfigure only the cmu pll without affecting the remaining blocks of the transceiver channel. when you reconfigure the cmu pll of a transceiver block to run at a different data rate, all the transceiver channels listening to this cmu pll also are reconfigured to the new data rate. 1 you cannot dynamically reconfigure a cmu pll into a cmu channel and vice versa. for more information about the supported configurations in cmu pll reconfiguration mode, refer to table 5?5 on page 5?19 . transmitter pll powerdown during cmu pll reconfiguration mode, the dynamic reconfiguration controller automatically powers down the selected cmu pll until it completes reconfiguration. the altgx_reconfig instance does not provide external ports to control the cmu pll power down. when you reconfigure the cmu pll, the pll_locked signal goes low. therefore, after reconfiguring the transceiver, wait for the pll_locked signal from the altgx instance before continuing normal operation. the dynamic reconfiguration controller powers down only the selected cmu pll. the other cmu pll is not affected. figure 5?25. .mif write transaction in channel and cmu pll reconfiguration mode addr0 addr1 1st 16 bits don?t care addr0 addr54 don?t care 3?b101 2?b00 2?b01 reconfig_mode_sel[2:0] logical_channel_address[1:0] rx_tx_du plex_sel[1:0] reconfig_clk w rite_all bu sy reconfig_address_out[5:0] reconfig_address_en reconfig_data[15:0] channel_reconfig_done 2nd 16 bits 55th 16 bits chapter 5: stratix iv dynamic reconfiguration 5?55 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 blocks reconfigured in cmu pll reconfiguration mode each transceiver block has two cmu plls? cmu0 pll and cmu1 pll.you can reconfigure each of these cmu plls to a different data rate in this mode. figure 5?26 shows a view of the reconfigurable blocks using cmu pll reconfiguration mode. altgx megawizard plug-in manager setup for cmu pll reconfiguration mode when you want to reconfigure the cmu pll to another data rate, enable .mif generation and set up the altgx megawizard plug-in manager, as described in the following steps. the dynamic reconfiguration controller reconfigures the cmu pll with the new information stored in the .mif . 1. select the channel and transmitter pll reconfiguration option in the modes screen. 2. provide the new data rate you want the cmu pll to run at in the general screen. 1 the logical reference index of cmu0 pll within a transceiver block is always the complement of the logical reference index of cmu1 pll. figure 5?26. cmu plls in a transceiver block in cmu pll reconfiguration mode note to figure 5?26 : (1) depending on the mode you select, pcs may or may not be present. fu ll d u plex transcei v er channel rx cdr tx channel rx channel cmu channels refclk0 refclk1 cmu0 pll cmu1 pll local divider tx pma + tx pcs logical tx pll select clock m ux clock m ux clock m ux rx pma + rx pcs (1) 5?56 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation altgx_reconfig plug-in manager setup for cmu pll reconfiguration mode for more information, refer to ?altgx_reconfig megawizard plug-in manager setup for channel and cmu pll reconfiguration mode? on page 5?47 . cmu pll reconfiguration operation set the reconfig_mode_sel[2:0] signal to 3? b100 to activate this mode. figure 5?27 shows a .mif write transaction in cmu pll reconfiguration mode. the dynamic reconfiguration controller asserts the channel_reconfig_done signal to indicate that the cmu pll reconfiguration is complete. in this example, the transceiver channel is configured in receiver and transmitter configuration. therefore, the .mif size is 8. you can optionally choose to trigger write_all once by selecting the continuous write operation in the altgx_reconfig megawizard plug-in manager. the quartus ii software then continuously writes all the words required for reconfiguration. for guidelines regarding re-using .mifs , specifying input reference clocks, or using logical_tx_pll_sel ports, refer to ?special guidelines? on page 5?57 . f for more information about reset, refer to the ?reset sequence when using dynamic reconfiguration with the channel and tx pll select/reconfig option? section in the reset control and power down chapter. figure 5?27. cmu pll reconfiguration .mif write transaction addr0 addr1 don?t care addr0 addr7 8th 16 bits don?t care 3?b100 reconfig_mode_sel[2:0] reconfig_clk w rite_all bu sy reconfig_address_out[5:0] reconfig_address_en reconfig_data[15:0] channel_reconfig_done 2nd 16 bits 1st 16 bits chapter 5: stratix iv dynamic reconfiguration 5?57 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 central control unit reconfiguration mode details central control unit reconfiguration mode is a .mif -based mode used to reconfigure the central control unit (ccu) of the transceiver. use reconfig_mode_sel[] to activate this mode. central control unit reconfiguration mode is applicable for bonded pcs configurations such as basic 4/8, xaui, pci express (pipe) 4/8, refer to table 5?5 on page 5?19 for the allowed configurations. for instance, to dynamically reconfigure an altgx instance in basic 4 configuration to xaui configuration, you must first configure: 1. the transceiver channel and cmu pll to run at the xaui data rate and functional mode (use channel and cmu pll reconfiguration mode). 2. reconfigure the central control unit portion of the transceiver from basic to xaui functional mode (use central control unit reconfiguration mode). for more information about the central control unit reconfiguration mode, refer to ?example 2? on page 5?101 . 1 dynamic reconfiguration is not available if hard ip is used in pci express mode. 1 to switch between one bonded pcs configuration and another, always use: 1) channel and cmu pll reconfiguration mode followed by 2) central control unit reconfiguration mode use the same .mif for both the these steps. in step 1, a partial .mif is written and the remaining contents of the .mif is written in step 2. in step 1, reconfigure all the channels one-by-one. in step-2, reconfiguration of the central control unit is transceiver block based. reconfigure any one of the four channels in the transceiver block. special guidelines the following section describes the special guidelines required for the transceiver channel reconfiguration modes previously described. this section includes the following: ?guidelines for re-using .mifs? on page 5?57 ?guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en ports? on page 5?59 ?guidelines for specifying the input reference clocks? on page 5?61 guidelines for re-using .mifs to configure the transceiver plls and receiver cdrs for multiple data rates, it is important to understand the input reference clock requirements. this helps you to efficiently create the clocking scheme for reconfiguration and to reuse the .mifs across all channels in the device. this section describes the clocking enhancements and the implications of using input clocks from various clock sources. the available clock inputs appear as a pll_inclk_rx_cruclk[] port and can be provided from the inter-transceiver block lines (also known as itb lines), from the global clock networks that are driven by an input pin or by a pll cascade clock. 5?58 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation f for more information about input reference clocking, refer to the ?input reference clocking? section of the stratix iv transceiver clocking chapter. the following section describes the clocking requirements to re-use .mifs . the .mif contains information about the input clock multiplexer settings and the functional blocks that you selected during the altgx megawizard plug-in manager instantiation. you can use a .mif to dynamically reconfigure any of the other transceiver channels in the device as long as the order of the clock inputs is consistent. for example, assume that a .mif is generated for a transceiver channel in transceiver block 0 and the input clock source is connected to the pll_inclk_rx_cruclk[0] port. when you use the generated .mif for a channel in other transceiver blocks (for example, transceiver block 1), the same clock source must be connected to the pll_inclk_rx_cruclk[0] port. figure 5?28 and figure 5?29 show the incorrect and correct order of input reference clocks, respectively. in figure 5?28 , the clocking is incorrect when re-using the .mif because the input reference clock is not connected to the corresponding pll_inclk_rx_cruclk[] ports in the two instances. figure 5?28. incorrect input reference clock connections when reusing a .mif note to figure 5?28 : (1) the red lines represent the alternate source of refclk. altgx instance 1 stratix i v gx de v ice 156.25 mhz 125 mhz transcei v er block 0 transcei v er block 1 altgx instance 2 pll_inclk_rx_cr uclk[0] pll_inclk_rx_cr uclk[1] pll_inclk_rx_cr uclk[0] pll_inclk_rx_cr uclk[1] (1) (1) chapter 5: stratix iv dynamic reconfiguration 5?59 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 figure 5?29 shows the correct input reference clock connections when re-using a .mif . 1 yo u c a n re -u se th e .mif generated for a transceiver channel on one side of the device for a transceiver channel on the other side of device, only if the input reference clock frequencies and order of the pll_inclk_rx_cruclk[] ports in the altgx instances on both sides are identical. in addition to the input reference clock requirements when re-using a .mif , refer to ?guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en ports? on page 5?59 for additional ways to re-use a .mif guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en ports this section describes when to enable the logical_tx_pll_sel and logical_tx_pll_sel_en ports and how to use them in the following dynamic reconfiguration modes: channel and cmu pll reconfiguration mode channel reconfiguration with transmitter pll select mode cmu pll reconfiguration mode these are optional input ports to the altgx_reconfig instance. figure 5?29. correct input reference clock connections when reusing a .mif note to figure 5?29 : (1) the red lines represent the alternate source of refclk. stratix i v gx de v ice 156.25 mhz 125 mhz transcei v er block 0 transcei v er block 1 altgx instance 1 altgx instance 2 pll_inclk_rx_cr uclk[0] pll_inclk_rx_cr uclk[1] pll_inclk_rx_cr uclk[1] pll_inclk_rx_cr uclk[0] (1) (1) 5?60 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation table 5?11 shows the conditions under which the dynamic reconfiguration controller uses either the logical_tx_pll_sel port value or the logical reference index value stored in the .mif . figure 5?30 shows the logical_tx_pll_sel and logical_tx_pll_sel_en ports. table 5?11 lists how the dynamic reconfiguration controller selects between the logical reference index stored in the .mif (logical tx pll) and the logical reference index specified at the logical_tx_pll_sel port. when you configure a transceiver channel in the altgx megawizard plug-in manager, altera recommends that you keep track of the transmitter pll that drives the channel. 1 the logical_tx_pll_sel port does not modify transceiver settings on the receiver side. if both the logical_tx_pll_sel and logical_tx_pll_sel_en ports are enabled, reconfigure the transmitter pll. keep the logical_tx_pll_sel and logical_tx_pll_sel_en signals at a constant logic level until the dynamic reconfiguration controller asserts the channel_reconfig_done signal. figure 5?30. using logical_tx_pll_sel and logical_tx_pll_sel_en ports logical tx pll (logical reference index v alue stored in the .mif) logical_tx_pll_sel (logical reference index specified on the port) logical_tx_pll_sel_en altgx_reconfig instance selected logical reference index v alue 0 1 table 5?11. various combinations of the logical_tx_pll_sel and logical_tx_pll_sel_en ports logical_tx_pll_sel logical_tx_pll_sel_en logical reference index value selected by the altgx_reconfig instance enabled enabled and value is 1 value on the logical_tx_pll_sel port enabled enabled and value is 0 logical reference index value stored in the .mif (logical tx pll) enabled disabled value on the logical_tx_pll_sel port disabled disabled logical reference index value stored in the .mif (logical tx pll) chapter 5: stratix iv dynamic reconfiguration 5?61 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 table 5?12 lists the two conditions under which you can re-use .mifs when using the logical_tx_pll_sel and logical_tx_pll_sel_en ports. guidelines for specifying the input reference clocks the following are guidelines for setting up the input reference clocks in the reconfiguration settings screen of the altgx megawizard plug-in manager. assign the identification numbers to all input reference clocks that are used by the transmitter plls in their corresponding pll screens. you can set up a maximum of 10 input reference clocks and assign identification numbers from 1 to 10 (1, 2, 3, 4, 5, 6, 7, 8, 9, and 10). keep the identification numbers consistent for all the .mifs generated in the design. maintain the input reference clock frequencies settings for all the .mifs . table 5?12. two conditions under which you can re-use .mifs (logical_tx_pll_sel and logical_tx_pll_sel_en) condition 1: re-use the .mif created for one cmu pll on the other cmu pll of the same transceiver block. condition 2: re-use the .mif created for one transmitter pll on the transmitter pll of another transceiver block. channel and cmu pll reconfiguration and cmu pll reconfiguration channel reconfiguration with transmitter pll select channel and cmu pll reconfiguration and cmu pll reconfiguration channel reconfiguration with transmitter pll select consider that you create a .mif containing the desired altgx settings to reconfigure the cmu0 pll. assume that the logical reference index you assigned to cmu0 pll is 0 . you can re-use this . mif created for cmu0 pll on cmu1 pll of the same transceiver block if you want to reconfigure cmu1 pll to the new data rate information stored in the .mif . you must set logical_tx_pll_ sel to the logical reference index of cmu1 pll ( 1'b1 ) and l ogical_tx_pll_ sel_en to 1'b1 and then write this .mif into the transceiver channel. by doing so, the dynamic reconfiguration controller overwrites the logical tx pll value stored in the .mif with the logical reference index of cmu1 pll. assume that the transceiver channel listens to cmu1 pll and the logical reference index assigned to it is 0 . generate a .mif for these settings. when you use channel reconfiguration with transmitter pll select mode and reconfigure the transceiver channel with this .mif , the transceiver channel is reconfigured to listen to cmu1 pll. if you want to reconfigure the transceiver channel to listen to cmu0 pll instead, you can re-use this .mif . you must set logical_tx_pll_ sel to the logical reference index of cmu0 pll ( 1'b1 ) and logical_tx_pll_ sel_en to 1'b1 and then write this .mif into the transceiver channel. consider that you create a .mif containing the desired altgx settings to reconfigure the transmitter pll of a transceiver block. assume that the logical reference of the transmitter pll is 1 . you can re-use this .mif created to reconfigure the transmitter pll of another transceiver block under the following condition: ? you want to reconfigure the transmitter pll of the other transceiver block to exactly the same data rate information stored in the .mif . yo u must s et logical_channel_ address to the logical channel address of the transmitter pll you intend to reconfigure. consider that you create a .mif containing the logical reference index of the transmitter pll that the reconfigured transceiver channel needs to listen to. assume that the transmitter pll used is cmu0 pll and the logical reference index assigned is 0 . when you use channel reconfiguration with transmitter pll select mode and reconfigure the transceiver channel with this .mif , the transceiver channel is reconfigured to listen to cmu0 pll. if you want to reconfigure this transceiver channel to listen to another transmitter pll outside the transceiver block, you can reuse this .mif , provided the intended data rate is the same. 5?62 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation figure 5?31 shows an example scenario where the input reference clock connections to the transceiver channels are based on what you set as the input clock source for each of the cmu transmitter plls within a transceiver block. figure 5?31. input reference clocks connections to the transceiver channels note to figure 5?31 : (1) depending on the mode you select, pcs unit may or may not be present. full duplex transceiver channel 1 cmu0 pll rx cdr cmu1 pll tx channel 1 logical tx pll select rx channel 1 156 .25 mhz 125mhz refclk0 (identification number = 2) refclk1 (identification number = 1) 3.125 gbps 3.125 gbps 3.125 gbps local divider 3.125 gbps 1 gbps cmu channels clock mux full duplex transceiver channel 2 rx cdr tx channel 2 logical tx pll select rx channel 2 1 gbps 1 gbps 1 gbps local divider clock mux based on what you have set up as the input clock source for cmu1 pll, this clock mux selects the corresponding input clock source for cmu1 pll. based on what you have set up as the input clock source for cmu0 pll, this clock mux selects the corresponding input clock source for cmu0 pll. clock mux clock mux tx pma + tx pcs (1) tx pma + tx pcs (1) rx pma + rx pcs rx pma + rx pcs chapter 5: stratix iv dynamic reconfiguration 5?63 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 data rate division in transmitter mode details you can use date rate division in transmitter mode to modify the data rate of the transmitter channel in multiples of 1, 2, and 4. this dynamic reconfiguration mode is available only for the transmit side and not for the receive side. blocks reconfigured in the data rate division in transmitter mode the only block that is reconfigured by the data rate division in transmitter mode is the transmitter local divider block of a transmitter channel. you can set the transmitter local divider to a divide by value of /1, /2, or /4, as shown in figure 5?32 . you must be aware of the device operating range before you enable and use this feature. there are no legal checks that are imposed by the quartus ii software because it is an on-the-fly control feature. you also need to ensure that a specific functional mode supports the data rate range before dividing the clock when using this rate switch option. 1 the date rate division in transmitter mode is applicable only to channels configured in non-bonded mode clocked by the cmu0/cmu1 located within the same transceiver block. altgx megawizard plug-in manager setup for data rate division in transmitter mode enable the following settings in the altgx megawizard plug-in manager: 1. select the channel and transmitter pll reconfiguration option in the reconfig screen to enable the altgx_reconfig instance to modify the transmitter channel local divider values dynamically. 2. set the what is the starting channel number? option in the reconfig screen. for more information, refer to ?logical channel addressing? on page 5?5 . the alternate reference clock is not required because a single clock source is used. the /1, /2, or /4 data rates can be derived from the single input reference clock. figure 5?32. local divider of a transmitter channel high-speed clock from tx pll0 high-speed clock from tx pll1 /n /1, /2, or /4 /4, /5, /8, or /10 high-speed serial clock lo w -speed parallel cloc k 5?64 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation altgx_reconfig megawizard plug-in manager setup for data rate division in transmitter mode enable the following settings in the altgx_reconfig megawizard plug-in manager for data rate division in transmitter mode: 1. in the reconfiguration settings screen, set the what is the number of channels controlled by the reconfig controller? option. for more information, refer to ?total number of channels option in the altgx_reconfig instance? on page 5?10 . 2. specify the logical channel address of the transmitter channel at the logical_channel_address input port. 3. in the reconfiguration settings screen, select the data rate division in tx option. the rate_switch_ctrl[1:0] input port is available when you enable the data rate division in tx option. the value you set at the rate_switch_ctrl[1:0] signal determines the transmitter local divider settings, as explained in ?dynamic reconfiguration controller port list? on page 5?78 . to read the existing local divider settings of the transmitter channel, select the use 'rate_switch_out' port to read out the current data rate division option in the error checks/data rate switch screen. decoding for the rate_switch_out[1:0] output signal is the same as the rate_switch_ctrl[1:0] input signal. 1 dynamic rate switch has no effect on the dividers on the receive side of the transceiver channel. it can be used only for the transmitter. 1 data rate division in transmitter mode does not require a .mif . data rate division in transmitter operation the following sections describe the steps involved in write and read transactions for the data rate division in transmitter mode. chapter 5: stratix iv dynamic reconfiguration 5?65 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 for this example, the value set in the what is the number of channels controlled by the reconfig controller? option of the altgx_reconfig megawizard plug-in manager is 4. therefore, the logical_channel_address input is 2 bits wide. also, you must reconfigure the local divider settings of the transmitter channel whose logical channel address is 2'b01. figure 5?33 shows a write transaction in data rate division in transmitter mode. figure 5?33. write transaction in data rate division in transmitter mode note to figure 5?33 : (1) for this example, you want to reconfigure the local divider settings of the transmitter channel to ?divide by 4?. therefore, the value set at rate_switch_ctrl[1:0 ] is 2'b10. busy 2'bxx 2'b01 2'bxx 2'b10 2'bxx 2'bxx 3'b011 3'bxxx reconfig_mode_sel[2:0] reconfig_clk rate_s w itch_ctrl[1:0] (1) logical_channel_address w rite_all 5?66 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation for this example, the value set in the what is the number of channels controlled by the reconfig controller? option of the altgx_reconfig megawizard plug-in manager is 4. therefore, the logical_channel_address input is 2 bits wide. also, you must read the existing local divider settings of the transmitter channel whose logical channel address is 2'b01. figure 5?34 shows a read transaction waveform in data rate division in transmitter mode. 1 do not perform a read transaction in date rate division in transmitter mode if rate_switch_out[1:0] is not selected in the altgx_reconfig megawizard plug-in manager. f for more information about reset, refer to the ?reset sequence when using dynamic reconfiguration with the channel and tx pll select/reconfig option? section in the reset control and power down chapter. offset cancellation feature the stratix iv gx and gt devices provide an offset cancellation circuit per receiver channel to counter the offset variations due to process, voltage, and temperature (pvt). these variations create an offset in the analog circuit voltages, pushing them out of the expected range. in addition to reconfiguring the transceiver channel, the dynamic reconfiguration controller performs offset cancellation on all receiver channels connected to it on power up. figure 5?34. read transaction in data rate division in transmitter mode note to figure 5?34 : (1) for this example, the existing local divider settings of the transmitter channel are ?divide by 2?. therefore, the value read out at rate_switch_out[1:0] is 2'b01. read busy 2'bxx 2'b01 2'bxx invalid output 2'b01 2'bxx 3'b011 3'bxxx reconfig_mode_sel[2:0] reconfig_clk logical_channel_address (1) rate_s witch_out[1:0] data_v alid chapter 5: stratix iv dynamic reconfiguration 5?67 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 the offset cancellation for receiver channels option is automatically enabled in both the altgx and altgx_reconfig megawizard plug-in managers for receiver and transmitter and receiver only configurations. it is not available for transmitter only configurations. for receiver and transmitter and receiver only configurations, you must connect the necessary interface signals between the altgx_reconfig and altgx (with receiver channels) instances. offset cancellation is automatically executed once every time the device is powered on. the control logic for offset cancellation is integrated into the dynamic reconfiguration controller. you must connect the altgx_reconfig instance to the altgx instances (with receiver channels) in your design. you must connect the reconfig_fromgxb, reconfig_togxb , and necessary clock signals to both the altgx_reconfig and altgx (with receiver channels) instances. 1 the offset cancellation control functionality remains the same for both regular transceiver channels and pma-only channels. operation every altgx instance for receiver and transmitter or receiver only configurations require that the offset cancellation for receiver channels option is enabled in the reconfig screen of the altgx megawizard plug-in manager. this option is enabled by default for the above two configurations. it is disabled for the transmitter only configuration. because this option is enabled by default, the altgx instance must be connected to an altgx_reconfig instance (dynamic reconfiguration controller). the offset cancellation controls are also enabled by default in the reconfiguration settings screen of the altgx_reconfig instance. you must also set the starting channel number in the what is the starting channel number? option for every altgx instance connected to the altgx_reconfig instance. for more information, refer to: ?logical channel addressing of regular transceiver channels? on page 5?6 ?logical channel addressing of pma-only channels? on page 5?7 ?logical channel addressing?combination of regular transceiver channels and pma-only channels? on page 5?9 . when the device powers up, the dynamic reconfiguration controller initiates offset cancellation on the receiver channel by disconnecting the receiver input pins from the receiver data path. it also sets the receiver cdr into a fixed set of dividers to guarantee a voltage controlled oscillator (vco) clock rate within the range necessary to provide proper offset cancellation. subsequently, the offset cancellation process goes through different states and culminates in the offset cancellation of the receiver buffer and receiver cdr. after offset cancellation is complete, the user divider settings are restored. 5?68 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation the dynamic reconfiguration controller sends and receives data to the transceiver channel through the reconfig_togxb and reconfig_fromgxb signals. you must connect these signals between the altgx_reconfig instance and the altgx instance. you must also set the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen of the altgx_reconfig megawizard plug-in manager. for more information, refer to ?total number of channels option in the altgx_reconfig instance? on page 5?10 . the use 'logical_channel_address' port for analog controls reconfiguration option in the analog controls screen of the altgx_reconfig megawizard plug-in manager is not applicable for the receiver offset cancellation process. 1 if the design does not require pma controls reconfiguration and uses optimum le resources, you can connect all the altgx instances in the design to a single dynamic reconfiguration controller (altgx_reconfig instance). 1 the gxb_powerdown signal must not be asserted during the offset cancellation sequence. to understand the impact on system start-up when you control all the transceiver channels using a single dynamic reconfiguration controller, refer to ?pma controls reconfiguration duration? on page 5?92 . altgx_reconfig inst ance signals transition during offset cancellation consider that the design has altgx instances with channels of both transmitter only and receiver only configurations. you must include the transmitter only channels while setting the what is the starting channel number? option in the altgx instance and setting the what is the number of channels controlled by the reconfig controller? option in the altgx_reconfig instance for receiver offset cancellation. after the device powers up, the busy signal remains low for the first reconfig_clk clock cycle. the busy signal then gets asserted for the second reconfig_clk clock cycle, when the dynamic reconfiguration controller initiates the offset cancellation process. the de-assertion of the busy signal indicates the successful completion of the offset cancellation process. chapter 5: stratix iv dynamic reconfiguration 5?69 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 figure 5?35 shows the dynamic reconfiguration signals transition during offset cancellation on receiver channels. 1 due to the offset cancellation process, the transceiver reset sequence has changed. for more information, refer to the reset control and power down chapter. eyeq eyeq hardware is available in stratix iv transceivers to analyze and debug the receiver data recovery path (receiver gain, clock jitter, and noise level). you can use it to monitor the eye width and assess the quality of the incoming signal. normally, the receiver cdr samples the incoming signal at the center of the eye. when you enable the eyeq hardware, it allows the cdr to sample across 32 different positions across one unit interval (ui) of the incoming data. you can manually control the sampling points and check the bit-error rate (ber) at each of these 32 sampling points. these sampling points are also known as phase steps. the ber increases at the edge of the eye-opening. by observing the number of sampling points results in a desired ber value, you can determine the eye width. 1 the eyeq hardware is available for both regular transceiver channels and cmu channels. f for more information about the supported data rates, phase step translation, and other specifications, refer to the dc and switching characterization chapter. enabling the eyeq control logic and the eyeq hardware you must enable the eyeq hardware in the altgx megawizard plug-in manager and the eyeq control block in the altgx_reconig megawizard plug-in manager. eyeq hardware is available for each transceiver channel in the receiver data path. select the analog controls option in the reconfiguration settings screen of the altgx megawizard plug-in manager to enable the eyeq hardware. eyeq control logic is available in the dynamic reconfiguration controller. select the eyeq control option in the altgx_reconfig megawizard plug-in manager to enable the eyeq control logic. figure 5?35. dynamic reconfiguration signals transition during offset cancellation on receiver channels note to figure 5?35 : (1) after device power up, the busy signal remains low for the first reconfig_clk cycle. reconfig_clk busy (1) 5?70 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation f eyeq uses an avalon memory mapped interface. for more information about this interface, refer to the avalon interface specification . connections between the altgx and altgx_re config inst ances to enable the eyeq options, use the following steps: 1. enable the eyeq options in the altgx and altgx_reconfig megawizard plug-in managers, as explained in ?enabling the eyeq control logic and the eyeq hardware? on page 5?69 . 2. connect the reconfig_{to/from}gxb ports between the altgx and altgx_reconfig instances. eyeq control logic in the dynamic reconfiguration controller allows you to write to the registers in the eyeq hardware. therefore, you must have a state machine in the user design that communicates to the eyeq control block of the altgx_reconfig instance. you can then access the internal registers of the eyeq hardware indirectly through the eyeq control logic. 1 altera recommends having an input pattern generator and checker to monitor the ber of the received data. figure 5?36 shows the connections between the eyeq hardware in the altgx instances and the eyeq control logic in the dynamic reconfiguration controller. figure 5?36. connecting altgx and altgx_reconfig instances with eyeq enabled busy error ctrl_ w ritedata[15:0] ctrl_address[15:0] ctrl_ w rite ctrl_read reconfig_fromgxb[17:0] reconfig_togxb[3:0] rx_datain[0] altgx instance eyeq hard w are receiv er channel 0 altgx_reconfig instance eyeq control block ctrl_ w aitrequest ctrl_readdata[15:0] reconfig_mode_sel[3:0] chapter 5: stratix iv dynamic reconfiguration 5?71 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 controlling the eyeq hardware the eyeq hardware is controlled by writing to the eyeq registers using eyeq interface registers in the altgx_reconfig instance. table 5?13 shows the register memory of the 16-bit eyeq registers. table 5?14 shows the eyeq phase step encoding for the 32 phase steps spanning one unit interval (ui). table 5?13. eyeq register mapping address description 00 bit[0]?0/1: disable/enable eyeq feature bit [15:1]?15'b000000000000000 01 bits [5:0]?eyeq phase step value. refer to table 5?14 for the eyeq phase step encoding. bits [15:6]?10'b0000000000 table 5?14. eyeq phase step encoding (part 1 of 2) desired phase step setting eyeq phase step encoding 0 6'b111111 1 6'b111110 2 6'b111101 3 6'b111100 4 6'b111011 5 6'b111010 6 6'b111001 7 6'b111000 8 6'b110111 9 6'b110110 10 6'b110101 11 6'b110100 12 6'b110011 13 6'b110010 14 6'b110001 15 6'b110000 16 6'b010000 17 6'b010001 18 6'b010010 19 6'b010011 20 6'b010100 21 6'b010101 22 6'b010110 23 6'b010111 5?72 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation table 5?15 shows the register memory of the 16-bit eyeq interface registers. 24 6'b011000 25 6'b011001 26 6'b011010 27 6'b011011 28 6'b011100 29 6'b011101 30 6'b011110 31 6'b011111 table 5?15. eyeq interface register mapping address description 00 control/status register (eyeq csr) bit [0]?start: writing a 1 to this bit instructs the altgx_reconfig instance to program the eyeq hardware. writing to this bit automatically clears any error bits. bit [1]?read/write: writing a 0 to this bit writes the contents of the data register to one of the eyeq registers depending on the address stored in the eyeq register address register. writing a 1 reads the contents of the eyeq register. bit [12:2]?11'b00000000000 bit [13] ?channel address error: this bit is set to 1 if the programmed channel address is invalid. writing a 1 to this bit clears the error. bit [14]?eyeq register address error: this bit is set to 1 if the programmed word address is invalid. writing a 1 to this bit clears the error. bit [15]?busy status: the value of this bit can be polled to determine if the altgx_reconfig read/write request has completed. when this active-high bit is asserted, all registers become read only until this bit is de-asserted. 01 channel address [15:0]?specifies the transceiver channel for the desired eyeq operation. this must match the logical_channel_address input port. 02 eyeq register address [15:0]?specifies the address eyeq register to be read from or written to. the values supported are 00 or 01. 03 data [15:0]? for a write operation, the data in this register is written to the eyeq register selected. for a read operation, this register contains the contents of the eyeq register selected. the data in this register is only valid when the busy status is low. a read operation overwrites the current contents of this register. table 5?14. eyeq phase step encoding (part 2 of 2) desired phase step setting eyeq phase step encoding chapter 5: stratix iv dynamic reconfiguration 5?73 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 to control the eyeq hardware, follow these steps: 1. read the eyeq interface register 00 (the control and status register) to check the busy status. the clear status bit indicates an idle status. 2. issue a write to the eyeq interface register 01 (the channel address register) to select the desired channel. 3. issue a write to the eyeq interface register 02 (the eye monitor register address) to select the desired eyeq register. 4. issue a write to the eyeq interface register 03 (the data register) to provide the data to be written to the target eyeq register. 5. issue a write to eyeq interface register 00 (the control and status register) to specify read/~write and to issue the start command. 6. poll the eyeq interface register 00 (the control and status register) and wait for the busy status to be de-asserted. once the status is no longer busy, the data is considered successfully written for write transactions. for read transactions, this indicates that the contents of the data register has been updated and can be read out. note that all writes that occur when the busy status is asserted are ignored; all registers become read only. 7. if the next operation is to the same eyeq register and same channel, you do not need to repeat steps 2 and 3. example of using the eyeq feature consider a design with one regular transceiver channel configured in basic functional mode. the channel has a data rate of 2.5 gbps with the eyeq feature enabled in both the altgx and altgx_reconfig instances. figure 5?37 shows how the eyeq mode is first enabled by writing into the eyeq registers using the eyeq interface registers. a phase step value of 25 is written to the eyeq register. before performing any operation, the following conditions must be met: the busy bit is 0 in the eyeq csr the ctrl_waitrequest is low 5?74 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation adaptive equalization (aeq) high-speed interface systems require different equalization settings to compensate for changing data rates and backplane losses. manual tuning of the receiver channel?s equalization stages involves finding the optimal settings through trial and error, and then locking in those values at compile time. this manual method is cumbersome under varying system characteristics. the aeq feature solves this problem by automatically tuning an active receiver channel?s equalization filters based on a frequency content comparison between the incoming signal and internally generated reference signals. user logic can dynamically control the aeq hardware in the receiver through the dynamic reconfiguration controller. this section describes how to enable different options and use them to control the aeq hardware. adaptive equalization limitations the following are the aeq feature requirements and limitations: the receive data must be 8b/10b encoded not available in pci-express (pipe) functional mode (because the aeq hardware cannot perform the equalization process when the receive link is under the electrical idle condition) the receiver input signal must have a minimum envelope of 400 mv (differential peak-to-peak). the quartus ii software does not check for this requirement aeq hardware is not present in the cmu channels f for more information about speed grade, data rates, receiver input signal level, and other specifications that support the aeq feature, refer to the dc and switching characterization chapter. figure 5?37. enabling eyeq mode 0 x 0 ? ? ? ? 4 0 1 25 1 0 1 2 3 0 2 3 0 reconfig_mode_sel[3:0] reconfig_clk ctrl_address[15:0] ctrl_read ctrl_ w rite ctrl_ w aitrequest ctrl_readdata[15:0] ctrl_ w ritedata[15:0] bu sy enab le eyeq set eyeq phase step v alue to 25 4?b1011 chapter 5: stratix iv dynamic reconfiguration 5?75 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 enabling the aeq control logic and aeq hardware to use the aeq feature, enable the aeq hardware in the altgx megawizard plug-in manager and the aeq control block in the altgx_reconig megawizard plug-in manager. to enable the aeq hardware and the aeq control logic: select the enable adaptive equalizer control option in the reconfiguration settings screen of the altgx megawizard plug-in manager. the aeq hardware is available for each transceiver channel in the receiver data path. select the enable adaptive equalizer control option in the altgx_reconfig megawizard plug-in manager. the aeq control logic is available in the dynamic reconfiguration controller. when you select the above two options, the altgx and altgx_reconfig megawizard plug-in managers provide the following additional ports: aeq_fromgxb[] aeq_togxb[] the aeq_fromgxb[] and aeq_togxb[] ports provide the interface between the receiver channel and the dynamic reconfiguration controller. the following section describes the connections between the aeq control block of the altgx_reconfig instance and the aeq hardware of the altgx instance. connections between the altgx and altgx_re config inst ances enable the adaptive equalization options in the altgx and altgx_reconfig megawizard plug-in managers, as explained in the previous section. to use the aeq control block and aeq hardware, you must connect the altgx receivers to the altgx_reconfig instance using the reconfig_{to/from}gxb and aeq_{to/from}gxb ports. you must also connect the altgx_reconfig instance to your design. if you have multiple transceiver instances and a single altgx_reconfig instance, connect the lsb of the aeq_togxb[] and aeq_fromgxb[] ports of the altgx_reconfig instance to the transceiver channel with a logical_channel_address value of 0. 5?76 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration modes implementation stratix iv device handbook volume 2 ? march 2010 altera corporation figure 5?38 shows the aeq_fromgxb[] and aeq_togxb[] connections between multiple altgx instances and the dynamic reconfiguration controller. figure 5?38. connecting the altgx and altgx_reconfig instances with aeq enabled recei v er channel 0 aeq hard ware busy error user logic altgx instance 1 aeq_togxb[23:0] aeq_fromgxb[7:0] logical_channel_address = 0 rx_datain[0] altgx instance 2 recei v er channel 1 logical_channel_address = 4 aeq hard ware rx_datain[1] altgx_reconfig aeq control block aeq_fromgxb[15:8] aeq_togxb[47:24] reconfig_mode_sel[3:0] altgx instance 3 recei v er channel 2 to 4 logical_channel_address = 8 aeq hard ware aeq_fromgxb[23:16] aeq_togxb[63:48] rx_datain[2] chapter 5: stratix iv dynamic reconfiguration 5?77 dynamic reconfiguration modes implementation ? march 2010 altera corporation stratix iv device handbook volume 2 you have three options to control the aeq hardware using the altgx_reconfig instance. the following section explains the three user modes. controlling the aeq hardware use reconfig_mode_sel[3:0] to select one of the following three modes. continuous mode for a single channel all functionalities of the aeq hardware are active and the equalization stages are continually being feedback-optimized ( figure 5?39 ). one time mode for a single channel the aeq hardware attempts to find a stable equalization and then locks to that value. once locked, the equalization values are held and are no longer updated. the timing diagram for this mode is similar to mode 1 shown in figure 5?39 with the exception that the reconfig_mode_sel[3:0] value used is 1001. powerdown for a single channel the aeq hardware of the specified receiver channel is put in standby mode. the aeq hardware comes out of the standby mode as soon as you change the value at reconfig_mode_sel[3:0] to one of the other two aeq control modes. the aeq hardware of the powered down receiver channel does not remember the converged equalization value once it comes out of the standby mode. it instead starts at the maximum equalization value after powering up again ( figure 5?40 ). figure 5?39. timing diagram for enabling aeq in continuous mode for a single channel (modes 1 and 2) note to figure 5?39 : (1) 1000 for mode 1 and 1001 for mode 2. w rite_all reconfig_mode_sel[3:0] logical_channel_address[] bu sy 4 (logical channel 4) 1000 (1) alt2gxb_reconfig indicates the completion of the w rite transation 5?78 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration controller port list stratix iv device handbook volume 2 ? march 2010 altera corporation dynamic reconfiguration controller port list table 5?16 lists the input control ports and output status ports of the dynamic reconfiguration controller. figure 5?40. timing diagram for powering down the aeq for a single channel (mode 3) w rite_all reconfig_mode_sel[3:0] logical_channel_address[] bu sy 4 (logical channel 4) 1000 0000 read rx_eq ctrl_out[19..16] xxxx v alid translated man ual equalization settings pma read operation alt2gxb_reconfig indicates that the aeq hardw are for logical channel address 4 is po w ered do wn table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 1 of 13) (note 3) , (4) port name input/ output description clock inputs to altgx_reconfig instance reconfig_clk input the frequency range of this clock depends on the following transceiver channel configuration modes: receiver only (37.5 mhz to 50 mhz) receiver and transmitter (37.5 mhz to 50 mhz) transmitter only (2.5 mhz to 50 mhz) by default, the quartus ii software assigns a global clock resource to this port. this clock must be a free-running clock sourced from an i/o clock pin. do not use dedicated transceiver refclk pins or any clocks generated by transceivers. chapter 5: stratix iv dynamic reconfiguration 5?79 dynamic reconfiguration controller port list ? march 2010 altera corporation stratix iv device handbook volume 2 altgx and altgx_reconfig interface signals reconfig_fromgxb input an output port in the altgx instance and an input port in the altgx_reconfig instance. this signal is transceiver-block based. therefore, the width of this signal increases in steps of 17 bits per transceiver block. in the altgx megawizard plug-in manager, the width of this signal depends on the following: whether the channels configured in the altgx instance are regular transceiver channels or pma-only channels. the number of channels you select in the what is the number of channels? option in the general screen. for example, if the channels in the altgx instance are regular transceiver channels and if you select the number of channels as follows: 1 channels 4, then the output port reconfig_fromgxb = 17 bits 5 channels 8, then the output port reconfig_fromgxb = 34 bits 9 channels 12, then the output port reconfig_fromgxb = 51 bits however, if the channels in the altgx instance are pma-only channels and if you select the number of channels as follows: number of pma-only channels = n, then the output port reconfig_fromgxb = n*17 bits for example, reconfig_fromgxb = 6 * 17 bits for 6 pma-only channels. in the altgx_reconfig megawizard plug-in manager, the width of this signal depends on the value you select in the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. for example, if you select the total number of channels controlled by altgx_reconfig instance as follows: 1 channels 4, then the input port reconfig_fromgxb = 17 bits 5 channels 8, then the input port reconfig_fromgxb = 34 bits 9 channels 12, then the input port reconfig_fromgxb = 51 bits table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 2 of 13) (note 3) , (4) port name input/ output description 5?80 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration controller port list stratix iv device handbook volume 2 ? march 2010 altera corporation reconfig_fromgxb (continued) input to connect the reconfig_fromgxb port between the altgx_reconfig instance and multiple altgx instances, follow these rules: connect the reconfig_fromgxb[16:0] of altgx instance 1 to the reconfig_fromgxb[16:0] of the altgx_reconfig instance. connect the reconfig_fromgxb[] port of the next altgx instance to the next available bits of the altgx_reconfig instance, and so on. connect the reconfig_fromgxb port of the altgx instance, which has the highest what is the starting channel number? option, to the msb of the reconfig_fromgxb port of the altgx_reconfig instance. the quartus ii fitter produces an error if the dynamic reconfiguration option is enabled in the altgx instance but the reconfig_fromgxb and reconfig_togxb ports are not connected to the altgx_reconfig instance. for more information, refer to ?connecting the altgx and altgx_reconfig instances? on page 5?11 . reconfig_togxb[3:0] output an input port of the altgx instance and an output port of the altgx_reconfig instance. you must connect the reconfig_togxb[3:0] input port of every altgx instance controlled by the dynamic reconfiguration controller to the reconfig_togxb[3:0] output port of the altgx_reconfig instance. the width of this port is always fixed to 3 bits. for more information, refer to ?connecting the altgx and altgx_reconfig instances? on page 5?11 . fpga fabric and altgx_reconfig interface signals write_all input assert this signal for one reconfig_clk clock cycle to initiate a write transaction from the altgx_reconfig instance to the altgx instance. you can use this signal in two ways for . mif -based modes: continuous write operation?select the enable continuous write of all the words needed for reconfiguration option to pulse the write_all signal only once for writing a whole .mif . the what is the read latency of the mif contents option is available for selection in this case only. enter the desired latency in terms of the reconfig_clk cycles. regular write operation?when the enable continuous write of all the words needed for reconfiguration option is disabled, every word of the .mif requires its own write cycle. table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 3 of 13) (note 3) , (4) port name input/ output description chapter 5: stratix iv dynamic reconfiguration 5?81 dynamic reconfiguration controller port list ? march 2010 altera corporation stratix iv device handbook volume 2 busy output this signal is used to indicate the busy status of the dynamic reconfiguration controller during offset cancellation. after the device powers up, this signal remains low for the first reconfig_clk clock cycle. it then is asserted and remains high when the dynamic reconfiguration controller performs offset cancellation on all the receiver channels connected to the altgx_reconfig instance. de-assertion of the busy signal indicates the successful completion of the offset cancellation process. for more information, refer to ?operation? on page 5?67 . pma controls reconfiguration mode?this signal is high when the dynamic reconfiguration controller performs a read or write transaction. all other dynamic reconfiguration modes?this signal is high when the dynamic reconfiguration controller writes the .mif into the transceiver channel. read input assert this signal for one reconfig_clk clock cycle to initiate a read transaction. the read port is applicable only to the pma controls reconfiguration mode and data rate division in transmitter mode. the read port is available when you select analog controls in the reconfiguration settings screen and select at least one of the pma control ports in the analog controls screen. for more information, refer to ?dynamically reconfiguring pma controls? on page 5?13 . data_valid output applicable only to pma controls reconfiguration mode. this port indicates the validity of the data read from the transceiver by the dynamic reconfiguration controller. the current data on the output read ports is the valid data only if data_valid is high. this signal is enabled when you enable at least one pma control port used in read transactions, for example tx_vodctrl_out . error output this indicates that an unsupported operation is attempted. you can select this in the error checks/data rate switch screen. the dynamic reconfiguration controller de-asserts the busy signal and asserts the error signal for two reconfig_clk cycles when you attempt an unsupported operation. for more information, refer to the ?error indication during dynamic reconfiguration? on page 5?91 . table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 4 of 13) (note 3) , (4) port name input/ output description 5?82 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration controller port list stratix iv device handbook volume 2 ? march 2010 altera corporation logical_channel_address [8:0] input enabled by the altgx_reconfig megawizard plug-in manager when you enable the use 'logical_channel_address' port for analog controls reconfiguration option in the analog controls screen. the width of the logical_channel_address port depends on the value you set in the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. this port can be enabled only when the number of channels controlled by the dynamic reconfiguration controller is more than one. for more information, refer to ?logical channel addressing of regular transceiver channels? on page 5?6 and ?logical channel addressing of pma-only channels? on page 5?7 . rx_tx_duplex_sel[1:0] input this is a 2-bit wide signal. you can select this in the error checks/data rate switch screen. the advantage of using this optional port is that it allows you to reconfigure only the transmitter portion of a channel, even if the channel configuration is duplex. for a setting of: rx_tx_duplex_sel[1:0] = 2'b00?the transmitter and receiver portion of the channel is reconfigured. rx_tx_duplex_sel[1:0] = 2'b01?the receiver portion of the channel is reconfigured. rx_tx_duplex_sel[1:0] = 2'b10?the transmitter portion of the channel is reconfigured. table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 5 of 13) (note 3) , (4) port name input/ output description chapter 5: stratix iv dynamic reconfiguration 5?83 dynamic reconfiguration controller port list ? march 2010 altera corporation stratix iv device handbook volume 2 analog settings control/status signals tx_vodctrl[2:0] (1) input this is an optional transmit buffer v od control signal. it is 3 bits per transmitter channel. the number of settings varies based on the transmit buffer supply setting and the termination resistor setting on the tx analog screen of the altgx megawizard plug-in manager. the width of this signal is fixed to 3 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 3 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 5?13 . the following shows the v od values corresponding to the tx_vodctrl settings for 100- termination. for more information, refer to the ?programmable output differential voltage? section of the stratix iv transceiver architecture chapter. tx_vodctrl[2:0] v od (mv) for 1.4 v v cc h 3?b000 200 3?b001 400 3?b010 600 3?b011 700 3?b100 800 3?b101 900 3?b110 1000 3?b111 1200 table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 6 of 13) (note 3) , (4) port name input/ output description 5?84 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration controller port list stratix iv device handbook volume 2 ? march 2010 altera corporation tx_preemp_0t[4:0] (1) input this is an optional pre-emphasis control for pre-tap for the transmit buffer. depending on what value you set at this input, the controller dynamically writes the value to the pre-emphasis control register of the transmit buffer. this signal controls both pre-emphasis positive and its inversion. the width of this signal is fixed to 5 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 5 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 5?13 . the following values are the legal settings allowed for this signal: 0 represents 0 1-15 represents -15 to -1 16 represents 0 17 - 31 represents 1 to 15 in pci express (pipe) configuration, set tx_preemp_0t[4:0] to 5'b00000 when you do a rate switch from gen 1 to gen 2 mode. this is to ensure that tx_preemp_0t[4:0] does not add to the signal boost, when tx_pipemargin and tx_pipedeemph take affect in pci express (pipe) gen 2 mode. for more information, refer to the ?programmable pre-emphasis? section of the stratix iv transceiver architecture chapter. tx_preemp_1t[4:0] (1) input this is an optional pre-emphasis write control for the first post-tap for the transmit buffer. depending on what value you set at this input, the controller dynamically writes the value to the first post-tap control register of the transmit buffer. the width of this signal is fixed to 5 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 5 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 5?13 and the ?programmable pre-emphasis? section of the stratix iv transceiver architecture chapter. table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 7 of 13) (note 3) , (4) port name input/ output description chapter 5: stratix iv dynamic reconfiguration 5?85 dynamic reconfiguration controller port list ? march 2010 altera corporation stratix iv device handbook volume 2 tx_preemp_2t[4:0] (1) input this is an optional pre-emphasis write control for the second post-tap for the transmit buffer. this signal controls both pre-emphasis positive and its inversion. depending on what value you set at this input, the controller dynamically writes the value to the pre-emphasis control register of the transmit buffer. the width of this signal is fixed to 5 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 5 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 5?13 . the following values are the legal settings allowed for this signal: 0 represents 0 1-15 represents -15 to -1 16 represents 0 17-31 represents 1 to 15 in pci express (pipe) configuration, set tx_preemp_2t[4:0] to 5'b00000 when you do a rate switch from gen 1 to gen 2 mode. this is to ensure that tx_preemp_2t[4:0] does not add to the signal boost when tx_pipemargin and tx_pipedeemph take affect in pci express (pipe) gen 2 mode. for more information, refer to the ?programmable pre-emphasis? section of the stratix iv transceiver architecture chapter. rx_eqctrl[3:0] (1) input this is an optional write control to write an equalization control value for the receive side of the pma. the width of this signal is fixed to 4 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 4 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 5?13 and the ?programmable equalization and dc gain? section of the stratix iv transceiver architecture chapter. table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 8 of 13) (note 3) , (4) port name input/ output description 5?86 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration controller port list stratix iv device handbook volume 2 ? march 2010 altera corporation rx_eqdcgain[2:0] (1) , (2) input this is an optional equalizer dc gain write control. the width of this signal is fixed to 3 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 3 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 5?13 . the following values are the legal settings allowed for this signal: 3?b000 => 0 db 3?b001 => 3 db 3?b010 => 6 db 3?b011 => 9 db 3?b100 => 12 db all other values => n/a for more information, refer to the ?programmable equalization and dc gain? section of the stratix iv transceiver architecture chapter. tx_vodctrl_out[2:0] output this is an optional transmit v od read control signal. this signal reads out the value written into the v od control register. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. tx_preemp_0t_out[4:0] output this is an optional pre-tap, pre-emphasis read control signal. this signal reads out the value written by its input control signal. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. tx_preemp_1t_out[4:0] output this is an optional first post-tap, pre-emphasis read control signal. this signal reads out the value written by its input control signal. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. tx_preemp_2t_out[4:0] output this is an optional second post-tap pre-emphasis read control signal. this signal reads out the value written by its input control signal. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. rx_eqctrl_out[3:0] output this is an optional read control signal to read the setting of equalization setting of the altgx instance. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. rx_eqdcgain_out[2:0] output this is an optional equalizer dc gain read control signal. this signal reads out the settings of the altgx instance dc gain. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 9 of 13) (note 3) , (4) port name input/ output description chapter 5: stratix iv dynamic reconfiguration 5?87 dynamic reconfiguration controller port list ? march 2010 altera corporation stratix iv device handbook volume 2 transceiver channel reconfiguration control/status signals reconfig_mode_sel[3:0] input set the following values at this signal to activate the appropriate dynamic reconfiguration mode: 3?b000 = pma controls reconfiguration mode. this is the default value. 3?b011 = data rate division in transmitter mode 3?b100 = cmu pll reconfiguration mode 3?b101 = channel and cmu pll reconfiguration mode 3?b110 = channel reconfiguration with transmitter pll select mode 3?b111 = central control unit reconfiguration mode the reconfig_mode_sel signal is 4 bits wide when you enable adaptive equalization control or eyeq control: 4'b1000 = aeq control (continuous mode for a single channel) 4'b1001 = aeq control (one time mode for a single channel) 4'b1010 = aeq control (power down for a single channel) 4/b1011 = eyeq control reconfig_mode_sel[] is available as an input only when you enable more than one dynamic reconfiguration mode. reconfig_address_out[5:0] output this signal is always available for you to select in the channel and tx pll reconfiguration screen. this signal is applicable only in the dynamic reconfiguration modes grouped under channel and tx pll select/reconfig option. this signal represents the current address used by the altgx_reconfig instance when writing the .mif into the transceiver channel. this signal increments by 1, from 0 to the last address, then starts at 0 again. you can use this signal to indicate the end of all the .mif write transactions ( reconfig_address_out[5:0] changes from the last address to 0 at the end of all the .mif write transactions). reconfig_address_en output this is an optional signal you can select in the channel and tx pll reconfiguration screen. this signal is applicable only in dynamic reconfiguration modes grouped under the channel and tx pll select/reconfig option. the dynamic reconfiguration controller asserts reconfig_address_en to indicate that reconfig_address_out[5:0] has changed. this signal is asserted only after the dynamic reconfiguration controller completes writing one 16-bit word of the .mif . reset_reconfig_address input this is an optional signal you can select in the channel and tx pll reconfiguration screen. this signal is applicable only in dynamic reconfiguration modes grouped under the channel and tx pll select/reconfig option. enable this signal and assert it for one reconfig_clk clock cycle if you want to reset the reconfiguration address used by the altgx_reconfig instance during reconfiguration. table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 10 of 13) (note 3) , (4) port name input/ output description 5?88 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration controller port list stratix iv device handbook volume 2 ? march 2010 altera corporation reconfig_data[15:0] input this signal is applicable only in the dynamic reconfiguration modes grouped under the channel and tx pll select/reconfig option. this is a 16-bit word carrying the reconfiguration information. it is stored in a .mif that you must generate. the altgx_reconfig instance requires that you provide reconfig_data [15:0] on every .mif write transaction using the write_all signal. reconfig_address[5:0] input this port is available for selection only in the .mif -based transceiver channel reconfiguration modes. for more information, refer to ?reduced .mif reconfiguration? on page 5?23 . rate_switch_ctrl[1:0] input this signal is available when you select data rate division in transmitter mode. based on the value you set here, the divide-by setting of the local divider in the transmitter channel gets modified. the legal values for this port are: 2?b00 = divide by 1 2?b01 = divide by 2 2?b10 = divide by 4 2?b11 = not supported rate_switch_out[1:0] input this signal is available when you select data rate division in transmitter mode. you can read the existing local divider settings of a transmitter channel at this port. the decoding for this signal is listed below: 2?b00 = division of 1 2?b01 = division of 2 2?b10 = division of 4 2?b11= not supported logical_tx_pll_sel input at this port you specify the identity of the transmitter pll you want to reconfigure. you can also specify the identity of the transmitter pll that you want the transceiver channel to listen to. when you enable this signal, the value set at this signal overwrites the logical_tx_pll value contained in the .mif . the value at this port must be held at a constant logic level until reconfiguration is done. logical_tx_pll_sel_en input if you want to use the logical_tx_pll_sel port only under some conditions and use the logical_tx_pll value contained in the .mif otherwise, enable this optional logical_tx_pll_sel_en port. only when logical_tx_pll_sel_en is enabled and set to 1 does the dynamic reconfiguration controller use logical_tx_pll_sel to identify the transmitter pll. the value at this port must be held at a constant logic level until reconfiguration is done. channel_reconfig_done output this signal goes high to indicate that the dynamic reconfiguration controller has finished writing all the words of the .mif . the channel_reconfig_done signal is automatically de-asserted at the start of a new dynamic reconfiguration write sequence. this signal is applicable only in channel and cmu pll reconfiguration and channel reconfiguration with transmitter pll select modes. table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 11 of 13) (note 3) , (4) port name input/ output description chapter 5: stratix iv dynamic reconfiguration 5?89 dynamic reconfiguration controller port list ? march 2010 altera corporation stratix iv device handbook volume 2 aeq_fromgxb[7:0] input the width of this signal depends on the number of channels controlled by the altgx_reconfig instance. for example, if you select the total number of channels controlled by the altgx_reconfig instance as follows: 1 channels 4, then the input port reconfig_fromgxb = 8bits 5 channels 8, then the input port reconfig_fromgxb = 16 bits 9 channels 12, then the input port reconfig_fromgxb = 24 bits this signal is available only when you enable the aeq control option. you must connect this signal between the altgx_reconfig and altgx instances when using aeq control. aeq_togxb output the width of this signal depends on the number of channels controlled by the altgx_reconfig instance. for example, if you select the total number of channels controlled by altgx_reconfig instance as follows: 1 channels 4, then the input port reconfig_fromgxb = 24 bits 5 channels 8, then the input port reconfig_fromgxb = 48 bits 9 channels 12, then the input port reconfig_fromgxb = 64 bits this signal is available only when you enable the aeq control option. you must connect this signal between the altgx_reconfig and altgx instances when using aeq control. ctrl_address[15:0] input used for eyeq control. this port is used to specify the address of the eyeq interface register for read and write operations. ctrl_writedata[15:0] input used for eyeq control. data present on this port is written to the eyeq interface register selected using the ctrl_address port. ctrl_readdata[15:0] output used for eyeq control. contents of the eyeq interface register selected using the ctrl_address port are available on this port after a read operation. ctrl_write input used for eyeq control. assert this signal high to write the data present on the ctrl_writedata port to the eyeq interface registers. ctrl_read input used for eyeq control. assert this signal high to read the contents of the eyeq interface registers to the ctrl_readdata port. table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 12 of 13) (note 3) , (4) port name input/ output description 5?90 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration controller port list stratix iv device handbook volume 2 ? march 2010 altera corporation ctrl_waitrequest output used for eyeq control. if asserted, this port indicates that the eyeq controller is busy with a read or write operation. you must wait until this signal goes low before you perform the next operation. ensure that the values on the ctrl_read , ctrl_write , ctrl_readdata , and ctrl_writedata ports are constant when ctrl_waitrequest is asserted. notes to ta bl e 5? 16 : (1) not all combinations of the input bits are legal values. (2) in pci express (pipe) mode, this input must be tied to 001 to be pci e-compliant. (3) for the various dynamic reconfiguration controller input and output ports and the software settings, refer to the stratix iv altgx_reconfig megafunction user guide chapter. (4) for the various transceiver input and output ports and the software settings, refer to the altgx transceiver setup guide chapter. table 5?16. dynamic reconfiguration controller port list (altgx_reconfig instance) (part 13 of 13) (note 3) , (4) port name input/ output description chapter 5: stratix iv dynamic reconfiguration 5?91 error indication during dynamic reconfiguration ? march 2010 altera corporation stratix iv device handbook volume 2 error indication during dynamic reconfiguration the altgx_reconfig megawizard plug-in manager provides an error status signal when you select the enable illegal mode checking option or the enable self recovery option in the error checks/data rate switch screen. the conditions under which the error signal is asserted are: enable illegal mode checking option ?when you select this option, the dynamic reconfiguration controller checks whether an attempted operation falls under one of the conditions listed below. the dynamic reconfiguration controller detects these conditions within two reconfig_clk cycles, de-asserts the busy signal, and asserts the error signal for two reconfig_clk cycles. pma controls, read operation?none of the output ports ( rx_eqctrl_out, rx_eqdcgain_out, tx_vodctrl_out, tx_preemp_0t_out , tx_preemp_1t_out , and tx_preemp_2t_out ) are selected in the altgx_reconfig instance and the read signal is asserted. pma controls, write operation?none of the input ports ( rx_eqctrl, rx_eqdcgain, tx_vodctrl, tx_preemp_0t, tx_preemp_1t , and tx_preemp_2t ) are selected in the altgx_reconfig instance and the write_all signal is asserted. tx data rate switch using local divider-read operation option?the read transaction is valid only for data rate division in transmitter mode tx data rate switch using local divider-write operation with unsupported value option: the rate_switch_ctrl input port is set to 11 the reconfig_mode_sel input port is set to 3 (if other reconfiguration mode options are selected in the reconfiguration settings screen) the write_all is asserted tx data rate switch using local divider-write operation without input port option: the rate_switch_ctrl input port is not used the reconfig_mode_sel port is set to 3 (if other reconfiguration mode options are selected in the reconfiguration settings screen) the write_all is asserted tx data rate switch using local divider- read operation without output port option: the rate_switch_out output port is not used the reconfig_mode_sel port is set to 3 (if other reconfiguration mode options are selected in the reconfiguration settings screen) the read is asserted channel and/or tx pll reconfig/select-read operation option: the reconfig_mode_sel input port is set to 4, 5, 6, or 7 the read signal is asserted 5?92 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration duration stratix iv device handbook volume 2 ? march 2010 altera corporation adaptive equalization option?read operation: reconfig_mode_sel input port is set to 7, 8, 9, or 10 read signal is asserted eyeq option?read operation: reconfig_mode_sel input port is set to 11 read signal is asserted enable self recovery option?when you select this option, the controller automatically recovers if the operation did not complete within the expected time. the error signal is driven high whenever the controller performs a self recovery. dynamic reconfiguration duration dynamic reconfiguration duration is the number of cycles the busy signal is asserted when the dynamic reconfiguration controller performs write transactions, read transactions, or offset cancellation of the receiver channels. pma controls reconfiguration duration the following section contains an estimate of the number of reconfig_clk clock cycles the busy signal is asserted during pma controls reconfiguration using method 1, method 2, or method 3. for more information, refer to ?dynamically reconfiguring pma controls? on page 5?13 . pma controls reconfiguration duration when using method 1 the logical_channel_address port is used in method 1. the write transaction and read transaction duration is as follows: write transaction duration for writing values to the following pma controls, the busy signal is asserted for 260 reconfig_clk clock cycles for each of these controls: tx_preemp_1t (pre-emphasis control first post-tap) tx_vodctrl (voltage output differential) rx_eqctrl (equalizer control) rx_eqdcgain (equalizer dc gain) for writing values to the following pma controls, the busy signal is asserted for 520 reconfig_clk clock cycles for each of these controls: tx_preemp_0t (pre-emphasis control pre-tap) tx_preemp_2t (pre-emphasis control second post-tap) chapter 5: stratix iv dynamic reconfiguration 5?93 dynamic reconfiguration duration ? march 2010 altera corporation stratix iv device handbook volume 2 read transaction duration for reading the existing values of the following pma controls, the busy signal is asserted for 130 reconfig_clk clock cycles for each of these controls. the data_valid signal is then asserted after the busy signal goes low. tx_preemp_1t_out (pre-emphasis control first post-tap) tx_vodctrl_out (voltage output differential) rx_eqctrl_out (equalizer control) rx_eqdcgain_out (equalizer dc gain) for reading the existing values of the following pma controls, the busy signal is asserted for 260 reconfig_clk clock cycles for each of these controls. the data_valid signal is then asserted once the busy signal goes low. tx_preemp_0t_out (pre-emphasis control pre-tap) tx_preemp_2t_out (pre-emphasis control second post-tap) pma controls reconfiguration duration when using method 2 or method 3 the logical_channel_address port is not used in method 2 and method 3. the write transaction duration and read transaction duration are as follows: write transaction duration for writing values to the following pma controls, the busy signal is asserted for 260 reconfig_clk clock cycles per channel for each of these controls: tx_preemp_1t (pre-emphasis control first post-tap) tx_vodctrl (voltage output differential) rx_eqctrl (equalizer control) rx_eqdcgain (equalizer dc gain) for writing values to the following pma controls, the busy signal is asserted for 520 reconfig_clk clock cycles per channel for each of these controls: tx_preemp_0t (pre-emphasis control pre-tap) tx_preemp_2t (pre-emphasis control second post-tap) read transaction duration for reading the existing values of the following pma controls, the busy signal is asserted for 130 reconfig_clk clock cycles per channel for each of these controls. the data_valid signal is then asserted after the busy signal goes low. tx_preemp_1t_out (pre-emphasis control first post-tap) tx_vodctrl_out (voltage output differential) rx_eqctrl_out (equalizer control) rx_eqdcgain_out (equalizer dc gain) 5?94 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration duration stratix iv device handbook volume 2 ? march 2010 altera corporation for reading the existing values of the following pma controls, the busy signal is asserted for 260 reconfig_clk clock cycles per channel for each of these controls. the data_valid signal is then asserted after the busy signal goes low. tx_preemp_0t_out (pre-emphasis control pre-tap) tx_preemp_2t_out (pre-emphasis control second post-tap) offset cancellation duration when the device powers up, the busy signal remains low for the first reconfig_clk clock cycle. offset cancellation control is only for the receiver channels. the altgx_reconfig instance takes approximately 18307 reconfig_clk clock cycles per channel for receiver only and receiver and transmitter channels. it takes approximately 877 reconfig_clk clock cycles per channel for transmitter only channels to determine if the channel under reconfiguration is a receiver channel or not. the atlgx_reconfig requires an add it on al 130,000 clock cycles for these values to take effect. the altgx_reconfig instance takes approximately two reconfig_clk clock cycles per channel for the unused logical channels. to demonstrate offset cancellation duration, consider the following example: one altgx_reconfig instance is connected to two altgx instances. altgx instance 1 has one transmitter only channel (logical_channel_address = 0) altgx instance 2 has one receiver only channel (logical_channel_address = 4) for this example, the altgx_reconfig instance consumes the following number of reconfig_clk clock cycles for offset cancellation: 877 cycles for the transmitter only channel 18307 cycles for the receiver only channel 2 cycles each for non-existent channels with logical_channel_addresses = 1, 2, and 3. 130000 cycles as a baseline for the values to take affect. the offset cancellation duration for the altgx_reconfig instance to reconfigure the transmitter only channel, receiver only channel, non-existent logical channels 1, 2, and 3 = 149190 cycles (877 +18307 +6 + 130000). dynamic reconfiguration duration for channel and transmitter pll select/reconfig modes table 5?17 lists the number of reconfig_clk clock cycles it takes for the dynamic reconfiguration controller to reconfigure various parts of the transceiver channel and cmu pll. table 5?17. dynamic reconfiguration duration for transceiver channel and cmu pll reconfiguration (part 1 of 2) transceiver portion under reconfiguration number of reconfig_clk clock cycles transmitter channel reconfiguration 1518 clock cycles receiver channel reconfiguration 5255 clock cycles transmitter and receiver channel reconfiguration 6762 clock cycles cmu pll only reconfiguration 863 clock cycles chapter 5: stratix iv dynamic reconfiguration 5?95 dynamic reconfiguration (altgx_reconfig instance) resource utilization ? march 2010 altera corporation stratix iv device handbook volume 2 dynamic reconfiguration (altgx_reconfig instance) resource utilization you can observe the resources used during dynamic reconfiguration in the altgx_reconfig megawizard plug-in manager. this section contains an estimate of the le resources used during dynamic reconfiguration. you can obtain resource utilization for all other pma controls from the altgx_reconfig megawizard plug-in manager. for example, the number of les used by one dynamic reconfiguration controller is 43 with only tx_vodctrl selected and the number of registers is 130. figure 5?41 shows resource utilization in the altgx_reconfig megawizard plug-in manager. transmitter channel and cmu pll reconfiguration 2370 clock cycles transceiver channel and cmu pll reconfiguration 7614 clock cycles central control unit reconfiguration 925 clock cycles table 5?17. dynamic reconfiguration duration for transceiver channel and cmu pll reconfiguration (part 2 of 2) transceiver portion under reconfiguration number of reconfig_clk clock cycles figure 5?41. resource utilization in the altgx_reconfig megawizard plug-in manager 5?96 chapter 5: stratix iv dynamic reconfiguration functional simulation of the dynamic reconfiguration process stratix iv device handbook volume 2 ? march 2010 altera corporation functional simulation of the dynamic reconfiguration process this section describes the points to be considered during functional simulation of the dynamic reconfiguration process. you must connect the altgx_reconfig instance to the altgx_instance/altgx instances in your design for functional simulation. the functional simulation uses a reduced timing model of the dynamic reconfiguration controller. the duration of the offset cancellation process is 16 reconfig_clk clock cycles for functional simulation only. the gxb_powerdown signal must not be asserted during the offset cancellation sequence (for functional simulation and silicon). dynamic reconfiguration examples the following examples help to describe the dynamic reconfiguration feature. example 1 consider a design with the following configuration: seven regular transceiver channels in basic functional mode. you can configure the seven regular transceiver channels from 2.5 gbps to 5 gbps and vice versa using a single cmu. four channels in basic (pma direct) functional mode. you can reconfigure the four pma-only channels from 3.125 gbps to 5 gbps and vice versa. you can reconfigure the pma controls for any one of these channels. chapter 5: stratix iv dynamic reconfiguration 5?97 dynamic reconfiguration examples ? march 2010 altera corporation stratix iv device handbook volume 2 figure 5?42 shows the arrangement of these channels in the s4gx230 device. because this example does not require the use of the alternate cmu transmitter pll or additional transmitter plls, the logical channel addressing remains the same as explained in ?logical channel addressing? on page 5?5 . figure 5?42. dynamic reconfiguration configuration for the s4gx230 device (example 1) transcei v er block gxbr2 channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 transcei v er block gxbr1 channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 atx r0 pll block transcei v er block gxbr0 channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 regu lar transceiv er channels pma-only channels fo ur pma-only channels use a single cmu0 pll (gxbr0) in the design se v en regu lar transceiv er channels use a single cmu0 pll (gxbr2) in the design 5?98 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration examples stratix iv device handbook volume 2 ? march 2010 altera corporation table 5?18 lists how to set the starting channel number in the altgx megawizard plug-in manager, the total number of channels in the altgx_reconfig megawizard plug-in manager, and how to connect the altgx instances to the altgx_reconfig instance. table 5?18. logical channel addressing combination of regular transceiver channels and pma-only channels (example 1) altgx settings and instances altgx_reconfig setting and instance altgx setting altgx instance 1 (basic functional mode) altgx instance 2 (basic [pma direct] functional mode) altgx_reconfig setting altgx_reconfig instance 1 what is the number of channels? option in the general screen 7 (regular transceiver channels) 4 (pma-only channels) what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. determine the highest logical channel address (20). round it up to the next multiple of 4. set this option to 24 . what is the starting channel number? option in the reconfig screen set this option to 0 . the logical channel addresses of the first to sixth channels are 0 , 1 , 2 , 3 , 4 , 5 , and 6 , respectively. set this option to 8 . this is because the starting channel numbers 0 and 4 have already been used in altgx instance 1. the logical channel addresses of the first to fourth channels are 8 , 12 , 16 , and 20 , respectively. ?? reconfig_ fromgxb1 and reconfig_ fromgxb2 outputs reconfig_ fromgxb1 is 34 bits wide ( 2 * 17) reconfig_ fromgxb2 is 68 bits wide ( 4 * 17) reconfig_ fromgxb input reconfig_ fromgxb is 102 bits wide ( 24 regular transceiver channels can logically fit into 6 transceiver blocks; 6 * 17 = 102) chapter 5: stratix iv dynamic reconfiguration 5?99 dynamic reconfiguration examples ? march 2010 altera corporation stratix iv device handbook volume 2 figure 5?43 shows how the logical channel addresses of all the channels are set, based on what you set as the starting channel number. figure 5?43. logical channel addresses for example 1 notes to figure 5?43 : (1) for more information, refer to ?total number of channels option in the altgx_reconfig instance? on page 5?10 . (2) reconfig_fromgxb[101:0] = { reconfig_fromgxb2[67:0] , reconfig_fromgxb1[33:0]} altgx instance 1 basic functional mode starting channel number = 0 altgx_reconfig instance 1 set the what is the number of channels controlled by the reconfig controller? option = 24 (1) altgx instance 2 basic (pma direct) configuration starting channel number = 8 reconfig_fromgxb1[33:0] reconfig_fromgxb2[67:0] reconfig_fromgxb[101:0] (2) reconfig_togxb[3:0] channel 0 (logical channel address = 0) channel 1 (logical channel address = 1) channel 2 (logical channel address = 2) channel 3 (logical channel address = 3) channel 4 (logical channel address = 4) channel 5 (logical channel address = 5) channel 6 (logical channel address = 6) channel 0 (logical channel address = 8) channel 1 (logical channel address = 12) channel 2 (logical channel address = 16) channel 3 (logical channel address = 20) 5?100 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration examples stratix iv device handbook volume 2 ? march 2010 altera corporation different dynamic reconfiguration modes involved 1. channel and cmu pll reconfiguration mode: is used for reconfiguring the seven regular transceiver channels from one data rate to another using the same cmu0 pll (in gxbr2) 1 this mode is chosen because both the receiver and transmitter of the regular channels must be re-configured using a single cmu. 2. channel and cmu pll select reconfiguration mode: is used for reconfiguring the four pma-only channels from one data rate to another using cmu0 pll (in gxbr0) and cmu1 pll (gxbr0) 1 this mode is chosen because both the receiver and transmitter of the regular channels must be re-configured and more than one cmu can be used. 3. the rx_tx_duplex_sel[1:0] port allows you to reconfigure the transmitter and receiver channels to operate at the different data rates. 4. pma controls reconfiguration mode used to configure the pma settings for all the channels. for more information, refer to ?transceiver channel reconfiguration mode details? on page 5?19 . .mif generation the following .mifs are required for this example: for the seven regular transceiver channels, you will need to generate two .mifs . one to move from a data rate of 2.5 gbps to 5 gbps and the other revert back to 2.5 gbps. for the for pma-only channels, you will need to generate two .mifs . one to move from a data rate of 3.125 gbps to 5 gbps and the other revert back to 3.125 gbps. for more information, refer to ?memory initialization file (.mif)? on page 5?19 . various dynamic reconfiguration transactions the following dynamic reconfiguration transactions are required ?example 1? on page 5?96 : .mif write transaction?for more information, refer to ?channel and cmu pll reconfiguration mode details? on page 5?24 and ?channel reconfiguration with transmitter pll select mode details? on page 5?48 . reconfiguring pma controls?for more information, refer to ?dynamically reconfiguring pma controls? on page 5?13 . chapter 5: stratix iv dynamic reconfiguration 5?101 dynamic reconfiguration examples ? march 2010 altera corporation stratix iv device handbook volume 2 example 2 consider a design with the following configuration: four regular transceiver channels in xaui configuration. you can configure these channels from the xaui configuration (the primary configuration) to the pci express (pipe) gen2 4 configuration (the secondary configuration) and vice versa. figure 5?44 shows the arrangement of these channels in the s4gx230 device. because this example does not require the use of the alternate cmu transmitter pll or additional transmitter plls, the logical channel addressing remains the same as explained in ?logical channel addressing? on page 5?5 . table 5?19 lists how to set the starting channel number in the altgx megawizard plug-in manager, the total number of channels in the altgx_reconfig megawizard plug-in manager, and how to connect the altgx instances to the altgx_reconfig instance. figure 5?44. dynamic reconfiguration configuration for the s4gx230 device (example 2) transcei v er block gxbr0 channel 3 channel 2 cmu1 channel cmu0 channel channel 1 channel 0 fo ur regular channels using the cmu0 pll in the design 1 0 156.25 mhz for xaui 100 mhz for pipe gen2 x4 mode table 5?19. logical channel addressing combination 4 bonded channels (example 2) (part 1 of 2) altgx settings and instances altgx_reconfig setting and instance altgx setting altgx instance 1 (xaui mode) altgx_reconfig setting altgx_reconfig instance 1 what is the number of channels? option in the general screen 4 (regular transceiver channels) what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. determine the highest logical channel address (3). round it up to the next multiple of 4. set this option to 4 . what is the starting channel number? option in the reconfig screen set this option to 0 . the logical channel addresses of the first to sixth channels are 0 , 1 , 2 , and 3 , respectively. ?? 5?102 chapter 5: stratix iv dynamic reconfiguration dynamic reconfiguration examples stratix iv device handbook volume 2 ? march 2010 altera corporation figure 5?45 shows how the logical channel addresses of all the channels are set, based on what you set as the starting channel number. settings in reconfiguration settings page enable channel and transmitter pll reconfiguration enable channel interface set 2 for the how many clock inputs are used? option. set 0 for the xaui altgx instance and set 1 for the pci express (pipe) gen2 x4 altgx instance for the what is the selected input clock source for tx/rx plls? option. ?? reconfig_fromgxb1 and reconfig_fromgxb2 outputs reconfig_fromgxb1 is 17 bits wide reconfig_fromgxb input reconfig_fromgxb is 17 bits wide ( 4 regular transceiver channels can logically fit into 1 transceiver blocks; 1 * 17 = 17) table 5?19. logical channel addressing combination 4 bonded channels (example 2) (part 2 of 2) altgx settings and instances altgx_reconfig setting and instance altgx setting altgx instance 1 (xaui mode) altgx_reconfig setting altgx_reconfig instance 1 figure 5?45. logical channel addresses for example 2 set the what is the number of channels controlled by the reconfi g controller? option = 4 reconfig_fromgxb[16:0] * altgx_reconfig instance reconfig_fromgxb[16:0] altgx instance 1 fo ur regu lar transceiv er channels xaui/pci express (pipe) gen2 x4 f unctional mode starting channel n umber = 0 reconfig_togx b[3:0] channel 0 (logical channel address = 0) channel 1 (logical channel address = 1) channel 2 (logical channel address = 2) channel 3 (logical channel address = 3) chapter 5: stratix iv dynamic reconfiguration 5?103 dynamic reconfiguration examples ? march 2010 altera corporation stratix iv device handbook volume 2 different dynamic reconfiguration modes involved 1. channel and cmu pll reconfiguration mode?used for reconfiguring four regular transceiver channels and cmu0 pll (in gxbr0) from xaui mode to pci express (pipe) 4 mode and vice versa. 1 use this mode instead of channel reconfiguration with transmitter pll select mode because the central clock divider used for bonded modes is only available in cmu0 ; therefore, you cannot use cmu1 as an alternate tx pll. 2. central control unit reconfiguration mode?used for reconfiguring central control unit logic used in bonded modes from xaui mode to pci express (pipe) 4 mode. for more information, refer to ?transceiver channel reconfiguration mode details? on page 5?19 . .mif generation the following .mifs are required for this example: one .mif is needed to move from xaui mode to pci express (pipe) 4 mode another .mif is needed to revert back to xaui mode from pci express (pipe) 4 mode for more information, refer to ?memory initialization file (.mif)? on page 5?19 . various dynamic reconfiguration transactions the following dynamic reconfiguration transactions are required for this example: .mif write transaction?for more information, refer to ?channel and cmu pll reconfiguration mode details? on page 5?24 . alternatively, you may use reduced .mif reconfiguration. reduced .mifs are generated using the altgx_diffmifgen.exe command. for more information, refer to ?reduced .mif reconfiguration? on page 5?23 . 5?104 chapter 5: stratix iv dynamic reconfiguration document revision history stratix iv device handbook volume 2 ? march 2010 altera corporation document revision history table 5?20 shows the revision history for this chapter. table 5?20. document revision history date and document version changes made summary of changes march 2010, v3.1 updated tab le 5 ?5 , ta bl e 5? 6, tab le 5 ?1 5 , table 5?16 , and table 5?17 . updated figure 5?1 , figure 5?14 , figure 5?16 , figure 5?26 , and figure 5?37 . updated the ?blocks reconfigured in the data rate division in transmitter mode? , ?logical channel addressing of pma-only channels? , ?central control unit reconfiguration mode details? , ?eyeq? , ?error indication during dynamic reconfiguration? , and ?functional simulation of the dynamic reconfiguration process? sections. added a note to the ?central control unit reconfiguration mode details? section. minor text edits. ? november 2009, v3.0 completely re-wrote and re-organized chapter. updated all graphics and tables. ? june 2009, v2.1 updated figure 5?4, figure 5?8, figure 5?9, figure 5?10, figure 5?11, figure 5?15, figure 5?22, table 5?37, table 5?38, figure 5?44, figure 5?47, figure 5?48, figure 5?49, figure 5?50, figure 5?51, figure 5?52, figure 5?53, and figure 5?54 updated table 5?2 and table 5?31 changed ?logical_tx_pll_sel[1:0]? to ?logical_tx_pll_sel? throughout updated ?the reconfig_clk clock requirements for the altgx instance and altgx_reconfig instance?, ?the logical_tx_pll_sel and logical_tx_pll_sel_en ports?, ?how to use the logical_tx_pll_sel port??, and ?when can the logical_tx_pll_sel and logical_tx_pll_sel_en ports be used?? minor text edits ? march 2009, v2.0 complete re-write and re-organization of the chapter. added or revised: offset cancellation control for receiver channels pma controls reconfiguration channel and cmu pll reconfiguration mode data rate division in transmitter: operation channel reconfiguration with transmitter pll select mode cmu pll reconfiguration mode ? november 2008, v1.0 initial release ? 101 innovation drive san jose, ca 95134 www.altera.com stratix iv device handbook volume 3 siv5v3-4.0 copyright ? 2009 altera corporation. all rights reserved. altera, the programmable solutions company, the stylized altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of their respective holders. altera products are protected under numerous u.s. and foreign patents and pending ap- plications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specification s in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibilit y or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera cu stomers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services . ? november 2009 altera corporation stratix iv device handbook volume 3 contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v additional information about this handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .info-vii how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .info-vii typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .info-vii section i. transceiver configuration guide revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 chapter 1. altgx transceiver setup guide parameter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 general screen for the parameter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 pll/ports screen for the parameter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 ports/calibration screen for the parameter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 loopback screen for the parameter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 rx analog screen for the parameter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 tx analog screen for the parameter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 reconfiguration settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 modes screen for the reconfiguration settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 transmitter pll settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 clocking/interface screen for the reconfiguration settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 protocol settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 8b10b screen for the protocol settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 word aligner screen for the protocol settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 rate match/byte order screen for the protocol settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 44 protocol settings screen for gige and xaui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47 protocol settings screen for the (oif) cei phy interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50 protocol settings screen for pci express (pipe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 protocol settings screen for sonet/sdh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 eda screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-61 summary screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-63 chapter 2. transceiver design flow guide architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 device specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 transceiver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 dynamic reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 board design requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 iv contents stratix iv device handbook volume 3 ? november 2009 altera corporation implementation and integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 create transceiver instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 create dynamic reconfiguration controller instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 create reset and control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 create data processing and other user logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 ppm detector when the receiver cdr is used in manual lock mode . . . . . . . . . . . . . . . . . . . . . 2-8 synchronization state machine in manual word alignment mode . . . . . . . . . . . . . . . . . . . . . . . . 2-9 gear boxing logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 integrate the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 report files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 fitter summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 pin-out file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 resource section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 functional simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 guidelines to debug transceiver-based designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 guidelines to debug the fpga logic and the transceiver interface . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 guidelines to debug system level issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 example 1: fibre channel protocol application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 phase 1?architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 device specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 transceiver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 dynamic reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 phase 2?implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 create the transceiver instance for an fc4g configuration (channel 0) . . . . . . . . . . . . . . . . . . . 2-21 create the transceiver instance for an fc1g configuration (channel 1) . . . . . . . . . . . . . . . . . . . 2-30 create the instance for an fc4g configuration?transmitter only mode (channel 2) . . . . . . 2-31 create the dynamic reconfiguration controller (altgx_reconfig) instance . . . . . . . . . . . . . . 2-33 create reset logic to control the fpga fabric and transceivers . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 create data processing and other user logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 phase 3?compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 phase 4?simulating the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 chapter 3. stratix iv altgx_reconfig megafunction user guide dynamic reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 ? november 2009 altera corporation stratix iv device handbook volume 3 chapter revision dates the chapters in this book, stratix iv device handbook volume 3 , were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1 altgx transceiver setup guide revised: november 2009 part number: siv53001-4.0 chapter 2 transceiver design flow guide revised: november 2009 part number: siv53002-4.0 chapter 3 stratix iv altgx_reconfig megafunction user guide revised: november 2009 part number: siv53004-3.0 vi chapter revision dates stratix iv device handbook volume 3 ? november 2009 altera corporation ? november 2009 altera corporation stratix iv device handbook volume 3 additional information about this handbook this handbook provides comprehensive information about the altera ? stratix ? iv family of devices. how to contact altera for the most up-to-date information about altera products, see the following table. typographic conventions the following table shows the typographic conventions that this document uses. contact (note 1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature non-technical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicates command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicates document titles. for example, an 519: stratix iv design guidelines. italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, info?viii additional information stratix iv device handbook volume 3 ? november 2009 altera corporation courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . active-low signals are denoted by suffix n . for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). 1., 2., 3., and a., b., c., and so on. numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. r the angled arrow instructs you to press enter . f the feet direct you to more information about a particular topic. visual cue meaning ? november 2009 altera corporation stratix iv device handbook volume 3 section i. transceiver configuration guide this section includes the following chapters: chapter 1, altgx transceiver setup guide chapter 2, transceiver design flow guide chapter 3, stratix iv altgx_reconfig megafunction user guide revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook. i?2 section i: transceiver configuration guide stratix iv device handbook volume 3 ? november 2009 altera corporation ? november 2009 altera corporation stratix iv device handbook volume 3 1. altgx transceiver setup guide this chapter describes the options you can choose in the altgx megawizard ? plug-in manager in the quartus ? ii software to configure stratix ? iv gx and gt devices in different functional modes. the megawizard plug-in manager in the quartus ii software creates or modifies de sign files that contain custom megafunction variations that can then be instantiated in a design file. the megawizard plug-in manager provides a megawizard that allows you to specify options for the altgx megafunction. you can use the megawizard plug-in manager to set the altgx megafunction features in the design. the altgx megafunction allows you to configure one or more transceiver channels. you can select the physical coding sublayer (pcs) and physical medium attachment (pma) functional blocks depending on your transceiver configuration. this chapter contains the following sections: ?parameter settings? on page 1?3 ?reconfiguration settings? on page 1?28 ?protocol settings? on page 1?35 start the megawizard plug-in manager using one of the following methods: from the tools menu, select megawizard plug - in manager . when working in the block editor, click megawizard plug - in manager in the symbol dialog box (edit menu). start the stand-alone version of the megawizard plug-in manager by typing the following command at the command prompt: qmegawiz. figure 1?1 shows the first page of the megawizard plug-in manager. to generate an altgx custom megafunction variation, select cr eate a new custom megafunction variation . figure 1?1. megawizard plug-in manager (page 1) siv53001-4.0 1?2 chapter 1: altgx transceiver setup guide stratix iv device handbook volume 3 ? november 2009 altera corporation figure 1?2 shows the second page of the megawizard plug-in manager. to use the megawizard plug-in manager to configure a stratix iv device: 1. select stratix iv as the device family. 2. select either vhdl or verilog hdl depending on the type of output files you want to create. 3. select the altgx megafunction under the i/o section of the available megafunctions. 4. name the output file, and then browse to the folder you want to save your file in and click next . the general screen of the altgx megawizard plug-in manager opens ( figure 1?3 ). 1 all reset and control signals are active high unless otherwise mentioned. 1 all output ports are synchronous to the data path unless otherwise specified. figure 1?2. megawizard plug-in manager (page 2) chapter 1: altgx transceiver setup guide 1?3 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 1 throughout this chapter, the various functional modes and their settings are explained for stratix iv gx and gt devices. parameter settings this section describes the options available on the individual pages of the altgx megawizard plug-in manager for the parameter settings. the megawizard plug-in manager provides a warning if any of the settings you choose are illegal. general screen for the parameter settings figure 1?3 shows the gen eral screen of the altgx megawizard plug-in manager for the parameter settings. figure 1?3. megawizard plug - in manager?altgx (general screen for the parameter settings) 1?4 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation ta b l e 1?1 describes the available functional modes and their options on the gen eral screen of the megawizard plug-in manager. depending on your configuration, you will s elect one of the following functional modes: basic basic (pma direct) deterministic latency gige (oif) cei phy interface pci express (pipe) sdi serial rapidio sonet/sdh xaui if you select basic (pma direct) mode, all the channels are configured with only the pma bl ocks. these channels are called pma-only channels throughout this chapter. the pma-only channels include: regular transceiver channels with pma blocks only cmu channels (clock multiplier unit phase-locked loops [cmu plls] configured as additional transceiver channels with pma blocks only) chapter 1: altgx transceiver setup guide 1?5 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 table 1?1. megawizard plug- in manager options (general screen for basic mode) (part 1 of 10) altgx setting description reference which device variation will you be using? select gx or gt based on the stratix iv device used in your design. select the speed grade of your device. the available speed grades for the stratix iv gx device are 2, 2, 3, and 4. based on the speed grade you select, the corresponding stratix iv device can operate at the following maximum speeds: -2 => 8.5 gbps -2, 3 => 6.5 gbps -4 => 5 gbps the available speed grades for the stratix iv gt device are 1, 2 and 3. refer to datasheet for the supported data rates. table 1-22 and table 1-23 in the dc and switching characteristics chapter. stratix iv device datasheet section. which protocol will you be using? determines the specific protocol under which the transceiver operates. for a specific mode, you must select the desired protocol from the following list: basic basic (pma direct) deterministic latency gige (oif) cei phy interface pci express (pipe) serial rapidio table 1-1 in the stratix iv transceiver architecture chapter in volume 2 of the stratix iv device handbook. which protocol will you be using? determines the specific protocol under which the transceiver operates. for a specific mode, you must select the desired protocol from the following list: (oif) cei phy interface sdi sonet/sdh xaui table 1-2 in the stratix iv transceiver architecture chapter in volume 2 of the stratix iv device handbook. 1?6 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation which subprotocol will you be using? basic in basic mode, the subprotocols are diagnostic modes. the available options are as follows: none?this is the normal operation of the transceiver. 4?in this mode, all four channels within the transceiver block are clocked from its central clock divider block to minimize transmitter channel-to-channel skew. 8?in this mode, all eight channels in two transceiver blocks are clocked from the central clock divider of the master transceiver block to minimize transmitter channel-to-channel skew. bist?this subprotocol is applicable only for receiver and transmitter operation mode. this mode loops the parallel data from the built-in self test (bist) (non-prbs) back to the bist verifier in the receiver path. parallel loopback is allowed only in basic double-width mode. prbs?this subprotocol is applicable only for receiver and transmitter operation mode.this is another serial loopback mode but with the pseudo-random binary sequence (prbs) bist block active. the prbs pattern depends on the serializer/deserializer (serdes) factor. ?basic functional mode? section in the stratix iv transceiver architecture chapter . basic (pma direct) none?this is the normal mode of operation in which each channel is treated independently. xn?in this mode, the ?n? in xn represents the number of channels in the bonded configuration. all n channels are clocked by the same transmit clock from the central clock divider block to minimize transmitter channel-to-channel skew. ?basic pma direct functional mode? section in the stratix iv transceiver architecture chapter . deterministic latency 1?in this mode, you can have up to two configured channels per transceiver block. each channel uses one cmu pll and its feedback path to compensate for the uncertain latency. 4?in this mode, you can have up to four configured channels per transceiver block. all channels use one cmu pll per block and its feedback path to compensate for the uncertain latency. ?deterministic latency mode? section in the stratix iv transceiver architecture chapter . table 1?1. megawizard plug- in manager options (general screen for basic mode) (part 2 of 10) altgx setting description reference chapter 1: altgx transceiver setup guide 1?7 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 which subprotocol will you be using? pci express (pipe) in pci express (pipe) mode, there are six subprotocols: gen1 1?the transceiver is configured as a single-lane pci express (pipe) link for a 2.5 gbps data rate. gen1 4?the transceiver is configured as a four-lane pci express (pipe) link for a data rate of 2.5 gbps. gen1 8?the transceiver is configured as an eight-lane pci express (pipe) link for a data rate of 2.5 gbps. gen2 1?the transceiver is configured as a single-lane pci express (pipe) link for a 5.0 gbps data rate. gen2 4?the transceiver is configured as a four-lane pci express link for a data rate of 5.0 gbps. gen2 8?the transceiver is configured as an eight-lane pci express (pipe) link for a data rate of 5.0 gbps. ?pci express (pipe) mode? in the stratix iv transceiver architecture chapter . sdi in sdi mode, the two available subprotocols are: 3g?third-generation (3 gbps) sdi at 2967 mbps or 2970 mbps. hd?high-definition sdi at 1483.5 mbps or 1485 mbps. ?sdi mode? in the stratix iv transceiver architecture chapter . sonet/sdh in sonet/sdh mode, the three available subprotocols and their data rates are: oc-12?622 mbps oc-48?2488.32 mbps oc-96?4976.64 mbps ?sonet/sdh mode? in the stratix iv transceiver architecture chapter . enforce default settings for this protocol. deterministic latency gige (oif) cei phy interface pci express (pipe) sonet/sdh xaui if you select this option, all mode-specific ports and settings are used. ? table 1?1. megawizard plug- in manager options (general screen for basic mode) (part 3 of 10) altgx setting description reference 1?8 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation what is the operation mode? basic basic (pma direct) deterministic latency sdi serial rapidio sonet/sdh the available operation modes are receiver only , transmitter only , and receiver and transmitter . ? gige the available operation modes are transmitter only , and receiver and transmitter . ? pci express (pipe) xaui only receiver and transmitter mode is allowed. ? what is the number of channels? basic basic (pma direct) deterministic latency sdi serial rapidio the number of channels required with the same configuration. this option determines how many identical channels this altgx instance contains. ? gige (oif) cei phy interface sonet/sdh this option allows you to select how many channels this altgx instance contains. in these modes, the number of channels increments by one. ? pci express (pipe) this is the number of channels required with the same configuration. in a 4 subprotocol, the number of channels increments by 4. in a 8 subprotocol, the number of channels increment by 8. ? xaui this option allows you to select how many identical channels this altgx instance contains. in xaui mode, the number of channels increments by 4. ? table 1?1. megawizard plug- in manager options (general screen for basic mode) (part 4 of 10) altgx setting description reference chapter 1: altgx transceiver setup guide 1?9 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 what is the deserializer block width? basic basic (pma direct) deterministic latency this option sets the transceiver data path width. single - width ?this mode operates from 600 mbps to 3.75 gbps. double - width ?this mode operates from 1 gbps to 8.5 gbps. ?basic single-width mode configurations? and ?basic double-width mode configurations ? sections in the stratix iv transceiver architecture chapter . gige pci express (pipe) sdi serial rapidio xaui these modes only operate in single-width mode. double-width mode is not allowed. ? (oif) cei phy interface the (oif) cei phy interface mode only operates in double-width mode. single-width mode is not allowed. ? sonet/sdh this option allows you to set the transceiver data path width. single-width ?selected automatically in oc-12 and oc-48 configurations. the transceiver data path width is 8 bits. double-width ?selected automatically in oc-96 configurations. the transceiver data path width is 16 bits. ? table 1?1. megawizard plug- in manager options (general screen for basic mode) (part 5 of 10) altgx setting description reference 1?10 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation what is the channel width? basic deterministic latency this option determines the fpga fabric-transceiver interface width. single-width mode?selecting 8 or 10 bits bypasses the byte serializer/deserializer. selecting 16 or 20 bits uses the byte serializer/deserializer. double-width mode?selecting 16 or 20 bits bypasses the byte serializer/deserializer. selecting 32 or 40 bits uses the byte serializer/deserializer. ?byte serializer? and ? byte deserializer? sections in the stratix iv transceiver architecture chapter . basic (pma direct) this option determines the fpga fabric-transceiver interface width. single-width mode?you can select 8 or 10 bits. double-width mode? you can select 16 or 20 bits. gige this option determines the fpga fabric-transceiver interface width. in gige mode, only 8 bits are allowed. (oif) cei phy interface this option selects the fpga fabric-transceiver width. in (oif) cei phy interface mode, only 32 bits are allowed. pci express (pipe) this option determines the fpga fabric-transceiver interface width. in pci express (pipe) gen1 (2.5 gbps) mode, 8 and 16 bits are allowed. in pci express (pipe) gen2 (5 gbps) mode, only 16 bits are allowed. sdi this option determines the fpga fabric-transceiver interface width: hd mode?10-bit and 20-bit channel widths are allowed. 3g mode?only 20-bit channel width is allowed. 10-bit configuration?the byte serializer is not used. 20-bit configuration?the byte serializer is used. serial rapidio the channel width is fixed to 16 in serial rapidio mode. table 1?1. megawizard plug- in manager options (general screen for basic mode) (part 6 of 10) altgx setting description reference chapter 1: altgx transceiver setup guide 1?11 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 what is the channel width? sonet/sdh this option selects the fpga fabric-transceiver interface width. depending on your subprotocol selection, choose one of the following: 8 bits for oc-12 mode 16 bits for oc-48 mode 32 bits for oc-96 mode ?byte serializer? and ? byte deserializer? sections in the stratix iv transceiver architecture chapter . xaui xaui mode only operates in single-width mode. what would you like to base the setting on? basic basic (pma direct) you can select one of the following options: data rate ?selecting this option allows you to enter the transceiver channel serial data rate. based on the value you enter, the altgx megawizard plug-in manager populates the input reference clock frequency options in the what is the input clock frequency? field. the altgx megawizard plug-in manager determines these input reference clock frequencies depending on the available multiplier settings. input clock frequency ?selecting this option allows you to enter your input clock frequency. based on the value you enter, the altgx megawizard plug-in manager populates the data rate options in the what is the effective data rate? field. the altgx megawizard plug-in manager determines these data rate options depending on the available multipler settings. ? table 1?1. megawizard plug- in manager options (general screen for basic mode) (part 7 of 10) altgx setting description reference 1?12 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation what is the effective data rate? basic basic (pma direct) deterministic latency if you select the data rate option in the what would you like to base the setting on? field, the altgx megawizard plug-in manager allows you to specify the effective serial data rate value in this field. if you select the input clock frequency option in the what would you like to base the setting on? field, the altgx megawizard plug-in manager displays the list of effective serial data rates in this field. ? gige this option is not available in gige mode. the transceiver channel serial data rate is fixed to 1250 mbps in this mode. ? (oif) cei phy interface the allowed effective data rate is between 3125 mbps and 6500 mbps. enter the transceiver channel?s serial data rate in this field. ? pci express (pipe) this option is not available in pci express (pipe) mode. the defaults are: 2500 mbps for pci express (pipe) gen1 mode. 5000 mbps for pci express (pipe) gen 2 mode. ? sdi the effective data rate is fixed at: 2967 mbps or 2970 mbps in 3g mode. 1483.5 mbps or 1485 mbps in hd mode. ? serial rapidio enter one of these three data rates in this option: 1250 mbps. 2500 mbps. 3125 mbps. ? sonet/sdh the effective data rate is fixed at: 622 mbps in oc-12 mode. 2488.32 mbps in oc-48 mode. 4976 mbps in oc-96 mode. ? xaui the effective data rate can be from 3125 mbps to 3750 mbps. ? table 1?1. megawizard plug- in manager options (general screen for basic mode) (part 8 of 10) altgx setting description reference chapter 1: altgx transceiver setup guide 1?13 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 what is the input clock frequency? basic basic (pma direct) if you select the input clock frequency option in the what would you like to base the setting on? field, the altgx megawizard plug-in manager allows you to specify the input reference clock frequency in this field. if you select the data rate option in the what would you like to base the setting on? field, the altgx megawizard plug-in manager displays the list of input reference clock frequencies in this field. ?input reference clocking? section in the stratix iv transceiver clocking chapter . deterministic latency gige (oif) cei phy interface sdi sonet/sdh based on the effective data rate value in the what is the effective data rate? field, the altgx megawizard plug-in manager determines the input reference clock frequencies depending on the available multiplier settings. pci express (pipe) this option is not available in pci express (pipe) mode. the input reference clock frequency is fixed to 100 mhz in pci express (pipe) mode. serial rapidio xaui this option provides the available input reference clock frequencies depending on whether your effective serial data rate is 1250 mbps, 2500 mbps, or 3125 mbps and the available multiplier settings. table 1?1. megawizard plug- in manager options (general screen for basic mode) (part 9 of 10) altgx setting description reference 1?14 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation specify base data rate. basic basic (pma direct) the altgx megawizard plug-in manager provides you the base data rate options for the cmu/atx pll and receiver clock data recovery (cdr). if you select a value in this field that is greater than the value in the what is the effective data rate? field, the altgx megawizard plug-in manager enables the appropriate local clock divider values. the local divider is present in the and receiver channels. ? gige this option is not available in this mode because the data rate is fixed. the altgx megawizard plug-in manager provides you the base data rate options for the cmu pll and receiver cdr. ? (oif) cei phy interface serial rapidio xaui this option is not available in these modes. the altgx megawizard plug-in manager provides you the base data rate options for the cmu pll and receiver cdr. ? pci express (pipe) for gen1 1, an optional base data rate of either 2500 or 5000 mbps is available. ? sdi this option is not available this mode as the data rate is fixed in 3g and hd modes. the altgx megawizard plug-in manager provides you the base data rate options for the cmu pll and receiver cdr. ? sonet/sdh this option is not available in this mode as the data rates are fixed in oc-12, oc-48, and oc-96 modes. the altgx megawizard plug-in manager provides you the base data rate options for the cmu pll and receiver cdr in this option. ? table 1?1. megawizard plug- in manager options (general screen for basic mode) (part 10 of 10) altgx setting description reference chapter 1: altgx transceiver setup guide 1?15 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 pll/ports screen for the parameter settings figure 1?4 shows the pll/p orts screen of the altgx megawizard plug-in manager for the parameter settings. figure 1?4. megawizard plug - in manager?altgx (pll/ports screen) 1?16 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation ta b l e 1?2 describes the available options on the pll/ ports screen of the megawizard plug-in manager for your altgx custom megafunction variation. table 1?2. megawizard plug- in manager options (pll/ports screen) (part 1 of 3) altgx setting description reference train receiver clock and data recovery (cdr) from pll_inclk . if you select this option, the input reference clock to the cmu pll trains the receiver cdr. table 1-77 in the stratix iv transceiver architecture chapter . use atx transmitter pll this option is only available for certain data rates. refer to datasheet for the supported data rates. this option enables the auxiliary transmitter pll. this is a low-jitter pll that resides between the transceiver blocks and can be used as a transmitter pll. ?auxiliary transmit (atx) pll block? section in the stratix iv transceiver architecture , the stratix iv transceiver clocking chapter, and the stratix iv device datasheet section . enable pll phase frequency detector (pfd) feedback to compensate latency uncertainty in tx_dataout and tx_clkout paths relative to the reference clock. this option applies only when you select deterministic latency functional mode. ?cmu pll feedback? section in the stratix iv transceiver architecture chapter . what is the tx pll bandwidth mode? the available options are auto, low , medium , and high . select the appropriate option based on your system requirements. ?pll bandwidth setting? section in the stratix iv transceiver architecture chapter and the stratix iv device datasheet section . what is the receiver cdr bandwidth mode? the available options are auto, low , medium , and high . select the appropriate option based on your system requirements. ?clock and data recovery unit? section in the stratix iv transceiver architecture chapter and the stratix iv device datasheet section . what is the acceptable ppm threshold between the receiver cdr vco and the receiver input reference clock? in automatic lock mode, the cdr remains in lock-to-data (ltd) mode as long as the parts per million (ppm) difference between the cdr vco output clock and the input reference clock is less than the ppm value that you set in this option. if the ppm difference is greater than the ppm value that you set in this option, the cdr switches to lock-to-reference (ltr) mode. the range of values available in this option is 62.5 ppm to 1000 ppm. (1) ?automatic lock mode? section in the stratix iv transceiver architecture chapter . optional ports create a g xb_powerdown po rt to power down the transceiver block. when asserted, this signal powers down the entire transceiver block. if none of the channels are instantiated in a transceiver block, the quartus ii software automatically powers down the entire transceiver block. ?user reset and power down signals? section in the reset control and power down chapter . create a pll_powerdown port to power down the tx pll. each transceiver block has two cmu plls. each cmu/atx pll has a dedicated power down signal called pll_powerdown . this signal powers do wn t he c mu / at x pl l. ?user reset and power down signals? section in the reset control and power down chapter . chapter 1: altgx transceiver setup guide 1?17 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 create a rx_analogreset port for the analog portion of the receiver. the receiver analog reset port is available in receiver only and receiver and transmitter operation modes. this resets part of the analog portion of the receiver cdr in the receiver channel. altera recommends using this port to implement the recommended reset sequence. the minimum pulse width is two parallel clock cycles. ?user reset and power down signals? in the reset control and power down chapter . create a rx_digitalreset port for the digital portion of the receiver. the receiver digital reset port is available in receiver only and receiver and transmitter operation modes. this resets the pcs portion of the receiver channel. altera recommends using this port to implement the recommended reset sequence. the minimum pulse width is two parallel clock cycles. ?user reset and power down signals? section in the reset control and power down chapter . create a tx_digitalreset port for the digital portion of the transmitter. the transmitter digital reset port is available in transmitter only and receiver and transmitter operation modes. this resets the pcs portion of the transmitter channel. altera recommends using this port to implement the recommended reset sequence. the minimum pulse width is two parallel clock cycles. ?user reset and power down signals? section in the reset control and power down chapter . create a pll_locked port to indicate pll is in lock with the reference input clock. each cmu/atx pll has a dedicated pll_locked signal that is fed to the fpga fabric to indicate when the pll is locked to the input reference clock. ?transceiver reset sequences? section in the reset control and power down chapter . create an rx_locktorefclk port to lock the rx cdr to the reference clock. when this signal is asserted high, the ltr/ltd controller forces the receiver cdr to lock to the phase and frequency of the input reference clock. (1) , (2) ?ltr/ltd controller? section in the stratix iv transceiver architecture chapter . create an rx_locktodata port to lock the rx cdr to the received data. when this signal is asserted high, the ltr/ltd controller forces the receiver cdr to lock to the received data. (1) , (2) ?ltr/ltd controller? section in the stratix iv transceiver architecture chapter . create an rx_pll_locked port to indicate rx cdr is locked to the input reference clock. in ltr mode, this signal is asserted high to indicate that the receiver cdr has locked to the phase and frequency of the input reference clock. in ltd mode, this signal has no significance. (1) ?lock-to-reference (ltr) mode? section in the stratix iv transceiver architecture chapter . table 1?2. megawizard plug- in manager options (pll/ports screen) (part 2 of 3) altgx setting description reference 1?18 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation create an rx_freqlocked port to indicate rx cdr is locked to the received data. this signal is asserted high to indicate that the receiver cdr has switched from ltr to ltd mode. this signal has relevance only in automatic lock mode and may be required to control the transceiver resets, as described in the user reset and power down signals section in the reset control and power down chapter in volume 2 of the stratix iv device handbook. (1) ?ltr/ltd controller? section in the stratix iv transceiver architecture chapter . notes to table 1?2 : (1) ltr mode is lock-to-reference mode and ltd mode is lock-to-data mode. (2) when rx_locktorefclk and rx_locktodata are both asserted high, rx_locktodata takes precedence over rx_locktorefclk , forcing the cdr to lock to the received data. when both these signals are de-asserted, the ltr/ltd controller is configured in automatic lock mode. table 1?2. megawizard plug- in manager options (pll/ports screen) (part 3 of 3) altgx setting description reference chapter 1: altgx transceiver setup guide 1?19 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 ports/calibration screen for the parameter settings figure 1?5 shows the po rts/calibration screen of the altgx megawizard plug-in manager for the parameter settings. ta b l e 1?3 describes the available options on the po rts/calibration screen of the megawizard plug-in manager for your altgx custom megafunction variation. un less indicated otherwise, the options apply to all functional modes. figure 1?5. megawizard plug-in manager?altgx (ports/calibration screen) table 1?3. megawizard plug-in manager options (ports/calibration screen) (part 1 of 3) altgx setting description reference optional ports/controls create an rx_signaldetect port to indicate data input signal detection. this port is only available in basic and pci express (pipe) mode. ?signal threshold detection circuitry? section in the stratix iv transceiver architecture chapter . enable tx phase comp fifo in register mode. this option is only available in deterministic latency mode. ?tx phase compensation fifo status signal? section in the stratix iv transceiver architecture chapter . create an rx_phase_comp_fifo_error output port. this output port indicates a receiver phase compensation fifo overflow or under-run condition. ?receiver phase compensation fifo error flag? section in the stratix iv transceiver architecture chapter . 1?20 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation create a tx_phase_comp_fifo_error output port. this output port indicates a transmitter phase compensation fifo overflow or under-run condition. ?tx phase compensation fifo status signal? section in the stratix iv transceiver architecture chapter . create an rx_coreclk port to connect to the read clock of the rx phase compensation fifo. you can clock the parallel output data from the receiver using this optional input port. this port allows you to clock the read side of the receiver phase compensation fifo with a user-provided clock (fpga fabric clock, fpga fabric-transceiver interface clock, or input reference clock). ?fpga fabric-transceiver interface clocking? section in the stratix iv transceiver clocking chapter . create a tx_coreclk port to connect to the write clock of the tx phase compensation fifo. you can clock the parallel transmitter data generated in the fpga fabric using this optional input port. this port allows you to clock the write side of the transmitter phase compensation fifo with a user-provided clock (fpga fabric clock, fpga fabric-transceiver interface clock, or input reference clock). ?fpga fabric-transceiver interface clocking? section in the stratix iv transceiver clocking chapter . create a tx_forceelecidle input port in basic and pci express (pipe) modes, this optional input signal places the transmitter buffer in the electrical idle state. ?transceiver channel architecture? section in the stratix iv transceiver architecture chapter . use calibration block. the calibration block is always enabled. ?calibration blocks? section in the stratix iv transceiver architecture chapter . table 1?3. megawizard plug-in manager options (ports/calibration screen) (part 2 of 3) altgx setting description reference chapter 1: altgx transceiver setup guide 1?21 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 create an active high cal_blk_powerdown to power down the calibration block. asserting this signal high powers down the calibration block. a high-to-low transition on this signal restarts calibration. ?input signals to the calibration block? section in the stratix iv transceiver architecture chapter . what is the analog power (v cca_l/r )? the options available for selection are based on what you specify in the specify base data rate option: 3.3 v ?available up to 11.3 gbps for stratix iv gt devices only. 2.5 v ?available up to 4.25 gbps. auto ?the altgx megawizard plug-in manager automatically sets v cca_l/r to 2.5 v for the vco data rates less than 4.25 gbps. or v cca_l/r to 3.0 v for the vco data rates greater than 4.25 gbps. it is up to you to connect the correct voltage supply to the v cca_l/r pins on the board. ?general requirements to combine channels? section in the configuring multiple protocols and data rates chapter . table 1?3. megawizard plug-in manager options (ports/calibration screen) (part 3 of 3) altgx setting description reference 1?22 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation loopback screen for the parameter settings figure 1?6 shows the loopba ck screen of the altgx megawizard plug-in manager for the parameter settings. figure 1?6. megawizard plug - in manager?altgx (loopback screen) chapter 1: altgx transceiver setup guide 1?23 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 ta b l e 1?4 describes the available options on the loopba ck screen of the megawizard plug-in manager for your altgx custom megafunction variation. table 1?4. megawizard plug - in manager options (lpbk screen) altgx setting description reference which loopback option would you like? there are two options available: no loopback ?this is the default mode. serial loopback ?if you select serial loopback, the rx_seriallpbken port is available to control the serial loopback feature dynamically. ? 1'b1?enables serial loopback ? 1'b0?disables serial loopback this signal is asynchronous to the receiver datapath. ?serial loopback? section in the stratix iv transceiver architecture chapter . which reverse loopback option would you like? there are three options available: no reverse loopback ?this is the default mode. reverse serial loopback (pre-cdr) ?this is the loopback before the receiver?s cdr block to the transmitter buffer. the receiver path in pcs is active but the transmitter side is not. reverse serial loopback ?this is a loopback after the receiver?s cdr block to the transmitter buffer. the receiver path in pcs is active but the transmitter side is not. ?loopback modes? section in the stratix iv transceiver architecture chapter . 1?24 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation rx analog screen for the parameter settings figure 1?7 shows the rx analog screen of the altgx megawizard plug-in manager for the parameter settings. ta b l e 1?5 describes the available options on the rx a nalog screen of the megawizard plug-in manager for your altgx custom megafunction variation. figure 1?7. megawizard plug - in manager?altgx (rx analog screen) table 1?5. megawizard plug- in manager options (rx analog screen) (part 1 of 2) altgx setting description reference enable static equalizer control. this option enables the static equalizer settings. ?programmable equalization and dc gain? section in the stratix iv transceiver architecture chapter and the stratix iv device datasheet section . what is the dc gain? this dc gain option has five settings: 0 ? 0 db 1 ? 3 db 2 ? 6 db 3 ? 9 db 4 ? 12 db ?programmable equalization and dc gain? section in the stratix iv transceiver architecture chapter . chapter 1: altgx transceiver setup guide 1?25 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 what is the receiver common mode voltage (rx v cm )? the receiver common mode voltage is programmable to 0.82 v or 1.1 v. ?receiver channel datapath? section in the stratix iv transceiver architecture chapter . force signal detection. in pci express (pipe) mode, this option disables the signal threshold detect circuit for the receiver cdr. the receiver cdr no longer depends on the signal detect criterion to switch from ltr to ltd mode. ?signal threshold detection circuitry? section in the stratix iv transceiver architecture chapter . what is the signal detect threshold? use this option in pci express (pipe) or basic mode with the 8b10b block enabled and the rx_signaldetect port selected to determine the threshold level for the signal detect circuit. pipe mode?the levels are fixed. basic mode?a range of values depending on the data rate are available. the levels will be determined after characterization. ?signal threshold detection circuitry? section in the stratix iv transceiver architecture chapter . use external receiver termination. select this option if you want to use an external termination resistor instead of differential on-chip termination (oct). if checked, this option turns off the receiver oct. ?programmable differential on-chip termination? section in the stratix iv transceiver architecture chapter . what is the receiver termination resistance? this option allows you to select the receiver differential termination value. the settings allowed are: 85 100 120 150 . ?programmable differential on-chip termination? section in the stratix iv transceiver architecture chapter, and the stratix iv device datasheet section . table 1?5. megawizard plug- in manager options (rx analog screen) (part 2 of 2) altgx setting description reference 1?26 chapter 1: altgx transceiver setup guide parameter settings stratix iv device handbook volume 3 ? november 2009 altera corporation tx analog screen for the parameter settings figure 1?8 shows the tx an alog screen of the altgx megawizard plug-in manager for the parameter settings. figure 1?8. megawizard plug - in manager?altgx (tx analog screen) chapter 1: altgx transceiver setup guide 1?27 parameter settings ? november 2009 altera corporation stratix iv device handbook volume 3 ta b l e 1?6 describes the available options on the tx an alog screen of the megawizard plug-in manager for your altgx custom megafunction variation. table 1?6. megawizard plug- in manager options (tx analog screen) altgx setting description reference what is the transmitter buffer power (v cc h )? the options available for selection are based on what you enter in the what is the effective data rate? option. 1.4 v ?available up to 8.5 gbps. 1.5 v is available up to 6.5 gbps (not available for stratix iv gt). auto ?the altgx megawizard plug-in manager automatically sets v cch to 1.5 v for the effective data rates less than 6.5 gbps or v cch to 1.4 v for effective data rates greater than 6.5 gbps. it is up to you to connect the correct voltage supply to the v cch pins on the board. ?programmable transmit output buffer power (v cch )? section in the stratix iv transceiver architecture chapter . what is the transmitter common mode voltage (v cm )? the transmitter common mode voltage is fixed to 0.65 v. ?transmitter output buffer? in the stratix iv transceiver architecture chapter and the stratix iv device datasheet section . use external transmitter termination. this option is available if you want to use an external termination resistor instead of the differential on-chip termination. checking this option turns off the transmitter differential oct. ?programmable transmitter termination? section in the stratix iv transceiver architecture chapter and the stratix iv device datasheet section . select the transmitter termination resistance. this option selects the transmitter differential termination value. the settings allowed are 85 , 100 , 120 , and 150 . ?programmable transmitter termination? section in the stratix iv transceiver architecture chapter and the stratix iv device datasheet section . what is the voltage output differential (v od ) control setting? this option selects the v od of the transmitter buffer. the available v od settings change based on the transmitter termination resistance value. ?programmable output differential voltage? section in the stratix iv transceiver architecture chapter and and the stratix iv device datasheet section . what is the pre-emphasis first post-tap setting (% of v od )? this option sets the amount of pre-emphasis on the transmitter buffer using first post-tap. ?programmable pre-emphasis? section in the stratix iv transceiver architecture chapter . what is the pre-emphasis pre-tap setting (% of v od )? this option sets the amount of pre-emphasis on the transmitter buffer using pre-tap. ?programmable pre-emphasis? section in the stratix iv transceiver architecture chapter . what is the pre-emphasis second post-tap setting (% of v od )? this option sets the amount of pre-emphasis on the transmitter buffer using second post-tap. ?programmable pre-emphasis? section in the stratix iv transceiver architecture chapter . 1?28 chapter 1: altgx transceiver setup guide reconfiguration settings stratix iv device handbook volume 3 ? november 2009 altera corporation reconfiguration settings this section describes the various dynamic reconfiguration modes and settings for stratix iv gx and gt transceivers. in reconfiguration settings, when you enable the enab le channel and transmitter pll reconfiguration option, the following screens become available: modes tr a n sm i tt er p l l s clocking/interface the following sections describe these screens and their corresponding settings. modes screen for the reconfiguration settings figure 1?9 shows the mod es screen, listing the various dynamic reconfiguration modes available. figure 1?9. megawizard plug - in manager?reconfiguration settings chapter 1: altgx transceiver setup guide 1?29 reconfiguration settings ? november 2009 altera corporation stratix iv device handbook volume 3 ta b l e 1?7 describes the different options available in the mod es screen of the megawizard plug-in manager for your altgx custom megafunction variation. table 1?7. megawizard plug - in manager options (modes screen) (part 1 of 2) altgx setting description reference dynamic reconfiguration settings what do you want to be able to dynamically reconfigure in the transceiver? the different dynamic reconfiguration modes available are listed in the reconfiguration settings screen. based on which portion of the transceiver you want to reconfigure, select the corresponding options, and connect the altgx_reconfig instance to the altgx instance. analog controls (vod, pre-emphasis, and manual equalization and eyeq)?enable this option to dynamically reconfigure the pma control settings similar to vod, pre-emphasis, manual equalization, dc gain, and eyeq. enable adaptive equalizer control?selecting this option enables the adaptive equalization (aeq) hardware and provides the following additional ports: ? aeq_togxb[] ? aeq_fromgxb[] these ports provide the interface between the receiver channel and the dynamic reconfiguration controller. offset cancellation for receiver channels?this option is enabled by default for receiver only and receiver and transmitter configurations. it is not available for transmitter only configurations. ensure that you connect a dynamic reconfiguration controller to all the transceiver channels in the design. ?dynamic reconfiguration modes implementation? section in the stratix iv dynamic reconfiguration chapter . ?pma controls reconfiguration mode details? section in the stratix iv dynamic reconfiguration chapter . ? enabling the aeq control logic and aeq hardware? section in the stratix iv dynamic reconfiguration chapter. ?offset cancellation feature? section in the stratix iv dynamic reconfiguration chapter . 1?30 chapter 1: altgx transceiver setup guide reconfiguration settings stratix iv device handbook volume 3 ? november 2009 altera corporation enable channel and transmitter pll reconfiguration you must enable this option to reconfigure one of the following: transmitter local divider block, cmu pll, transceiver channel, or both the cmu pll and transceiver channel. channel interface?this option enables memory initialization file ( .mif )-based reconfiguration among functional modes that have different fpga fabric-transceiver interface signals. this option also allows channel interface reconfiguration. use alternate cmu transmitter pll?this option sets up the alternate pll so that the transceiver channel can optionally select between the output of the main and alternate transmitter pll. use additional cmu/atx transmitter plls from outside the transceiver block?this option allows you to select a maximum of four transmitter plls. for example, you can select the atx pll as the main pll and three additional plls. ? how many additional plls are used??you can have a maximum of two plls outside the transceiver block. ?transceiver channel reconfiguration modes details? section in the stratix iv dynamic reconfiguration chapter . ?fpga fabric-transceiver channel interface selection? section in the stratix iv dynamic reconfiguration chapter . ?transceiver channel reconfiguration modes details? section in the stratix iv dynamic reconfiguration chapter in volume 2 of the stratix iv device handbook. ?multi-pll settings? section in the stratix iv dynamic reconfiguration chapter. how many input clocks are used? enter the number of input clocks available for selection for the transmitter plls and receiver pll. you have a choice of up to 10 input clock sources (clock 1, clock 2, and so on). ?guidelines for specifying the input reference clocks? section in the stratix iv dynamic reconfiguration chapter. what is the starting channel number? you must set the starting channel number of the first altgx instance controlled by the dynamic reconfiguration controller to 0 . set the starting channel number of the consecutive altgx instances controlled by the same dynamic reconfiguration controller, if any, in the next available multiples of 4. ?logical channel addressing while reconfiguring the pma controls? section in the stratix iv dynamic reconfiguration chapter . table 1?7. megawizard plug - in manager options (modes screen) (part 2 of 2) altgx setting description reference chapter 1: altgx transceiver setup guide 1?31 reconfiguration settings ? november 2009 altera corporation stratix iv device handbook volume 3 transmitter pll settings depending on the number of additional plls you select in the how many additional plls are used? option in reconfiguration settings, the corresponding pll screens become available. each of these pll screens have the same settings available for selection. table 1?8 describes each of these settings in detail. 1 the main pll is the pll you configure in the general screen. therefore, some of the options are already enabled or disabled for this pll. some of the options differ when compared with the additional transmitter plls. figure 1?10 shows the options available on the ma in pll screen of the altgx megawizard plug-in manager. figure 1?10. megawizard plug - in manager options?main pll screen 1?32 chapter 1: altgx transceiver setup guide reconfiguration settings stratix iv device handbook volume 3 ? november 2009 altera corporation ta b l e 1?8 describes the available options on the ma in pll screen of the megawizard plug-in manager for your altgx custom megafunction variation. table 1?8. megawizard plug - in manager options (main pll screen) (part 1 of 3) altgx setting description reference main tx pll/rx pll settings use central clock divider to drive the transmitter channels using 4/n lines if this option is enabled, the transmitter pll is outside the transceiver block. if this option is disabled, the transmitter pll is one of the cmu plls within the same transceiver block. ?selecting the pll logical reference index for additional plls? and the ?multi-pll settings? sections in the stratix iv dynamic reconfiguration chapter. what is the pll logical reference index (used in reconfiguration)? the pll logical reference index is selected based on the location of the alternate pll. if the use central clock divider to drive the transmitter channels using 4/n lines option is unchecked this must be 0 or 1, otherwise this must be 2 or 3. ?selecting the pll logical reference index for additional plls? and ?selecting the logical reference index of the cmu pll? sections in the stratix iv dynamic reconfiguration chapter. what is the selected input clock source for the rx/tx plls? assign identification numbers to all input reference clocks that are used by the transmitter plls in their corresponding pll screens. you can set up a maximum of 10 input reference clocks and assign identification numbers from 1 to 10. ?guidelines for specifying the input reference clocks? section in the stratix iv dynamic reconfiguration chapter. what is the protocol to be reconfigured to? select the desired functional mode here, if you intend to dynamically reconfigure the transceiver channel to a different functional mode using the alternate transmitter pll. ?channel reconfiguration with transmitter pll select mode details? in the stratix iv dynamic reconfiguration chapter. what is the subprotocol to be reconfigured to? this option is not available for the basic , (oif) cei phy interface , serial rapidio , gige , and xaui functional modes. this option is available for the following protocols and subprotocols: protocol = pci express (pipe) ; subprotocols = gen 1 and gen 2 protocol = sdi ; subprotocols = 3g and hd protocol = sonet/sdh ; subprotocols = oc12, oc48, and oc96 ? chapter 1: altgx transceiver setup guide 1?33 reconfiguration settings ? november 2009 altera corporation stratix iv device handbook volume 3 what would you like to base the setting on? this option is available only for basic mode.you can select one of the following options for the alternate transmitter pll: input clock frequency ?selecting this option allows you to enter your input clock frequency. based on the value you enter, the altgx megawizard plug-in manager populates the data rate options in the what is the effective data rate? field. the altgx megawizard plug-in manager determines these data rate options depending on the available multiplier settings. data rate ?selecting this option allows you to enter the transceiver channel serial data rate. based on the value you enter, the altgx megawizard plug-in manager populates the input reference clock frequency options in the what is the input clock frequency? field. the altgx megawizard plug-in manager determines these input reference clock frequencies depending on the available multiplier settings. ? what is the data rate? these settings are to dynamically reconfigure the transceiver channel to listen to the alternate transmitter pll. if you select the data rate option in the what would you like to base the setting on? field, the altgx megawizard plug-in manager allows you to specify the effective serial data rate value in this field. if you select the input clock frequency option in the what would you like to base the setting on? field, the altgx megawizard plug-in manager displays the list of effective serial data rates in this field. ? what is the input clock frequency? these settings are to dynamically reconfigure the transceiver channel to listen to the alternate transmitter pll. if you select the input clock frequency option in the what would you like to base the setting on? field, the altgx megawizard plug-in manager displays the list of effective serial data rates in this field. if you select the data rate option in the what would you like to base the setting on? field, the altgx megawizard plug-in manager allows you to specify the effective serial data rate value in this field. ?cmu pll reconfiguration mode details? section in the stratix iv dynamic reconfiguration chapter. what is the pll bandwith mode? the available options are auto , low , medium , and high . select the appropriate option based on your system requirements. ?pll bandwidth setting? section in the stratix iv transceiver architecture chapter. create powerdown port to power down the pll. each transceiver block has two cmu plls. each cmu/atx pll has a dedicated power down signal called pll_powerdown . this signal powers down the cmu pll. ?user reset and power-down signals? section in the reset control and power down chapter. table 1?8. megawizard plug - in manager options (main pll screen) (part 2 of 3) altgx setting description reference 1?34 chapter 1: altgx transceiver setup guide reconfiguration settings stratix iv device handbook volume 3 ? november 2009 altera corporation clocking/interface screen for the reconfiguration settings figure 1?11 shows the cl ocking/interface screen of the altgx megawizard plug-in manager for the reconfiguration settings. create locked port to indicate that the pll is in lock with the reference clock. each cmu/atx pll has a dedicated pll_locked signal that is fed to the fpga fabric to indicate when the pll is locked to the input reference clock. ?user reset and power-down signals? section in the reset control and power down chapter. use auxiliary transmitter (atx) pll (available only if central clock divider is used) this option is only available for certain data rates. refer to datasheet for the supported data rates. this option enables the auxiliary transmitter pll. this is a low-jitter pll that resides between the transceiver blocks and can be used as a transmitter pll. ?auxiliary transmit (atx) pll block? section in the stratix iv transceiver architecture chapter and the stratix iv device datasheet section . table 1?8. megawizard plug - in manager options (main pll screen) (part 3 of 3) altgx setting description reference figure 1?11. megawizard plug - in manager options (clocking/interface screen) chapter 1: altgx transceiver setup guide 1?35 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 ta b l e 1?9 describes the available options on the cl ocking/interface screen of the megawizard plug-in manager for your altgx custom megafunction variation. 1 this screen is not available for basic (pma direct) 1 and xn configurations. protocol settings this section describes the various screens available to set up the pcs blocks of the stratix iv transceiver. 1 protocol settings are not available for basic (pma direct) functional mode. b ased on the protocol you select in the gen eral screen of parameter settings, the screens listed in ta b l e 1?10 become available. the following sections describe these screens and the available settings for each of them. table 1?9. megawizard plug - in manager options (clocking/interface screen) altgx setting description reference dynamic reconfiguration channel internal and interface settings how should the receivers be clocked? select one of the following available options: share a single transmitter core clock between receivers use the respective channel transmitter core clocks use the respective channel receiver core clocks ?clocking/interface options? section in the stratix iv dynamic reconfiguration chapter . how should the transmitters be clocked? select one of the following available options: share a single transmitter core clock between transmitters use the respective channel transmitter core clocks ?clocking/interface options? section in the stratix iv dynamic reconfiguration chapter . create an 'rx_revbitorderwa' input port to use receiver enable bit reversal this optional input port allows you to dynamically reverse the bit order at the output of the receiver word aligner. ?word aligner? section in the stratix iv transceiver architecture chapter . check a control box to use the corresponding control port. you can select various control and status signals depending on what protocol(s) you intend to dynamically reconfigure the transceiver channel to. ?fpga fabric-transceiver channel interface selection? section in the stratix iv dynamic reconfiguration chapter . table 1?10. protocol settings protocols protocol settings screens 8b/10b word aligner rate match/byte order basic (basic/8b10b) ? deterministic latency ( det. latency/8b10b) ? sdi ( sdi/8b10b) ? serial rapidio ( serial rapidio/8b10b) ? 1?36 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation 8b10b screen for the protocol settings figure 1?12 shows the 8b10b s creen of the megawizard plug-in manager for the protocol settings. ta b l e 1?11 describes the available options on the 8b10b s creen of the megawizard plug-in manager for your altgx custom megafunction variation. figure 1?12. megawizard plug - in manager?altgx (8b10b screen) table 1?11. megawizard plug- in manager options (8b10b screen) (part 1 of 3) altgx setting description reference enable low latency pcs mode. this option disables all the pcs blocks except the tx/rx phase comp fifo and optional byte serializer/de-serializer. ?low latency pcs datapath? section in the stratix iv transceiver architecture chapter . enable 8b/10b decoder/encoder. this option is available if the channel width is 8-bits, 16-bits, or 32-bits. ?8b/10b decoder? section in the stratix iv transceiver architecture chapter . create a tx_forcedisp to enable force disparity and use tx_dispval to code up the incoming word using positive or negative disparity. 8b/10b encoder force disparity control: when asserted high?forces the 8b/10b encoder to encode the data on the tx_datain port with a positive or negative disparity depending on the tx_dispval signal level. when de-asserted low?the 8b/10b encoder encodes the data on the tx_datain port according to the 8b/10b running disparity rules. ?8b/10b encoder? and ?transceiver port lists? sections in the stratix iv transceiver architecture chapter . chapter 1: altgx transceiver setup guide 1?37 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 create an rx_ctrldetect port to indicate 8b/10b decoder has detected a control code. this is an output status signal that the 8b/10b decoder forwards to the fpga fabric. this signal indicates whether the decoded 8-bit code group is a data or control code group on this port. if the received 10-bit code group is one of the 12 control code groups (/kx.y/) specified in the ieee802.3 specification, this signal is driven high. if the received 10-bit code group is a data code group (/dx.y/), this signal is driven low. the signal width is 1, 2, and 4 bits for a channel width of 8 bits, 16 bits, and 32 bits, respectively. ?8b/10b decoder? section in the stratix iv transceiver architecture chapter . create an rx_errdetect port to indicate 8b/10b decoder has detected an error code. this is an output status signal that the 8b/10b decoder forwards to the fpga fabric, and indicates an 8b/10b code group violation. this signal is asserted high if the received 10-bit code group has a code violation or disparity error. it is used along with the rx_disperr signal to differentiate between a code violation error and/or a disparity error. the signal width is 1, 2 and 4 bits for a channel width of 8 bits, 16 bits, and 32 bits, respectively. ?8b/10b decoder? section in the stratix iv transceiver architecture chapter . create an rx_disperr port to indicate 8b/10b decoder has detected a disparity error. this is an output status signal that the 8b/10b decoder forwards to the fpga fabric. this signal is asserted high if the received 10-bit code or data group has a disparity error. when this signal goes high, rx_errdetect is also asserted high. the signal width is 1, 2, and 4 bits for a channel width of 8 bits, 16 bits, and 32 bits, respectively. ?8b/10b decoder? section in the stratix iv transceiver architecture chapter . create an rx_runningdisp port to indicate the current running disparity of the 8b10b decoded byte. this is an output status signal that the 8b/10b decoder forwards to the fpga fabric to indicate the current running disparity of the 8b/10b decoded byte. ?8b/10b decoder? section of table 1-77 in the stratix iv transceiver architecture chapter . flip receiver output data bits. this option reverses the bit order of the parallel receiver data at a byte level at the output of the receiver phase compensation fifo. for example, if the 16-bit parallel receiver data at the output of the receiver phase compensation fifo is '10111100 10101101' (16'hbcad), enabling this option reverses the data on rx_dataout port to '00111101 10110101' (16'h3db5). ? flip transmitter input data bits. this option reverses the bit order of the parallel transmitter data at a byte level at the input of the transmitter phase compensation fifo. for example, if the 16-bit parallel transmitter data at the tx_datain port is '10111100 10101101' (16'hbcad), enabling this option reverses the input data to the transmitter phase compensation fifo to '00111101 10110101' (16'h3db5). ? table 1?11. megawizard plug- in manager options (8b10b screen) (part 2 of 3) altgx setting description reference 1?38 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation enable transmitter bit reversal. enabling this option in: single-width mode?the 8-bit d[7:0] or 10-bit d[9:0] data at the input of the serializer gets rewired to d[0:7] or d[0:9] , respectively. double-width mode?the 16-bit d[15:0] or 20-bit d[19:0] data at the input of the serializer gets rewired to d[0:15 ] or d[0:19] , respectively. for example, if the 8-bit parallel data at the input of the serializer is '00111101', enabling this option reverses this serializer input data to '10111100.' ?transmitter bit reversal? section in the stratix iv transceiver architecture chapter . create a tx_invpolarity port to allow transmitter polarity inversion. this optional port allows you to dynamically reverse the polarity of every bit of the data word fed to the serializer in the transmitter data path. use this option when the positive and negative signals of the differential output from the transmitter ( tx_dataout ) are erroneously swapped on the board. ?transmitter polarity inversion? section in the stratix iv transceiver architecture chapter . create tx_bitslipboundary select port to control the number of words slipped in the tx bitslipper. you can only select this option when you use the transmitter only or receiver and transmitter operation mode. this option enables the tx_bitslipboundaryselect input to control the number of bits slipped in the tx bitslipper. ? table 1?11. megawizard plug- in manager options (8b10b screen) (part 3 of 3) altgx setting description reference chapter 1: altgx transceiver setup guide 1?39 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 word aligner screen for the protocol settings figure 1?13 shows the wor d a l ign e r screen of the megawizard plug-in manager for the protocol settings. figure 1?13. megawizard plug - in manager?altgx (word aligner screen) 1?40 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation ta b l e 1?12 describes the available options on the wo rd aligner screen of the megawizard plug-in manager for your altgx custom megafunction variation. 1 the word aligner and rate matcher operations and patterns are pre-configured for pci e xpress (pipe), gige, and xaui modes, and cannot be altered. table 1?12. megawizard plug- in manager options (word aligner screen) (part 1 of 4) altgx setting description reference use manual word alignment mode. enabling this option sets the word aligner in manual alignment mode. in manual alignment mode, the word aligner operation is controlled by the input signal rx_enapatternalign . ?manual alignment mode word aligner with 8-bit pma-pcs interface modes? and ?manual alignment mode word aligner with 10-bit pma-pcs interface modes? sections in the stratix iv transceiver architecture chapter . when should the word aligner realign? two options are available in manual mode: realign continuously while the rx_enapatternalign signal is high. realign at the rising edge of the rx_enapatternalign signal. ?manual alignment mode word aligner with 8-bit pma-pcs interface modes? and ?manual alignment mode word aligner with 10-bit pma-pcs interface modes? sections in the stratix iv transceiver architecture chapter . use manual bitslipping mode. this option sets the word aligner in bit-slip mode. enabling this option creates an input signal rx_bitslip to control the word aligner. at every rising edge of the rx_bitslip signal, the bit slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. sdi because word alignment and framing occur after de-scrambling, the word aligner in the receiver data path is not useful in sdi systems. altera recommends driving the altgx rx_bitslip signal low to prevent the word aligner from inserting bits in the received data stream. ?word aligner? section in the stratix iv transceiver architecture chapter . use the automatic synchronization state machine mode. this option sets the word aligner in automatic synchronization state machine mode. this mode is available only in single-width mode for 8b/10b encoded data: 10-bit pcs-pma interface where the 8b/10b encoder is enabled or 10-bit pcs-pma interface where the 8b/10b is disabled but the data is already 8b/10b encoded ?automatic synchronization state machine mode word aligner with 10-bit pma-pcs interface mode? section in the stratix iv transceiver architecture chapter . number of continuous valid code groups received to reduce the error count by 1. use this option in automatic synchronization state machine mode to indicate the number of continuous valid code groups that it must receive between erroneous code groups to reduce the error count by one. the rx_syncstatus stays high as long as the error count is less than the programmed error count. ?automatic synchronization state machine mode word aligner with 10-bit pma-pcs interface mode? section in the stratix iv transceiver architecture chapter . chapter 1: altgx transceiver setup guide 1?41 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 number of erroneous code groups (error count) received to lose synchronization. use this option in automatic synchronization state machine mode to indicate the number of erroneous code groups (error count) that it must receive to lose synchronization. the loss-of-synch is indicated by the rx_syncstatus signal going low. ?automatic synchronization state machine mode word aligner with 10-bit pma-pcs interface mode? section in the stratix iv transceiver architecture chapter . number of valid code groups received to achieve synchronization. use this option in automatic synchronization state machine mode to indicate the number of word alignment patterns that it must receive without intermediate erroneous code groups to achieve synchronization. the rx_syncstatus signal is driven high to indicate that synchronization has been achieved. ?automatic synchronization state machine mode word aligner with 10-bit pma-pcs interface mode? section in the stratix iv transceiver architecture chapter . what is the word alignment pattern length? this option sets the word alignment pattern length. the available choices depend on the following conditions: whether the data is 8b/10b encoded or not which mode is used in single-width mode: ? for 8-bit pcs-pma interface (8b/10b encoder disabled), only 16 bits are allowed. ? for 10-bit pcs-pma, 7 and 10 bits are allowed. which mode is used in double-width mode: ? for 16-bit pcs-pma interface (8b/10b encoder disabled), 8, 16, and 32 bits are allowed. ? for 20-bit pcs-pma interface, 7, 10, and 20 bits are allowed. ?word aligner in single-width mode? and ?word aligner in double-width mode? sections in the stratix iv transceiver architecture chapter . what is the word alignment pattern? enter the word alignment pattern in msb to lsb order with msb at the left most bit position. the length of the alignment pattern is based on the what is the word alignment pattern length? option. the word aligner restores the word boundary by looking for the pattern that you enter here. for example, if you want to set the word alignment pattern to /k28.5/: you must enter the word alignment pattern length: 10 . you must enter the word alignment pattern: 0101111100 (17c). ?word aligner in single-width mode? and ?word aligner in double-width mode? sections in the stratix iv transceiver architecture chapter . flip word alignment pattern bits. when this option is enabled, the altgx megawizard plug-in manager flips the bit order of the pattern that you enter in the what is the word alignment pattern? option and uses the flipped version as the word alignment pattern. for example, if you enter '0101111100' (17c) as the word alignment pattern and enable this option, the word aligner uses '0011111010' as the word alignment pattern. ? table 1?12. megawizard plug- in manager options (word aligner screen) (part 2 of 4) altgx setting description reference 1?42 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation enable run-length violation checking with a run length of: this option creates the output signal rx_rlv . enabling this option also activates the run-length violation circuit. if the number of continuous 1s and 0s exceeds the number that you set in this option, the run-length violation circuit asserts the rx_rlv signal. the rx_rlv signal is asynchronous to the receiver data path and is asserted for a minimum of two recovered clock cycles in single-width mode. similarly, it is asserted for a minimum of three recovered clock cycles in double-width mode. the run length limits are as follows: single-width mode: ? 8-bit and 16-bit channel width: 4 to 128 in increments of four ? 10-bit and 20-bit channel width: 5 to 160 in increments of five double-width mode: ? 16-bit and 32-bit channel width: 8 to 512 in increments of eight ? 20-bit and 40-bit channel width: 10 to 640 in increments of 10 ?programmable run length violation detection? section in the stratix iv transceiver architecture chapter . enable word aligner output reverse bit ordering. in manual bit-slip mode, this option creates an input port rx_revbitorderwa to dynamically reverse the bit order at the output of the receiver word aligner. ?receiver bit reversal? section in the stratix iv transceiver architecture chapter . create an rx_syncstatus output port for pattern detector and word aligner. this is an output status signal that the word aligner forwards to the fpga fabric to indicate that synchronization has been achieved. this signal is synchronous with the parallel receiver data on the rx_dataout port. this signal is not available in bit-slip mode. signal width is 1, 2, and 4 bits for a channel width of 8-bits/10-bits, 16-bits/20-bits, and 32-bits/40-bits, respectively. table 1-77, ?word aligner in single-width mode? and ?word aligner in double-width mode? sections in the stratix iv transceiver architecture chapter . create an rx_patterndetect port to indicate pattern detected. this is an output status signal that the word aligner forwards to the fpga fabric to indicate that the word alignment pattern programmed has been detected in the current word boundary. signal width is 1, 2, and 4 bits for a channel width of 8-bits/10-bits, 16-bits/20-bits, and 32-bits/40-bits, respectively. table 1-77 and ?word aligner in single-width mode? and ?word aligner in double-width mode? sections in the stratix iv transceiver architecture chapter . create an rx_invpolarity port to enable word aligner polarity inversion. this optional port allows you to dynamically reverse the polarity of every bit of the received data at the input of the word aligner. use this option when the positive and negative signals of the differential input to the receiver ( rx_datain ) are erroneously swapped on the board. ?receiver polarity inversion? section in the stratix iv transceiver architecture chapter . table 1?12. megawizard plug- in manager options (word aligner screen) (part 3 of 4) altgx setting description reference chapter 1: altgx transceiver setup guide 1?43 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 create an rx_revbyteorderwa to enable receiver symbol swap. this is an optional input port that is available only in the double-width mode. it creates an rx_revbyteorderwa port to dynamically swap the msbyte and lsbyte of the data at the output of the word aligner in the receiver data path. enabling this option compensates for the erroneous swapping of bytes at the upstream transmitter and corrects the data received by the downstream systems. for example, if the 16-bit output of the word aligner is 0b0a, asserting the rx_revbyteorderwa signal swaps the two bytes so the output becomes 0a0b. ?receiver byte reversal in basic double-width modes? section in the stratix iv transceiver architecture chapter . create rx_bitslipboundaryse lectout port to indicate the number of bits slipped in the word aligner. this option is available for selection only when you are in receiver only or receiver and transmitter operation mode. this option enables the rx_bitslipboundaryselectout output to indicate the number of bits slipped in the word aligner. ? table 1?12. megawizard plug- in manager options (word aligner screen) (part 4 of 4) altgx setting description reference 1?44 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation rate match/byte order screen for the protocol settings figure 1?14 shows the ra te match/byte order screen of the megawizard plug-in manager for the protocol settings. figure 1?14. megawizard plug - in manager?altgx (rate match/byte order screen) chapter 1: altgx transceiver setup guide 1?45 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 ta b l e 1?13 describes the available options on the ra te match/byte order screen of the megawizard plug-in manager for your altgx custom megafunction variation. table 1?13. megawizard plug- in manager options (rate match/byte order screen) (part 1 of 3) altgx setting description reference enable rate match fifo. this option enables the rate match (clock rate compensation) fifo. the rate match block consists of a 20-word deep fifo. depending on the ppm difference, the rate match fifo controls insertion and deletion of skip characters based on the 20-bit rate match pattern you enter in the what is the 20 - bit rate match pattern1? and what is the 20 - bit rate match pattern2? options. to enable this block: the transceiver channel must have both the transmitter and the receiver channels instantiated. you must select the receiver and transmitter option in the what is the operation mode? field in the general screen. you must also enable the 8b/10b encoder/decoder in the 8b10b screen. the rate match block is capable of compensating up to 300 ppm difference between the upstream transmitter clock and the local receiver?s input reference clock. ?rate match fifo in basic single-width mode? and ?rate match fifo in basic double-width mode? sections in the stratix iv transceiver architecture chapter . what is the 20-bit rate match pattern1? (usually used for +ve disparity pattern) enter a 10-bit skip pattern and a 10-bit control pattern. in the skip pattern field, you must choose a 10-bit code group that has neutral disparity. when the rate matcher receives the 10-bit control pattern followed by the 10-bit skip pattern, it inserts or deletes the 10-bit skip pattern as necessary to avoid rate match fifo overflow or underflow conditions. (1) ?rate match fifo in basic single-width mode? and ?rate match fifo in basic double-width mode? sections in the stratix iv transceiver architecture chapter . what is the 20-bit rate match pattern2? (usually used for -ve disparity pattern) enter a 10-bit skip pattern and a 10-bit control pattern. in the skip pattern field, you must choose a 10-bit code group that has neutral disparity. when the rate matcher receives the 10-bit control pattern followed by the 10-bit skip pattern, it inserts or deletes the 10-bit skip pattern as necessary to avoid rate match fifo overflow or underflow conditions. (1) ?rate match fifo in basic single-width mode? and ?rate match fifo in basic double-width mode? sections in the stratix iv transceiver architecture chapter . create the rx_rmfifofull port to indicate when the rate match fifo is full. this option creates the output port rx_rmfifofull when you enable the enable rate match fifo option. it is a status flag that the rate match block forwards to the fpga fabric. it indicates when the rate match fifo block is full (20 words). this signal remains high as long as the fifo is full. it is asynchronous to the receiver data path. ?rate match fifo in basic single-width mode? and ?rate match fifo in basic double-width mode? sections in the stratix iv transceiver architecture chapter . 1?46 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation create the rx_rmfifoempty port to indicate when the rate match fifo is empty. this option creates the output port rx_rmfifoempty when you enable the enable rate match fifo option. it is a status flag that the rate match block forwards to the fpga fabric. it indicates when the rate match fifo block is empty (5 words full). this signal remains high as long as the fifo is empty. it is asynchronous to the receiver data path. ?rate match fifo in basic single-width mode? and ?rate match fifo in basic double-width mode? sections in the stratix iv transceiver architecture chapter . create the rx_rmfifodatainserted port to indicate when data is inserted in the rate match fifo. this option creates the output port rx_rmfifodatainserted flag when you enable the enable rate match fifo option. it is a status flag that the rate match block forwards to the fpga fabric. this indicates the insertion of skip patterns. for every deletion, this signal is high for one parallel clock cycle. ?rate match fifo in basic single-width mode? and ?rate match fifo in basic double-width mode? sections in the stratix iv transceiver architecture chapter . create the rx_rmfifodatadeleted port to indicate when data is deleted in the rate match fifo. this option creates the output port rx_rmfifodatadeleted flag when you enable the enable rate match fifo option. it is a status flag that the rate match block forwards to the fpga fabric. this indicates the deletion of skip patterns. for every insertion, this signal is high for one parallel clock cycle. ?rate match fifo in basic single-width mode? and ?rate match fifo in basic double-width mode? sections in the stratix iv transceiver architecture chapter . enable insertion or deletion of consecutive characters or ordered sets this option enables the back-to-back insertion or deletion of skip characters in the rate match fifo. this option is available for selection in single-width mode. it is enabled by default in double-width mode. ? enable byte ordering block. this option enables the byte ordering block. it is available in both single-width and double-width modes. it is available only when the channel width is: 16-bits/20-bits in single-width mode 32-bits/40-bits in double-width mode as soon as the byte ordering block sees the rising edge of the appropriate signal, it compares the lsbyte coming out of the byte deserializer with the byte ordering pattern. if they do not match, the byte ordering block inserts the pad character that you enter in the what is the byte ordering pad pattern? option such that the byte ordering pattern is seen in the lsbyte position. inserting this pad character enables the byte ordering block to restore the correct byte order. ?byte ordering block? section in the stratix iv transceiver architecture chapter . what do you want the byte ordering to be based on? this option is available only when the byte ordering block is enabled. this option allows you to trigger the byte ordering block on the rising edge of either the rx_syncstatus signal or the user-controlled rx_enabyteord signal from the fpga fabric. ?byte ordering block? section in the stratix iv transceiver architecture chapter . what is the byte ordering pattern? this option is available only when the byte ordering block is enabled. enter the 10-bit pattern that the byte ordering block must place in the lsbyte position of the receiver parallel data on the rx_dataout port. ?byte ordering block? section in the stratix iv transceiver architecture chapter . table 1?13. megawizard plug- in manager options (rate match/byte order screen) (part 2 of 3) altgx setting description reference chapter 1: altgx transceiver setup guide 1?47 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 protocol settings screen for gige and xaui figure 1?15 shows the protocol settings screen for the gig e and xaui modes of the megawizard plug-in manager. what is the byte ordering pad pattern? when the byte ordering block does not find the byte ordering pattern in the lsbyte position of the data coming out of the byte deseriazlier, it inserts this byte ordering pad pattern such that the byte ordering pattern is seen in the lsbyte position of the receiver parallel data on the rx_dataout port. inserting this pad character enables the byte ordering block to restore the correct byte order. ?byte ordering block? section in the stratix iv transceiver architecture chapter . note to table 1?13 : (1) if you want the rate matcher to insert or delete both the positive and negative disparities of the 20-bit rate matching patt ern, enter the positive disparity as pattern1 and negative disparity as pattern2. table 1?13. megawizard plug- in manager options (rate match/byte order screen) (part 3 of 3) altgx setting description reference figure 1?15. megawizard plug - in manager?altgx (protocol settings screen?gige and xaui) 1?48 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation ta b l e 1?14 describes the available options for the gige an d xaui modes in the protocol settings screen of the megawizard plug-in manager for your altgx custom me gafunction variation. table 1?14. megawizard plug- in manager options (protocol settings ?gige and xaui) (part 1 of 3) altgx setting description reference enable run-length violation checking with a run length of __. this option creates the output signal rx_rlv . enabling this option also activates the run-length violation circuit. if the number of continuous 1s and 0s exceeds the number that you set in this option, the run-length violation circuit asserts the rx_rlv signal. the rx_rlv signal is asynchronous to the receiver data path and is asserted for a minimum of two recovered clock cycles. the run length limits are 5 to 160 in increments of five. ?programmable run length violation detection? section in the stratix iv transceiver architecture chapter . create an rx_syncstatus output port for pattern detector and word aligner. this is an output status signal that the word aligner forwards to the fpga fabric to indicate that synchronization has been achieved. this signal is synchronous with the parallel receiver data on the rx_dataout port. receiver synchronization is indicated on the rx_syncstatus port of each channel. table 1-33 and the ?word aligner? section in the stratix iv transceiver architecture chapter . create an rx_patterndetect port to indicate pattern detected. this is an output status signal that the word aligner forwards to the fpga fabric to indicate that the word alignment pattern programmed has been detected in the current word boundary. table 1-33 and the ?word aligner? section in the stratix iv transceiver architecture chapter . create an rx_invpolarity port to enable word aligner polarity inversion. this optional port allows you to dynamically reverse the polarity of every bit of the received data at the input of the word aligner. use this option when the positive and negative signals of the differential input to the receiver ( rx_datain ) are erroneously swapped on the board. ?receiver polarity inversion? section in the stratix iv transceiver architecture chapter . create an rx_ctrldetect port to indicate 8b/10b decoder has detected a control code. this is an output status signal that the 8b/10b decoder forwards to the fpga fabric. this signal indicates whether the decoded 8-bit code group is a data or control code group on this port. if the received 10-bit code group is one of the 12 control code groups (/kx.y/) specified in ieee802.3 specification, this signal is driven high. if the received 10-bit code group is a data code group (/dx.y/), this signal is driven low. ?8b/10b decoder? section in the stratix iv transceiver architecture chapter . create an rx_errdetect port to indicate 8b/10b decoder has detected an error code. this is an output status signal that the 8b/10b decoder forwards to the fpga fabric. this signal indicates an 8b/10b code group violation. it is asserted high if the received 10-bit code group has a code violation or disparity error. it is used along with the rx_disperr signal to differentiate between a code violation error and/or a disparity error. ?8b/10b decoder? section in the stratix iv transceiver architecture chapter . chapter 1: altgx transceiver setup guide 1?49 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 create an rx_disperr port to indicate 8b/10b decoder has detected a disparity error. this is an output status signal that the 8b/10b decoder forwards to the fpga fabric.this signal is asserted high if the received 10-bit code or data group has a disparity error. when this signal goes high, rx_errdetect also is asserted high. ?8b/10b decoder? section in the stratix iv transceiver architecture chapter . create a tx_invpolarity port to allow transmitter polarity inversion. this optional port allows you to dynamically reverse the polarity of every bit of the data word fed to the serializer in the transmitter data path. use this option when the positive and negative signals of the differential output from the transmitter ( tx_dataout ) are erroneously swapped on the board. ?transmitter polarity inversion? section in the stratix iv transceiver architecture chapter . create an rx_runningdisp port to indicate the current running disparity of the 8b/10b decoded byte. this is an output status signal that the 8b/10b decoder forwards to the fpga fabric. this signal is asserted high when the current running disparity of the 8b/10b decoded byte is negative. this signal is low when the current running disparity of the 8b/10b decoded byte is positive. ? create an rx_rmfifofull port to indicate when the rate match fifo is full. this option creates the output port rx_rmfifofull . it is a status flag that the rate match block forwards to the fpga fabric. this indicates when the rate match fifo block is full (20 words). this signal remains high as long as the fifo is full and is asynchronous to the receiver data path. ?rate match (clock rate compensation) fifo? section in the stratix iv transceiver architecture chapter . create an rx_rmfifoempty port to indicate when the rate match fifo is empty. this option creates the output port rx_rmfifoempty . it is a status flag that the rate match block forwards to the fpga fabric. this indicates when the rate match fifo block is empty (5 words). this signal remains high as long as the fifo is empty and is asynchronous to the receiver data path. ?rate match (clock rate compensation) fifo? section in the stratix iv transceiver architecture chapter . create an rx_rmfifodatainserted port to indicate when data is inserted in the rate match fifo. this option creates the output port rx_rmfifodatainserted flag. it is a status flag that the rate match block forwards to the fpga fabric. the rx_rmfifodatainserted flag is asserted when a rate match pattern byte is inserted to compensate for the ppm difference in reference clock frequencies between the upstream transmitter and the local receiver. ?rate match (clock rate compensation) fifo? section in the stratix iv transceiver architecture chapter . create an rx_rmfifodatadeleted port to indicate when data is deleted in the rate match fifo. this option creates the output port rx_rmfifodatadeleted . it is a status flag that the rate match block forwards to the fpga fabric. the rx_rmfifodatadeleted flag is asserted when a rate match pattern byte is inserted to compensate for the ppm difference in reference clock frequencies between the upstream transmitter and the local receiver. ?rate match (clock rate compensation) fifo? section in the stratix iv transceiver architecture chapter . table 1?14. megawizard plug- in manager options (protocol settings ?gige and xaui) (part 2 of 3) altgx setting description reference 1?50 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation protocol settings screen for the (oif) cei phy interface ta b l e 1?15 describes the available options for the (oif ) cei phy interface mode in the protocol settings screen of the megawizard plug-in manager for your altgx custom me gafunction variation. enable transmitter bit reversal. enabling this option reverses every bit of the 10-bit parallel data at the input of the serializer. the 10-bit input to the serializer d[9:0] is reversed to d[0:9] . ?8b/10b encoder? section in the stratix iv transceiver architecture chapter . what is the word alignment pattern length? this option sets the word alignment pattern length. the available choices are 7 and 10 for the gige and xaui modes. the default setting for this option is 10 . ?rate match (clock rate compensation) fifo? section in the stratix iv transceiver architecture chapter . table 1?14. megawizard plug- in manager options (protocol settings ?gige and xaui) (part 3 of 3) altgx setting description reference table 1?15. megawizard plug - in manager options (protocol settings - [oif] cei phy interface) altgx setting description reference enable run-length violation checking with a run length of __. this option creates the output signal rx_rlv . enabling this option also activates the run-length violation circuit. if the number of continuous 1s and 0s exceeds the number that you set in this option, the run-length violation circuit asserts the rx_rlv signal. the rx_rlv signal is asynchronous to the receiver data path and is asserted for a minimum of two recovered clock cycles. for a 32-bit channel width, the run length limits are 8 to 512 in increments of eight. ?programmable run length violation detection? section in the stratix iv transceiver architecture chapter. chapter 1: altgx transceiver setup guide 1?51 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 protocol settings screen for pci express (pipe) figure 1?16 shows the pci express (pipe) 1 screen for protocol settings of the megawizard plug-in manager. figure 1?16. megawizard plug - in manager?altgx (pci express [pipe] 1 screen) 1?52 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation ta b l e 1?16 describes the available options on the pci express (pipe) 1 screen of the megawizard plug-in manager for your altgx custom megafunction variation. table 1?16. megawizard plug- in manager options (pci express [pipe] 1) (part 1 of 3) altgx setting description reference enable low latency synchronous pci express (pipe). this option puts the rate match fifo into low latency mode, which forces the system into a 0 ppm mode. ensure that there is a 0 ppm difference between the upstream transmitter?s and the local receiver?s input reference clocks. ?rate match (clock rate compensation) fifo? section in the stratix iv transceiver architecture chapter . enable run-length violation checking with a run length of __. this option creates the output signal rx_rlv . enabling this option also activates the run-length violation circuit. if the number of continuous 1s and 0s exceeds the number that you set in this option, the run-length violation circuit asserts the rx_rlv signal. the rx_rlv signal is asynchronous to the receiver data path. for both 8-bit and 16-bit channel widths, the run length limits are 5 to 160 in increments of five. ?programmable run length violation detection? section in the stratix iv transceiver architecture chapter . enable fast recovery mode. this option enables the cdr control block. when this block is enabled, the rx_locktodata and rx_locktorefclk signals are disabled. ?fast recovery mode? section in the stratix iv transceiver architecture chapter . enable electrical idle inference functionality. enable the electrical idle inference module by selecting this option. in pci express (pipe) mode, the pcs has an optional electrical idle inference module designed to implement the electrical idle inference conditions specified in pci express (pipe) base specification 2.0. enabling this option creates the rx_elecidleinfersel[2:0] input signal. the electrical idle inference module infers electrical idle depending on the logic level driven on rx_elecidleinfersel[2:0] input signal. for the electrical idle inference module to correctly infer an electrical idle condition in each ltssm sub-state, you must drive the rx_elecidleinfersel[2:0] signal appropriately. ?electrical idle inference? section in the stratix iv transceiver architecture chapter . create an rx_syncstatus output port for pattern detector and word aligner. the altgx megawizard plug-in manager automatically configures the word aligner in automatic synchronization state machine mode for pci express (pipe) mode. this is an output status signal that the word aligner forwards to the fpga fabric to indicate that synchronization has been achieved. this signal is synchronous with the parallel receiver data on the rx_dataout port. the signal width is 1 and 2 bits for a channel width of 8 bits and 16 bits, respectively. table 1-29 and ?automatic synchronization state machine mode word aligner with 10-bit pma-pcs interface mode? section in the stratix iv transceiver architecture chapter . chapter 1: altgx transceiver setup guide 1?53 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 create an rx_patterndetect output port to indicate pattern detected. this is an output status signal that the word aligner forwards to the fpga fabric to indicate that the word alignment pattern programmed has been detected in the current word boundary. the signal width is 1 and 2 bits for a channel width of 8 bits and 16 bits, respectively. ?automatic synchronization state machine mode word aligner with 10-bit pma-pcs interface mode? section in the stratix iv transceiver architecture chapter . create an rx_ctrldetect port to indicate 8b/10b decoder has detected a control code. this is an output status signal that the 8b/10b decoder forwards to the fpga fabric. this signal indicates whether the decoded 8-bit code group is a data or control code group on this port. if the received 10-bit code group is one of the 12 control code groups (/kx.y/) specified in the ieee802.3 specification, this signal is driven high. if the received 10-bit code group is a data code group (/dx.y/), this signal is driven low. the signal width is 1 and 2 bits for a channel width of 8 bits and 16 bits, respectively. ?8b/10b decoder? section in the stratix iv transceiver architecture chapter . create a tx_detectrxloop input port as receiver detect or loopback enable, depending on the power state. depending on the power-down mode, asserting this signal enables either the receiver detect operation or loopback mode . (1) ?receiver detection? and ?pci express (pipe) reverse parallel loopback? section in the stratix iv transceiver architecture chapter . create a tx_forceelecidle input port to force the transmitter to send electrical idle signals. enabling this port sets the transmitter buffer in electrical idle mode. this port is available in all pci express (pipe) power-down modes and has a specific use in each mode. (1) ?transmitter buffer electrical idle? section in the stratix iv transceiver architecture chapter . create a tx_forcedispcompliance input port to force negative running disparity. a high level on this port forces the associated parallel transmitter data on the tx_datain port to be transmitted with negative current running disparity. for 8-bit transceiver channel width configurations, you must drive tx_forcedispcompliance[1:0] high in the same parallel clock cycle as the first /k28.5/ of the compliance pattern on the tx_datain port. for 16-bit transceiver channel width configurations, you must drive only the lsb of tx_forcedispcompliance[1:0] high in the same parallel clock cycle as /k28.5/d21.5/ of the compliance pattern on the tx_datain port. ?compliance pattern transmission support? section in the stratix iv transceiver architecture chapter . table 1?16. megawizard plug- in manager options (pci express [pipe] 1) (part 2 of 3) altgx setting description reference 1?54 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation figure 1?17 shows the pci express (pipe) 2 screen of protocol settings for the megawizard plug-in manager. create a tx_invpolarity port to allow transmitter polarity inversion. this optional port allows you to dynamically reverse the polarity of every bit of the data word fed to the serializer in the transmitter data path. use this option when the positive and negative signals of the differential output from the transmitter ( tx_dataout ) are erroneously swapped on the board. ?transmitter polarity inversion? section in the stratix iv transceiver architecture chapter . note to table 1?16 : (1) refer to the table ' power states and functions allowed in each power state ' in the pipe interface section in the stratix iv transceiver architecture chapter in volume 2 of the stratix iv device handbook . table 1?16. megawizard plug- in manager options (pci express [pipe] 1) (part 3 of 3) altgx setting description reference figure 1?17. megawizard plug - in manager?altgx (pci express [pipe] 2 screen) chapter 1: altgx transceiver setup guide 1?55 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 ta b l e 1?17 describes the available options on the pci express (pipe) 2 screen of the megawizard plug-in manager for your altgx custom megafunction variation. table 1?17. megawizard plug- in manager options (pci express [pipe] 2 screen) (part 1 of 2) altgx setting description reference create a pipestatus output port for pipe interface status signal. the pci express (pipe) interface block receives status signals from the transceiver channel pcs and pma blocks and encodes the status on a 3-bit output signal ( pipestatus[2:0] ) that is forwarded to the fpga fabric. the encoding of the status signals on pipestatus[2:0] is compliant to the pci express (pipe) v2.00 specification: 3'b000?received data ok 3'b001?one skp symbol added 3'b010?one skp symbol deleted 3'b011?receiver detected 3'b100?8b/10b decode error 3'b101?elastic buffer (rate match fifo) overflow 3'b110?elastic buffer (rate match fifo) underflow 3'b111?received disparity error ?receiver status? section and table 1-53 in the stratix iv transceiver architecture chapter . create a pipedatavalid output port to indicate valid data from the receiver. this is an output status port that indicates the receiver parallel data on the rx_dataout port is valid. ? create a pipeelecidle output port for electrical idle detect status signal. enabling this option creates the pipeelecidle output status port that is forwarded to the fpga fabric. if you select enable electrical idle inference module, the pipeelecidle signal is driven high when the electrical idle inference module infers an electrical idle condition depending on the logic driven on the rx_elecidleinfersel[2:0] port. otherwise, it is driven low. if you do not select enable electrical idle inference module , the rx_signaldetect output signal from the signal threshold detection circuitry is inverted and driven on the pipeelecidle port. the pipeelecidle signal is asynchronous to the receiver data path. ?electrical idle inference? section in the stratix iv transceiver architecture chapter . create a pipephydonestatus output port to indicate pipe completed power state transitions. this is an output status signal forwarded to the fpga fabric. the completion of various phy functions; for example, receiver detection, power state transition, clock switch, and rate switch, are indicated on this pipephydonestatus signal by driving this signal high for one parallel clock cycle. ?pci express (pipe) mode? section in the stratix iv transceiver architecture chapter . 1?56 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation create a pipe8b10binvpolarity port to enable polarity inversion in pipe. this optional port allows you to dynamically reverse every bit of the received data at the input of the 8b/10b decoder. ?pci express (pipe) mode? section in the stratix iv transceiver architecture chapter . create a powerdn input port for pipe powerdown directive. enabling this option creates an input control port powerdn[1:0] for each transceiver channel. depending on the logic levels driven on this port, the pci express (pipe) interface block drives the transceiver channel into one of the following power states: 2'b00?p0 (normal operation) 2'b01?p0s (low recovery time power saving 2'b10?p1 (high recovery time power saving) 2'b11?p2 (lowest power saving state) ?power state management? section and table 1-51 in the stratix iv transceiver architecture chapter . table 1?17. megawizard plug- in manager options (pci express [pipe] 2 screen) (part 2 of 2) altgx setting description reference chapter 1: altgx transceiver setup guide 1?57 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 protocol settings screen for sonet/sdh figure 1?18 shows the son et/sdh screen for protocol settings of the megawizard plug-in manager. figure 1?18. megawizard plug - in manager?altgx (protocol settings?sonet/sdh) 1?58 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation ta b l e 1?18 describes the available options on the sone t/sdh screen for protocol settings of the megawizard plug-in manager for your altgx custom megafunction var iation. table 1?18. megawizard plug- in manager options (sonet/sdh screen) (part 1 of 3) altgx setting description reference when should the word aligner realign? this option is not available in sonet/sdh mode. in sonet/sdh mode, the word aligner operates in manual alignment mode. by default, the altgx megawizard plug-in manager sets the behavior of the word aligner such that re-alignment occurs when there is a rising edge of the rx_enapatternalign input signal in this mode. ?word aligner? section in the stratix iv transceiver architecture chapter . what is the word alignment pattern length? this option sets the length of the word alignment pattern. the following options are available: oc-12 ?only 16-bit pattern is allowed. oc-48 ?only 16-bit pattern is allowed. oc-96 ?16-bit and 32-bit patterns are allowed. ?sonet/sdh mode? (oc-12, oc-48, and oc-96) section in the stratix iv transceiver architecture chapter . what is the word alignment pattern? enter the word alignment pattern. by default, the pattern that appears in the megawizard plug-in manager is '0001010001101111' (16'h146f). ?sonet/sdh mode? (oc-12, oc-48, and oc-96) section in the stratix iv transceiver architecture chapter . flip word alignment pattern bits. this option is enabled in the megawizard plug-in manager by default. this option reverses the order of the alignment pattern at a bit level to support msb-to-lsb transmission in sonet/sdh mode. the altgx megawizard plug-in manager flips the bit order of the default word alignment pattern '0001010001101111 '(16'h146f) and uses the flipped version '1111011000101000' (16'hf628) as the word alignment pattern. ? what do you want the byte ordering to be based on? this option allows you to trigger the byte ordering block either on the rising edge of the rx_syncstatus signal or the user-controlled rx_enabyteord signal from the fpga fabric. the byte ordering block is enabled only in oc-48 mode. ?byte ordering block? section in the stratix iv transceiver architecture chapter . chapter 1: altgx transceiver setup guide 1?59 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 enable run-length violation checking with a run length of. this option creates the output signal rx_rlv . enabling this option also activates the run-length violation circuit. if the number of continuous 1s and 0s exceeds the number that you set in this option, the run-length violation circuit asserts the rx_rlv signal. the rx_rlv signal is asynchronous to the receiver data path and is asserted for a minimum of two recovered clock cycles in oc-12 and oc-48 modes. similarly, it is asserted for a minimum of three recovered clock cycles in the oc-96 mode. for the oc-12 and oc-48 modes, the run length limits are 4 to 128 in increments of four. for the oc-96 mode, the run length limits are 5 to 160 in increments of five. ?programmable run length violation detection? section in the stratix iv transceiver architecture chapter . create an rx_syncstatus output port for pattern detector and word aligner. this is an output status signal that the word aligner forwards to the fpga fabric to indicate that synchronization has been achieved. this signal is synchronous with the parallel receiver data on the rx_dataout port. the signal width is 1 bit, 2 bits, and 4 bits for a channel width of 8 bits, 16 bits, and 32 bits, respectively. table 1-77 and ?word aligner? section in the stratix iv transceiver architecture chapter . create an rx_patterndetect port to indicate pattern detected. this is an output status signal that the word aligner forwards to the fpga fabric to indicate that the word alignment pattern programmed has been detected in the current word boundary. the signal width is 1 bit, 2 bits, and 4 bits for a channel width of 8 bits, 16 bits, and 32 bits, respectively. table 1-33 and ?word aligner? section in the stratix iv transceiver architecture chapter . create a rx_invpolarity port to enable word aligner polarity inversion. this optional port allows you to dynamically reverse the polarity of every bit of the received data at the input of the word aligner. use this option when the positive and negative signals of the differential input to the receiver ( rx_datain ) are erroneously swapped on the board. ?receiver polarity inversion? section in the stratix iv transceiver architecture chapter . create a tx_invpolarity port to allow transmitter polarity inversion. this optional port allows you to dynamically reverse the polarity of every bit of the data word fed to the serializer in the transmitter data path. use this option when the positive and negative signals of the differential output from the transmitter ( tx_dataout ) are erroneously swapped on the board. ?transmitter polarity inversion? section in the stratix iv transceiver architecture chapter . table 1?18. megawizard plug- in manager options (sonet/sdh screen) (part 2 of 3) altgx setting description reference 1?60 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation flip receiver output data bits. this option reverses the bit order of the parallel receiver data at a byte level at the output of the receiver phase compensation fifo to support msb-to-lsb transmission in sonet/sdh mode. for example, if the 16-bit parallel receiver data at the output of the receiver phase compensation fifo is '10111100 10101101' (16'hbcad), enabling this option reverses the data on the rx_dataout port to '00111101 10110101' (16'h3db5). ?sonet/sdh mode? (oc-12, oc-48, and oc-96) section in the stratix iv transceiver architecture chapter . flip transmitter input data bits. this option reverses the bit order of the parallel transmitter data at a byte level at the input of the transmitter phase compensation fifo to support msb-to-lsb transmission protocols in sonet/sdh mode. for example, if the 16-bit parallel transmitter data at the tx_datain port is '10111100 10101101' (16'hbcad), enabling this option reverses the input data to the transmitter phase compensation fifo to '00111101 10110101' (16'h3db5). ?sonet/sdh mode? (oc-12, oc-48, and oc-96) section in the stratix iv transceiver architecture chapter . table 1?18. megawizard plug- in manager options (sonet/sdh screen) (part 3 of 3) altgx setting description reference chapter 1: altgx transceiver setup guide 1?61 protocol settings ? november 2009 altera corporation stratix iv device handbook volume 3 eda screen figure 1?19 shows the eda screen of the megawizard plug-in manager. the generate netlist op tion generates a netlist for the third party eda synthesis tool to estimate timing and resource utilization for the altgx instance. figure 1?19. megawizard plug - in manager?altgx (eda screen) 1?62 chapter 1: altgx transceiver setup guide protocol settings stratix iv device handbook volume 3 ? november 2009 altera corporation summary screen figure 1?20 shows the summary screen of the megawizard plug-in manager. you can select optional files on this page. after you make your selections, click fini sh to generate the files. figure 1?20. megawizard plug - in manager?altgx (summary screen) chapter 1: altgx transceiver setup guide 1?63 document revision history ? november 2009 altera corporation stratix iv device handbook volume 3 document revision history ta b l e 1?19 lists the revision history for this chapter. table 1?19. document revision history date and document version changes made summary of changes november 2009, v4.0 added deterministic latency protocol information. added aeq information. updated pll setting information. consolidated parameter settings information ( table 1?1 to ta ble 1 ?6 ). consolidated reconfiguration settings information ( table 1?7 to table 1?9 ). consolidated protocol settings information ( table 1?10 to table 1?18 ). minor text edits. ? june 20009, v3.1 updated table 1?9, table 1?29 and table 1?35. updated figure 1?10. added introductory sentences to improve search ability. minor text edits. ? march 2009, v3.0 updated the figures to match the software changes. removed the 'deterministic latency' subprotocol from basic functional mode. removed the various clock frequencies from the reconfig clks screen for all the applicable functional modes. ? november 2008, v2.0 updated table 1?1, table 1?6, and table 1?11. updated figure 1?8. added reconfig clks and reconfig 2 sections. added the ?use atx transmitter pll? setting. changed the ?which device speed grade will you be using?? setting to the ?which device variation will you be using? setting. ? june 2008, v1.1 minor text edit. ? may 2008, v1.0 initial release. ? 1?64 chapter 1: altgx transceiver setup guide document revision history stratix iv device handbook volume 3 ? november 2009 altera corporation ? november 2009 altera corporation stratix iv device handbook volume 3 2. transceiver design flow guide this chapter describes the altera-recommended basic design flow that simplifies stratix ? iv gx transceiver-based designs. use the following design flow techniques to simplify transceiver implementation. the ?guidelines to debug transceiver-based designs? on page 2?15 provides guidelines to trouble-shoot transceiver-based designs. an example of a fibre channel protocol application is also described in this chapter. the transceiver-based design is divided into phases and are detailed in the following sections: ?architecture? on page 2?3 ?implementation and integration? on page 2?7 ?compilation? on page 2?10 ?verification? on page 2?12 ?functional simulation? on page 2?12 ?example 1: fibre channel protocol application? on page 2?17 figure 2?1 shows the design flow chart of the different stages of the design flow. the design flow stages include architecture, functional simulation, compilation, and verification. each stage of the design flow are explained in the sections that follow. siv53002-4.0 2?2 chapter 2: transceiver design flow guide stratix iv device handbook volume 3 ? november 2009 altera corporation figure 2?1. flow chart of the different stages in a transceiver-based design device specification transceiver configuration select options in the dynamic reconfiguration controller (if required) clocking architecture create transceiver instances create reset and control logic create a dynamic reconfiguration controller using the altgx_reconfig megawizard create data processing logic integrate the design implementation synthesize the design compilation add signals to signaltap ii logic analyzer include signaltap file (.stp) in the compilation verification is simulation required ? require signaltap for verification? no yes no if used, include the stratix iv gx altgx megafunction-generated wrapper file (.v or .vhd) and altgx_reconfig megafunction-generated wrapper file add altera simulation library files functional simulation simulate the design no yes create pin and oct assignments create timing constraints create clock grouping constraints if required compile the design yes power supplies is dynamic reconfiguration required ? chapter 2: transceiver design flow guide 2?3 architecture ? november 2009 altera corporation stratix iv device handbook volume 3 architecture the first step in creating a transceiver-based design is to map your system requirements with the stratix iv gx device supported features. the stratix iv gx device contains multiple transceiver channels that you can configure in multiple data rates and protocols. it also provides multiple transceiver clocking options. for your design, identify the transceiver capabilities and clocking options to ensure that the transceiver meets your system requirements. this section describes the critical parameters that you need to identify as part of this architecture phase. device specification the following device specifications must meet your requirements: refer to the device data sheet to ensure that the transceivers meet the data rate and electrical requirements for your target high-speed interface application; for example, the jitter specification and voltage output differential (v od ) range. check whether the device family that you select supports your design requirements; for example, the number of transceiver channels, fpga logic density, memory elements, and dsp blocks. if you intend to migrate to a higher logic density or higher transceiver count device in the future, ensure that the migration device is available. f for information about device characteristics, refer to the ?transceiver performance specifications? section in the dc and switching characteristics of stratix iv devices chapter. for information about transceiver resources, refer to the stratix iv device family overview chapter. transceiver configuration use the altgx megawizard ? plug-in manager interface to configure the stratix iv transceiver channel?s features and options. when selecting a transceiver configuration, check for the following parameters: check whether the transceiver physical coding sublayer (pcs) and physical medium attachment (pma) functional blocks comply with your system requirements. for example, check whether the rate match (clock rate compensation) fifo in the receiver channel pcs meets the parts per million (ppm) specifications required for your application. f for more information about transceiver specifications, refer to the ?transceiver performance specifications? section of the dc and switching characteristics of stratix iv devices chapter. select a configuration that meets your latency requirements. if your system has maximum latency requirements through the transceiver data path, consider the appropriate functional configuration. the stratix iv gx transceiver supports various configurations that differ in latency (for example, low latency pcs mode and basic [pma direct] mode). chapter 2: transceiver design flow guide 2?4 architecture ? november 2009 altera corporation stratix iv device handbook volume 3 in some configurations, specific functional blocks in the transceiver are disabled or bypassed. before you select a transceiver configuration, understand the functional blocks that must be implemented in the fpga fabric. for example, basic (pma direct) mode provides reduced latency but does not have pcs functional blocks enabled (for example, word aligner and 8b/10b encoder). therefore, implement these functional blocks in the fpga fabric if you need them in your application. some examples of functional blocks that you may need to implement in the fpga fabric are shown in ?create data processing and other user logic? on page 2?8 . f for more information about the altgx megawizard plug-in manager, refer to the altgx megafunction user guide chapter. check whether the loop-back features are available for your selected functional mode. the stratix iv gx transceiver provides diagnostic loop-back features between the transmitter channel and the receiver channel at the transceiver pcs and pma interfaces. these loop-back features help in debugging your design. if your design uses multiple transceiver channels within the same transceiver block, based on the transceiver channel configurations, the quartus ? ii software might impose restrictions on combining these channels. f for more information about these restrictions, refer to the configuring multiple protocols and data rates in a transceiver block chapter. dynamic reconfiguration you can to use the stratix iv transceivers in multiple-link interconnect environments by allowing you to dynamically reconfigure the pma controls (for example, v od , pre- emphasis, equalization, dc gain, and the transceiver channel configuration). you can reconfigure the pma controls without affecting any other transceiver channel or the logic in the fpga fabric. use the transceiver channel reconfiguration to dynamically switch a transceiver channel to multiple protocols and data rates. the quartus ii software allows you to generate a memory initialization file ( .mif ) that stores unique transceiver settings and provides a dynamic reconfiguration controller, which is soft logic that controls the transceiver reconfiguration with minimal user interface logic. you can generate this soft logic using the altgx_reconfig megawizard interface. f for more information about the altgx_reconfig interface, refer to the altgx_reconfig megawizard plug-in manager chapter. 1 all receiver channels in the stratix iv gx device require offset cancellation to counter offset variations in process, voltage, and temperature (pvt) on the receiver. the dynamic reconfiguration controller initiates the sequence to perform offset cancellation on the receiver channels. therefore, if you configure the stratix iv gx transceiver channel in receiver only or transmitter and receiver configuration, you must instantiate a dynamic reconfiguration controller. f for more information about offset cancellation or dynamic reconfiguration of pma controls or channel configuration, refer to the ?offset cancellation feature? section in the stratix iv dynamic reconfiguration chapter . chapter 2: transceiver design flow guide 2?5 architecture ? november 2009 altera corporation stratix iv device handbook volume 3 clocking the stratix iv gx transceiver is clocked by various input reference clocks, for example: dedicated transceiver reference clock ( refclk ) pins. altera recommends using refclk pins whenever possible because the refclk pins yield reduced jitter on the transmitted data. clock sources connected to global clock lines. clock outputs from the phase-locked loops (plls) in the fpga fabric. identify the transceiver channels input reference clock sources, for example: ensure that your selected device has the required number of input reference clock resources to implement your design. ensure that the transceiver clock input supports the required i/o standards. ensure that the clocking restrictions work with your selected device: check whether the allowed frequencies for the transceiver input reference clocks meet your system requirements. if you use the pll cascade clock, understand its restrictions. if you are using the auxiliary transmit (atx) pll, understand the recommendations for the input reference clock sources and the restrictions on data rate ranges supported by the atx pll. for transceiver-fpga interface clocking: ensure that the transceiver-fpga interface clock frequency limits meet your system requirements. f for information about transceiver specifications, refer to the dc and switching characteristics of stratix iv devices chapter. identify the clocking scheme to clock the transceiver data to the logic in the fpga fabric. for example, if your design has multiple transceiver channels that run at the same data rate and are connected to the one upstream link, you might be able to use a single transceiver-fpga clock to provide clocks to the transceiver data path, which can conserve clock routing resources. if you are using basic (pma direct) mode, determine whether you require a left/right pll to provide phase shifted clocks to the fpga fabric. the left/right pll clocks the data received and transmitted between the transceiver and the fpga fabric interface and may be required to meet the timing requirements of the data transfer. f for information about transceiver clocking, refer to the stratix iv transceiver clocking chapter. after you identify the required transceiver parameters, start the implementation and integration phase. chapter 2: transceiver design flow guide 2?6 architecture ? november 2009 altera corporation stratix iv device handbook volume 3 power supplies the stratix iv gx device requires multiple power supplies. the pin connection guidelines provide specific recommendations about the type of power supply regulator (linear or switching) and the voltage supply options and restrictions. for example, the transmitter buffer supply vcchtx has two options -1.5 v and 1.4 v. there are specific data rate restrictions when using 1.5 v. you must understand these restrictions when you select a power supply value. f for more information, refer to the stratix iv pin connection guidelines . estimate the power required to run your design. this estimation allows you to select the appropriate power supply modules and to design the power distribution network on your board. use the early power estimator tool to estimate the transient current requirements. f for more information about the early power estimation tool, refer to the stratix iii and stratix iv powerplay early power estimator . if your design is already complete, use the power optimization features available in the stratix iv devices. f for more information about optimizing power in stratix iv fpga devices, refer to an 514: power optimization in stratix iv fpgas . board design requirements for improved signal integrity on the high-speed serial interface, follow the best design practices for your power distribution network, pcb design, and stack up. f for detailed guidelines and recommendations about your power distribution network, pcb design, and stack up, refer to the board design resource center web site. f for more information about the stratix iv gx design process, refer to an 519: stratix iv design guidelines . chapter 2: transceiver design flow guide 2?7 implementation and integration ? november 2009 altera corporation stratix iv device handbook volume 3 implementation and integration there are three steps to the implementation and integration phase: ?create transceiver instances? on page 2?7 ?create reset logic to control the fpga fabric and transceivers? on page 2?34 ?create data processing and other user logic? on page 2?36 create transceiver instances the altgx megawizard plug-in manager to creates the transceiver instance. in the architecture phase, you identified the transceiver configuration for your design. using the altgx megawizard plug-in manager, select the appropriate parameters that apply to your architecture requirements. reset signals: the altgx megawizard plug-in manger provides various reset and status signals: reset signals? tx_digitalreset , rx_digitalreset, rx_analogreset, and pll_powerdown are required to reset the transceiver pcs and pma functional blocks. status signals? rx_freqlocked and pll_locked indicate the state of the receiver cdr and transmitter pll, respectively. use these reset and status signals to implement the transceiver reset control logic in the fpga fabric. for more information, refer to ?create reset and control logic? on page 2?8 . if you determine that your application requires dynamic reconfiguration, select the options in the reconfig screen of the altgx megawizard interface. if you intend to dynamically reconfigure the channel into other protocol modes or data rates, the reconfig screen provides multiple options (for example, the channel interface and use alternate pll options) to enable this feature. f to u n d e rs ta n d t he logical channel addressing , logical pll index , and type of reconfiguration to select options in the reconfig screen, refer to the ? channel and cmu pll reconfiguration mode details? section in the stratix iv dynamic reconfiguration chapter. depending on your system, when you use multiple transceiver channels, you might be able to share the transmitter and receiver parallel clocks of one channel with the other channels. if your design requires sharing a clock resource, select the tx_coreclk and rx_coreclk ports. f transceiver-fpga fabric interface clock sharing conditions are provided in the stratix iv transceiver clocking chapter. f for more information about using the altgx megawizard plug-in manager and the functionality of the different options and signals available, refer to the altgx megafunction user guide chapter. chapter 2: transceiver design flow guide 2?8 implementation and integration ? november 2009 altera corporation stratix iv device handbook volume 3 create dynamic reconfiguration controller instances use the altgx_reconfig megawizard interface to create the dynamic reconfiguration controller instance. if you intend to use the channel and cmu pll reconfiguration feature, select the relevant options in the altgx_reconfig megawizard plug-in manager. f for descriptions of the options in the altgx_reconfig megafunction, refer to the stratix iv altgx_reconfig megafunction user guide chapter. f for more information about using the signals, refer to the stratix iv dynamic reconfiguration chapter. create reset and control logic the reset sequence is important for initializing the transceiver functional blocks to proper operating condition. altera recommends a reset sequence for different transceiver configurations and protocol functional modes. the altgx megawizard plug-in manager provides the tx_digitalreset , rx_analogreset, rx_digitalreset , and pll_powerdown signals to reset the different functional blocks of the transceiver. you can reset the cmu pll or the atx pll (based on your selection) using the pll_powerdown signal. for transceiver instances that share the same cmu pll or atx pll, the pll_powerdown port of these instances must be driven by the same logic. f for more information about reset sequences, refer to the reset control and powerdown chapter. create data processing and other user logic a typical transceiver-based design consists of custom data processing and other user logic that must be implemented in the fpga fabric based on your application requirements. in addition to application-specific logic, for specific transceiver configurations, you may need additional logic to interface with the transceivers. this section provides examples of such logic. ppm detector when the receiver cdr is used in m anual lock mode each receiver channel contains a clock data recovery (cdr) that you can use in automatic or manual lock mode. if you use receiver cdr in manual lock mode, you can control the timing of the cdr to lock to the input reference clock using the rx_locktorefclk port or lock to the recovered data using the rx_locktodata port. when you use the receiver cdr in manual lock mode, you may need to implement the ppm detector in the fpga fabric to determine the ppm difference between the upstream transmitter and the stratix iv gx receiver. chapter 2: transceiver design flow guide 2?9 implementation and integration ? november 2009 altera corporation stratix iv device handbook volume 3 synchronization state machine in manual word alignment mode each receiver channel contains a synchronization state machine in the pcs that you can enable in certain functional modes. the synchronization state machine triggers the loss of synchronization status to the fpga fabric based on invalid 8b/10b code groups. however, the synchronization state machine in the pcs is not available in some functional modes. you may need to implement custom logic in the fpga fabric to indicate the loss-of-synchronization status of the received data. gear boxing logic some protocols require a wider data path than provided by the transceiver interface; for example, the interlaken protocol requires 64/67-bit encoding and decoding, but the maximum data path interface in the stratix iv gx transceiver is 40 bits. therefore, you must implement gear boxing logic to interface the 64/67-bit encoder-decoder with the transceiver interface. functional blocks to interface with the transceiver configured in basic (pma direct) mode in basic (pma direct) mode, all the pcs functional blocks in the transceiver channel are disabled. therefore, you may need to implement the following blocks in the fpga fabric: word alignment?to align the byte boundary on the received data. byte deserializer?to increase the data path width to the rest of the user logic and to reduce the clock frequency of the data path by two. phase compensation fifo (for bonded channel applications)?in bonded channel applications in which multiple transceiver channels are connected to the same upstream system (for example, one interlaken protocol link using 24 transceiver channels). to minimize the global clock routing resources you use, implement a phase compensation fifo to interface the receiver side of the transceiver interface with the logic in the fpga fabric. use the recovered clock from each channel to clock the write side of the phase compensation fifo. use the recovered clock from any of the channels to clock the read side of the phase compensation fifo. with this method, you only use one clock resource and the subsequent receive-side logic in the fpga fabric can operate in this single clock domain. deskew logic (for bonded channel applications)?in bonded channel applications in which multiple transceiver channels are connected to the same upstream system, the data received between multiple channels are not aligned due to potential skew in the interconnect and the upstream transmitter system. to compensate for the skew, use deskew logic in the fpga fabric. encoding/decoding or scrambling/descrambling?many protocols require the transmitter data to be encoded or scrambled to maintain signal integrity. this logic may be required in the fpga fabric based on your application requirements. chapter 2: transceiver design flow guide 2?10 compilation ? november 2009 altera corporation stratix iv device handbook volume 3 integrate the design after you implement all of the required logic, integrate the transceiver instances with the remaining logic and provide the appropriate transceiver-fpga fabric interface clocking. synthesize the design using third-party synthesis tools, such as synopsys synplicity or the quartus ii software synthesis tool. this allows you to detect the syntax errors in your design. f if you are using the transceiver in basic (pma direct) mode, you must develop all the pcs functionality in the fpga fabric. compilation when you compile your design, the quartus ii software generates an sram object file ( .sof) or programmer object file ( .pof ) that you can download to the stratix iv gx hardware. typically, the first step in compiling the design is assigning pin locations for the i/os and clocks. use the pin planner tool in the quartus ii software to assign pins. 1 for a basic tutorial on the quartus ii software, open the quartus ii software, click the help menu and select tu to ri a l . stratix iv gx transceivers support a variety of i/o standards for the input reference clocks and serial data pins. assign pins and the logic level standard (for example, 1.5-v pcml and lvds) for the input and output pins. f for more information, refer to the i/o features in stratix iv devices chapter. if you share the same transceiver-fpga fabric interface clocks for multiple transceiver channels ( tx_coreclk and rx_coreclk ) in your design, set the 0 ppm constraints. these constraints enable the quartus ii software to relax the legality check restrictions on clocking. f for more information, refer to the ?common clock driver selection rules? section of the stratix iv transceiver clocking chapter. for transceiver serial pins and refclk pins, set the on-chip termination (oct) resistor settings. f for more information about supported oct settings, refer to ?transmitter output buffer? section of the stratix iv transceiver architecture chapter. create timing constraints for the clocks and data paths. use the timequest timing analyzer to set timing constraints. f for more information about the timequest timing analyzer, refer to the quartus ii development software handbook . compile the design. this generates a .sof that can be downloaded in the fpga. chapter 2: transceiver design flow guide 2?11 compilation ? november 2009 altera corporation stratix iv device handbook volume 3 the quartus ii software generates multiple report files that contain information such as transceiver configuration and clock resource utilization. the following section describes the report files relevant to using transceivers and clock resource. report files the quartus ii software provides a report file in the synthesis, fitter, map, placement, and assembler stages. the report file provides useful information on the device and transceiver configuration generated by the quartus ii software. this section only describes the reports provided in the fitter stage. to access the report, click on the processing menu, select the compilation report option and expand the fitter tab. fitter summary the fitter summary provides high-level information on fpga fabric resources and transceiver channels used by your design. for example, to ensure that the quartus ii software has created the number of transceiver channels as specified in your design, refer to the gxb receiver channels and gxb transmitter channels field at the bottom of the report. for detailed information on resource utilization, expand the fitter tab. pin-out file select the pin-out file option under the fitter tab. the quartus ii software displays the i/o standards and bank numbers of all the pins (used and unused) needed to connect to the board. the quartus ii software also generates a pin file ( .pin ) with the above information. altera recommends that you use the .pin as a guideline. use the pin connection guidelines for board layout. f for more information about pin connection guidelines for board layout, refer to stratix iv gx device family pin connection guidelines . resource section expand the resource section option under the fitter tab to view the following tabs: the gxb transmitter channel tab?provides generated settings for all the transmitter channels instantiated in your design. the gxb transmitter pll tab?provides generated settings for all the transmitter plls instantiated in your design. the gxb receiver channel tab?provides generated settings for all the receiver channels instantiated in your design. the global and other fast signals tab?displays the list of clock and other signals in your design that are assigned to the global and regional clock resources. you can use the report file to verify whether the transceiver settings (for example, data rate), are generated per your settings in the altgx megawizard plug-in manager. chapter 2: transceiver design flow guide 2?12 verification ? november 2009 altera corporation stratix iv device handbook volume 3 verification the signaltap ? logic analyzer allows you to verify design functionality using the on-chip logic analyzer. signaltap provides options to create multiple sets of signals that can be sampled using different trigger clocks. you can add the signals to the signaltap logic analyzer and save the file as an stp file ( .stp) . when you include this .stp along with the design files and compile the design, the quartus ii software creates an .sof that allows you to verify the functionality of the signals that you added in the signaltap logic analyzer file. you can run the .stp that connects to the device through the jtag port and displays the signal transitions using the quartus ii software. because the jtag port is required to run signaltap, consider designing the board with the jtag interface for debugging your system. f for more information about using signaltap, refer to the in-system design debugging section in volume 3 of the quartus ii development software handbook . to verify the functionality of the pcs and pma blocks, the stratix iv gx transceiver provides diagnostic loop-back features between the transmitter and receiver channels. f for more information, refer to the ?loopback modes? section in the stratix iv transceiver architecture chapter. functional simulation use the altgx megawizard-generated wrapper file to simulate the instantiated transceiver configuration in third-party simulation software such as modelsim. for simulation, specific altera ? simulation library files are required (listed in table 2?1 ). the following library files are available in vhdl and verilog versions: 220pack 220model altera_mf_components altera_mf sgate_pack sgate stratixiv_hssi_component stratixiv_hssi_atoms these simulation files are available under the following folder in the quartus ii installation directory: chapter 2: transceiver design flow guide 2?13 functional simulation ? november 2009 altera corporation stratix iv device handbook volume 3 for vhdl simulation using modelsim, create the following libraries in your modelsim project: lpm sgate altera_mf stratixiv_hssi these simulation files are available under 2?14 chapter 2: transceiver design flow guide functional simulation stratix iv device handbook volume 3 ? november 2009 altera corporation include all the libraries in the search path. add the altgx and altgx_reconfig megawizard plug-in manager-generated wrapper files ( .v or .vhd ) and all of the design files to the library. compile all the library files first, then the design files, and lastly run the simulation. for verilog simulation, add the altgx and altgx_reconfig megawizard plug-in manager-generated verilog wrapper files ( .v ), the altera library files, and all of the design files. compile all the library files first, then the simulation model file, followed by the design files. lastly, run the simulation. these guidelines are further described in ?example 1: fibre channel protocol application? below. f for more information about functional rtl simulation or post-fit simulation, refer to the simulation chapter in volume 3 of the quartus ii handbook . figure 2?2. modelsim option to compile files in a specific library chapter 2: transceiver design flow guide 2?15 guidelines to debug transceiver-based designs ? november 2009 altera corporation stratix iv device handbook volume 3 guidelines to debug transceiver-based designs this section provides guidelines to debug transceiver-based designs. if a system failure occurs, the first step is to ensure the functionality of the logic within the fpga. use the following information when you observe a system failure. guidelines to debug the fpga logic and the transceiver interface before checking the functionality in silicon, perform functional simulation to ensure the basic functionality of the rtl and the transceiver-fpga fabric interface. understand the limitations of functional simulation. if you intend to simulate timing parameters, consider post-fit simulation. the functional simulation model for transceivers does not model timing-related parameters or uncertainties in the transceiver data path. for example, the ppm difference in the rate matcher clocks (clock rate compensation) or the phase differences between the read and write side of the phase compensation fifo are not modeled. f for information about functional rtl simulation or post-fit simulation, refer to the simulation chapter in volume 3 of the quartus ii handbook . check whether the compiled design has timing violations in the timequest timing analyzer report. set the appropriate timing constraints on the failing paths. f for information about using the timequest timing analyzer, refer to the timing analysis chapter in volume 3 of the quartus ii handbook . verify the functionality of the transmitter and receiver data path with serial loopback. dynamically control the serial loopback through the rx_seriallpbken port. when this signal is asserted, data from the transmitter serializer is looped back to the receiver cdr of the channel. use signaltap to verify the behavior of the user logic and the transceiver interface signals. if you have fpga i/o pins available for debug, you can also use the external logic analyzer to debug the functionality of the device. f for more information, refer to the in-system debugging using external logic analyzers chapter in volume 3 of the quartus ii handbook . 1 to use these features, you must connect the jtag configuration pins in the fpga. verify the interconnect on the receive side by configuring the transceiver in reverse serial loopback mode. in this case, the recovered data from the receiver channel is sent to the transmitter buffer. to configure a transceiver channel operating in a different configuration to reverse serial loopback mode, use the dynamic reconfiguration controller. check whether the transceiver fpga fabric interface clocking schemes follow the recommendations provided in the ?fpga fabric-transceiver interface clocking? section in the stratix iv transceiver clocking chapter. ensure that you have used the recommended transceiver reset sequence. 2?16 chapter 2: transceiver design flow guide guidelines to debug transceiver-based designs stratix iv device handbook volume 3 ? november 2009 altera corporation guidelines to debug system level issues if you have determined that the logic in the fpga fabric is functionally correct, check for system level issues: check the voltage ripple across the 2 k resistor that is connected to the rref pin. the voltage ripple must be less than 60 mv. measure the eye on the near-end and far-end of the transmitter to understand the jitter added by the transmitter and interconnect. ensure that the high-speed scopes you use for measurement have sufficient bandwidth (bandwidth rating on the scope and cables must be at least three times the serial data rate). check whether the eye meets the eye-mask requirements if specified by the protocol application. use scopes that provide information on the different jitter components to understand the possible source of the increased jitter. for example, increased intersymbol interface (isi) indicates potential bandwidth limitations on the interconnect. 1 some scopes, such as agilent 86100c dca, require pre-defined patterns (for example, prbs7 or prbs23) to provide jitter components. measure signals on the traces (no connector) using high-impedance differential probe with short leads. ensure that characteristic impedance on the interconnect matches the source and load systems. check for impedance discontinuities on the trace by time domain reflectometry (tdr). revisit the board design, layout, and routing for any inconsistencies that can cause impedance discontinuities. check whether the termination schemes on the stratix iv gx device and on the upstream system are matched. altera recommends using oct in the stratix iv gx device instead of external termination to improve signal integrity. change the transmit output differential voltage to improve eye amplitude. compensate for high frequency losses in the interconnect by changing the equalization settings of the stratix iv gx device and check for improvement of the bit error rate. if the upstream system does not have an equalization feature, increase the pre-emphasis (1st post tap) of the stratix iv gx transmitter. in cases where there are multiple interconnects between the stratix iv gx device and upstream system, use the pre-tap and 2nd post tap. altera provides tools to select the pre-emphasis. chapter 2: transceiver design flow guide 2?17 example 1: fibre channel protocol application ? november 2009 altera corporation stratix iv device handbook volume 3 measure the increase in jitter at the near end and far end with one channel turned on at a time if you have multiple transceiver channels connected to the upstream system. this helps to observe the effect of cross talk from adjacent channels on the victim channel. check the board layout and routing to ensure that you have implemented the design practices to mitigate cross talk. ensure that the input voltage and duty cycle of the input reference clock source provided to the transmitter plls meet the input reference clock requirements. check whether the voltage drop on the power supplies is within the specified tolerance range. measure the voltage at the via beneath the power supply pin using a high- impedance probe. check whether the voltage regulator specifications meet the stratix iv gx power supply requirements. revisit the power distribution scheme for the supply voltage to ensure that it is designed to handle the transient current requirements of the transceiver. f for the tolerance values of the different power supplies, refer to the stratix iv dc and switching characteristics chapter. check for periodic modulation of other frequency components on the transmit data. send a high-frequency pattern (1010) from the transmitter side and connect the transmitter serial output to a spectrum analyzer. f for more information about stratix iv gx transceivers, refer to an 553: debugging transceivers . example 1: fibre channel protocol application assume that you want to implement a fibre channel protocol application using three transceiver channels. consider the following system requirements: you need three transceiver channels all the channels need to be placed in the same transceiver block all the channels need to have independent control to reset their pcs and pma functional blocks table 2?2 shows the transceiver channel configuration for example 1. tab le 2 ?2 . transceiver channel configuration for example 1 channels mode of operation data rate input reference clock frequency 0 receiver and transmitter fc4g (4.25 gbps) 106.25 mhz 1 receiver and transmitter fc1g (1.0625 gbps) 53.125 mhz 2 transmitter only fc4g (4.25 gbps) 106.25 mhz 2?18 chapter 2: transceiver design flow guide example 1: fibre channel protocol application stratix iv device handbook volume 3 ? november 2009 altera corporation phase 1?architecture in this phase, check whether the stratix iv gx device supports or meets your design requirements. device specification consider the questions listed in table 2?3 before setting device-specific parameters. f for the maximum data rates supported, refer to the ?transceiver performance specifications? section in the dc and switching characteristics of stratix iv devices chapter. transceiver configuration the fibre channel protocol uses an 8b/10b encoder and requires clock rate compensation. functional blocks consider the questions listed in table 2?4 before configuring the transceiver. tab le 2 ?3 . device specific parameters questions answer do the parameters meet the fibre channel protocol electrical requirements? ye s for more information, refer to the ?transceiver performance characteristics? section in the dc and switching characteristics of stratix iv devices chapter are three transceiver channels available? yes is there support for 4.25 gbps and 1.0625 gbps data rates? ye s two cmu plls are available within each transceiver block to support two different transmitter data rates. each receiver channel contains a dedicated receiver cdr that supports 4.25 gbps and 1.0625 gbps data rates. tab le 2 ?4 . configuring the transceiver questions answer is the 8b/10b encoder in the pcs block fibre channel compliant? no the fibre channel protocol consists of two different end-of- frame (eoft) ordered sets. the correct eoft ordered set sent by user logic depends on the ending disparity of the word preceeding the eoft. the stratix iv gx transceiver does not provide running disparity flags to the user logic. therefore, the user logic might not be able to select the correct eoft ordered set. is there a workaround? yes implement the 8b/10b encoder in the fpga fabric. is the clock rate compensation block in the pcs available without an 8b/10b encoder? no you can implement this in the fpga fabric. chapter 2: transceiver design flow guide 2?19 example 1: fibre channel protocol application ? november 2009 altera corporation stratix iv device handbook volume 3 the design requires a transmitter and receiver configuration for two channels and a transmitter only configuration for one channel ( table 2?5 ). dynamic reconfiguration if your application requires you to dynamically reconfigure the transceiver pma controls, ensure that you understand the settings, options, and user logic required to enable this feature. f for more information, refer to the ?interfacing altgx and altgx_reconfig instances? section in the stratix iv dynamic reconfiguration chapter. f for more information about initiating read and write transactions, refer to the ?dynamically reconfiguring pma controls? section in the stratix iv dynamic reconfiguration chapter . if you are using the channel reconfiguration feature, enable the appropriate options in the altgx and altgx_reconfig megawizards. f you can dynamically use the reconfiguration modes to reconfigure different functional blocks in a transceiver channel using .mifs . for information about generating .mifs , refer to the ?channel and cmu pll reconfiguration mode details? section in the stratix iv dynamic reconfiguration chapter. clocking consider the questions listed in table 2?6 before configuring clocking. tab le 2 ?5 . multiple channels questions answer does the stratix iv gx transceiver support these two configurations and allow you to combine them within the same transceiver block yes the available fpga fabric interface width is 20 or 40 bits to support 4.25 gbps and 1.0625 gbps data rates, respectively. this fpga fabric interface facilitates 8b/10b encoding and decoding in the fpga fabric without additional re- arrangement of the received parallel data to a 10-bit boundary. tab le 2 ?6 . configuring clocking (part 1 of 2) questions answer is there support for two different input reference clocks? yes the stratix iv gx transceiver has two refclk pins for each transceiver block. do the refclk pins support the required frequency range? yes the minimum frequency range of refclk is 50 mhz; the maximum frequency range is 622.08 mhz. 2?20 chapter 2: transceiver design flow guide example 1: fibre channel protocol application stratix iv device handbook volume 3 ? november 2009 altera corporation f for more information about clocking the transmitter and receiver channel data path for this type of configuration, refer to the ?transmitter channel datapath clocking? section of the stratix iv transceiver clocking chapter. figure 2?3 shows the transmitter side of the transceiver setup for example 1. 1 the transmitter side receives its clocks from the clock multiplier unit (cmu) plls. the receiver side contains its dedicated cdr that provides the high-speed serial and low-speed parallel clocks to its pma and pcs blocks, respectively. can transceiver-fpga fabric interface clocking be shared? no the design requires independent control on all channels, so you must not share the transceiver-fpga fabric interface clock of one channel with another channel. each of the channels must use its own tx_clkout and rx_clkout signals to clock the data between the transceiver channels and the fpga fabric. does the stratix iv gx transceiver support this feature? yes tab le 2 ?6 . configuring clocking (part 2 of 2) questions answer figure 2?3. top-level transceiver setup?transmitter-side only channel 0 (4.25 g bps) tx rx channel 1 (1.0625 g bps) tx rx channel 2 (4.25 g bps) tx one cmu pll config u red for 4.25 gbps data rate second cmu pll config u red for 1.0625 gbps data rate refclk0 (106.25 mhz) refclk1 (53.125 mhz) transcei v er block chapter 2: transceiver design flow guide 2?21 example 1: fibre channel protocol application ? november 2009 altera corporation stratix iv device handbook volume 3 phase 2?implementation create the transceiver instance using the altgx megawizard plug-in manager. f for a description of the individual options, refer to the altgx megafunction user guide chapter. create the transceiver instance for an fc4g configuration (channel 0) figure 2?4 through figure 2?14 show the different options available in the altgx megawizard plug-in manager to create the transceiver channel instance for the fc4g data rate. use this instance for channel 0, with the following settings: general screen?you can configure the stratix iv gx transceiver for fibre channel protocol using basic mode. set the options with the values shown in figure 2?4 . figure 2?4. fc4g instance settings (general screen) 2?22 chapter 2: transceiver design flow guide example 1: fibre channel protocol application stratix iv device handbook volume 3 ? november 2009 altera corporation pll / ports screen?check the train receiver cdr from pll inclk option, as shown in figure 2?5 . when you select this option, the same input reference clock used for the cmu pll is provided as a training clock to the receiver cdr. check the pll_powerdown signal. this signal allows you to power down the cmu pll. use this signal as part of your reset sequence. check the pll_locked signal. this signal indicates whether the cmu pll is locked to the input reference clock. the user logic waits until the pll_locked signal goes high before transmitting data. check the rx_freqlocked signal. this signal indicates whether the receiver cdr is locked to data. when the receiver cdr is configured in automatic lock mode, assert the rx_digitalreset signal if the rx_freqlocked signal goes low to keep the receiver pcs under reset. altera recommends specific transceiver reset sequences to ensure proper device operation. f for more information about receiver cdr and lock modes, refer to the ?receiver channel datapath? section of stratix iv transceiver architecture chapter. figure 2?5. fc4g instance settings (pll/ports screen) chapter 2: transceiver design flow guide 2?23 example 1: fibre channel protocol application ? november 2009 altera corporation stratix iv device handbook volume 3 ports /cal blk screen?the calibration block is required so it is always enabled. select the options shown in figure 2?6 . figure 2?6. fc4g instance settings (ports/cal blk screen) 2?24 chapter 2: transceiver design flow guide example 1: fibre channel protocol application stratix iv device handbook volume 3 ? november 2009 altera corporation rx analog screen?select the options shown in figure 2?7 . f for a description of the individual options, refer to the altgx megafunction user guide chapter. figure 2?7. fc4g instance settings (rxanalog screen) chapter 2: transceiver design flow guide 2?25 example 1: fibre channel protocol application ? november 2009 altera corporation stratix iv device handbook volume 3 tx analog screen?select the output differential voltage and common mode voltage values that meet the fibre channel protocol specification. if you intend to transmit data through faulty interconnects, select the pre-emphasis settings shown in figure 2?8 . f for more information about pre-emphasis settings, refer to the dc and switching characteristics of stratix iv devices chapter. figure 2?8. fc4g instance settings (tx analog screen) 2?26 chapter 2: transceiver design flow guide example 1: fibre channel protocol application stratix iv device handbook volume 3 ? november 2009 altera corporation reconfig screen?set the starting channel number to 0 . because offset cancellation is required for receiver channels, the offset cancellation for receiver channels option is automatically enabled. ensure that you connect the reconfig_fromgxb and reconfig_togxb ports with the dynamic reconfiguration controller ( figure 2?9 ). 1 for more information about the starting channel numbers, refer to the ?logical channel addressing while reconfiguring the pma controls? section of the stratix iv dynamic reconfiguration chapter. figure 2?9. fc4g instance settings (reconfig screen) chapter 2: transceiver design flow guide 2?27 example 1: fibre channel protocol application ? november 2009 altera corporation stratix iv device handbook volume 3 lpbk screen?the serial loopback option is enabled, as shown in figure 2?10 . figure 2?10. fc4g instance settings (lpbk screen) 2?28 chapter 2: transceiver design flow guide example 1: fibre channel protocol application stratix iv device handbook volume 3 ? november 2009 altera corporation basic/8b10b screen?the basic/8b10b screen is shown in figure 2?11 . the 8b/10b encoder is not compatible with the fibre channel protocol application; therefore, this option is unchecked. figure 2?11. fc4g instance settings (basic 8b/10b) chapter 2: transceiver design flow guide 2?29 example 1: fibre channel protocol application ? november 2009 altera corporation stratix iv device handbook volume 3 wor d a l ign e r screen?the fibre channel protocol requires that you use k28.5 to align the byte boundary. in the what is the word alignment pattern? option, set one of the 10-bit disparity values to k28.5 . the word aligner automatically detects when the other disparity value is received. select the rx_patterndetect and rx_syncstatus signals. the rx_patterndetect signal indicates whenever the word alignment pattern is detected in the word boundary. click finish to exit the altgx megawizard plug-in manager. figure 2?12. fc4g instance settings (word aligner screen) 2?30 chapter 2: transceiver design flow guide example 1: fibre channel protocol application stratix iv device handbook volume 3 ? november 2009 altera corporation create the transceiver instance for an fc1g configuration (channel 1) creating the instance for fc1g is very similar to that of the fc4g configuration, with the following changes: general screen?set the values shown in figure 2?13 . reconfig screen?set the starting channel number to 4. figure 2?13. fc1g instance (channel 1) settings (general screen) chapter 2: transceiver design flow guide 2?31 example 1: fibre channel protocol application ? november 2009 altera corporation stratix iv device handbook volume 3 create the instance for an fc4g configuration?transmitter only mode (channel 2) this configuration is similar to the channel 0 configuration, with the following changes: set the operation mode to transmitter only , as shown in figure 2?14 . because this is a transmitter only instance, all the options relevant to the receiver are not available in the altgx megawizard plug-in manager. figure 2?14. fc4g_txonly instance (channel 1) settings (general screen) 2?32 chapter 2: transceiver design flow guide example 1: fibre channel protocol application stratix iv device handbook volume 3 ? november 2009 altera corporation reconfig screen?set the starting channel number to 8 . select the analog controls option even if you do not intend to dynamically reconfigure the pma controls, as shown in figure 2?15 . selecting this option is required for this example scenario because: for a transmitter only instance, offset cancellation is not available; therefore, the reconfig_fromgxb and reconfig_togxb ports are not available. the other two instances (containing a receiver channel) have these ports available because offset cancellation is automatically enabled. if one transceiver instance has the reconfig_fromgxb and reconfig_togxb ports enabled, the quartus ii software requires the other transceiver instances to have these ports enabled to combine them in the same transceiver block. therefore, for this transmitter only instance, the analog options... must be selected. f for more information about the requirements to combine multiple transceiver instances, refer to the ?combining transceiver instances in multiple transceiver blocks? section in the configuring multiple protocols and data rates in a transceiver block chapter. figure 2?15. fc4g_txonly instance (reconfig) screen chapter 2: transceiver design flow guide 2?33 example 1: fibre channel protocol application ? november 2009 altera corporation stratix iv device handbook volume 3 create the dynamic reconfiguration controller (altgx_reconfig) instance this section only describes the relevant options that must be set to implement the application. f for more information, refer to the stratix iv dynamic reconfiguration chapter. figure 2?16 shows the options that you must set (assuming that you do not require dynamic reconfiguration of the pma controls in the transceiver channels). f for more information about selecting the number of channels option, refer to the ?total number of channels option in the altgx_reconfig instance? section in the stratix iv dynamic reconfiguration chapter. connect the following: reconfig_fromgxb[16:0] of the altgx_reconfig instance to the fc4g instance (channel0) reconfig_fromgxb[33:17] to the fc1g instance (channel1) reconfig_fromgxb[50:34] to the fc4g transmitter only instance (channel2) reconfig_togxb[3:0] of the altgx_reconfig instance to all three transceiver instances figure 2?16. altgx_reconfig settings (reconfiguration settings screen) 2?34 chapter 2: transceiver design flow guide example 1: fibre channel protocol application stratix iv device handbook volume 3 ? november 2009 altera corporation create reset logic to control the fpga fabric and transceivers the design requires independent control on each channel. altera recommends creating independent reset control logic for each channel. in this design, channel 0 and channel 2 share the same cmu pll (because they are configured at the same data rate) and channel 1 uses the second cmu pll. when you create a transmitter only or receiver and transmitter instance, the altgx megawizard plug-in manager provides a pll_powerdown signal to reset the cmu pll that provides clocks to the transmitter channel. in this design example, because channels 0 and 2 share the same cmu pll, drive the pll_powerdown port of channel 0 and channel 2 in the altgx instance from the same logic. chapter 2: transceiver design flow guide 2?35 example 1: fibre channel protocol application ? november 2009 altera corporation stratix iv device handbook volume 3 channels 0, 1, and 2 have separate rx_digitalreset, rx_analogreset , and tx_digitalreset signals. figure 2?17 shows the interface between the three transceiver instances and the fpga fabric. figure 2?17. transceiver?fpga fabric interface receiver side logic transmitter side logic transmitter side logic receiver side logic user logic reset control logic transmitter side logic data processing logic 8b/10b encoder 8b/10b decoder data processing logic reset control for cmu pll reset control logic data processing logic 8b/10b encoder reset control logic data processing logic data processing logic 8b/10b encoder 8b/10b decoder rx_dataout rx_syncstatus rx_patterndetect tx_datain rx_analogreset rx_digitalreset tx_digitalreset rx_freqlocked pll_locked pll_powerdown tx_datain tx_digitalreset pll_powerdown pll_locked rx_dataout rx_syncstatus rx_patterndetect tx_datain rx_analogreset tx_digitalreset rx_digitalreset rx_freqlocked altgx instance channel0 starting channel number = 0 reconfig_fromgxb[16:0] reconfig_togxb[3:0] altgx_reconfig instance reconfig_fromgxb[16:0] reconfig_fromgxb[50:34] reconfig_fromgxb[33:17] altgx instance channel 2 reconfig_fromgxb[16:0] reconfig_togxb[3:0] starting channel number = 8 altgx instance channel 1 reconfig_togxb[3:0] reconfig_fromgxb[16:0] starting channel number = 4 2?36 chapter 2: transceiver design flow guide document revision history stratix iv device handbook volume 3 ? november 2009 altera corporation create data processing and other user logic for this example, you must implement the 8b/10b encoder and decoder in the fpga fabric. figure 2?17 on page 2?35 shows the logic on the transmitter and receiver side and the system logic controls for all channels in the fpga fabric. this block diagram is a representation of a typical system and may not exactly show the different blocks in a practical application. interface all the logic blocks with the transceiver. if you would like to add signaltap for verification, first complete synthesis, then add the transceiver-fpga fabric or other user logic signals in signaltap. lastly, compile the design to generate the .sof . phase 3?compilation assign pins for the input and output signals in your design. the quartus ii software versions 8.1 and earlier do not allow pin assignments for the stratix iv gx device. set the oct values for the transceiver serial pins, add timing constraints for the clocks and data paths in your logic, then compile the design. phase 4?simulating the design to simulate the design, follow the steps outlined in ?functional simulation? on page 2?12 . document revision history table 2?7 shows the revision history for this chapter. tab le 2 ?7 . document revision history date and document version changes made summary of changes november 2009, v4.0 added table 2?3 , tab le 2 ?4 , ta ble 2? 5 , and ta bl e 2? 6 . minor text edits. ? june 2009, v3.1 updated the ?introduction?, ?power supplies?, ?transceiver configuration?, ?clocking?, ?create transceiver instances?, ?create dynamic reconfiguration controller instances?, ?create data processing and other user logic?, ?functional simulation? sections. added the ?board design requirements?, ?gear boxing logic?, ?guidelines to debug the fpga logic and the transceiver interface?, and ?guidelines to debug system leve l issues? sections. added introductory sentences to improve search ability. ? march 2009, v3.0 add ?power supplies? on page 2?6 updated ?dynamic reconfiguration? on page 2?4 te xt e dit s ? chapter 2: transceiver design flow guide 2?37 document revision history ? november 2009 altera corporation stratix iv device handbook volume 3 november 2008, v2.0 added ?transceiver configuration? on page 2?3 added ?create dynamic reconfiguration controller instances? on page 2?8 ?dynamic reconfiguration? on page 2?15 updated ?create the instance for an fc4g configuration?transmitter only mode (channel 2)? on page 2?28 added ?create the dynamic reconfiguration controller (altgx_reconfig) instance? on page 2?30 updated figure 2?1, figure 2?4, figure 2?5, figure 2?6, figure 2?7, figure 2?8, figure 2?10, figure 2?11, figure 2?12, figure 2?13, and figure 2?14 added figure 2?9, figure 2?15, and figure 2?16 ? may 2008, v1.0 initial release ? tab le 2 ?7 . document revision history 2?38 chapter 2: transceiver design flow guide document revision history stratix iv device handbook volume 3 ? november 2009 altera corporation ? november 2009 altera corporation stratix iv device handbook volume 3 3. stratix iv altgx_reconfig megafunction user guide you can use the altgx_reconfig megawizard? plug-in manager in the quartus ? ii software to create and modify design files for the stratix ? iv device family. this chapter describes the different quartus ii settings for dynamic reconfiguration in the altgx_reconfig megawizard plug-in manager. the megawizard plug-in manager helps you create or modify design files that contain custom megafunction variations. these auto-generated megawizard files can then be instantiated in a design file. the megawizard plug-in manager allows you to specify options for the altgx_reconfig megafunction. start the megawizard plug-in manager using one of the following methods: choose the megawizard plug-in manager command (tools menu). when working in the block editor (schematic symbol), open the edit menu and choose insert symbol . the symbol dialog box appears. in the symbol dialog box, click megawizard plug-in manager . start the stand-alone version of the megawizard plug-in manager by typing the following command at the command prompt: qmegawiz. dynamic reconfiguration this section describes the options available on the individual pages of the altgx_reconfig megawizard plug-in manager. 1 the megawizard plug-in manager provides a warning if any of the settings you choose are illegal. figure 3?1 shows the first page of the megawizard plug-in manager. to generate an altgx_reconfig custom megafunction variation, select create a new custom megafunction variation . click next . figure 3?1. megawizard plug-in manager (page 1) siv53004-3.0 3?2 chapter 3: stratix iv altgx_reconfig megafunction user guide dynamic reconfiguration stratix iv device handbook volume 3 ? november 2009 altera corporation figure 3?2 shows the second page of the megawizard plug-in manager. select the following options (click next when you are done): 1. in the list of megafunctions on the left, click the ? + ? icon beside the i/o item. from the options presented, choose altgx_reconfig megafunction . 2. from the drop-down menu beside which device family will you be using? , select stratix iv . 3. from the radio buttons under which type of output file do you want to create? , choose your output file format ( ahdl , vhdl , or verilog hdl ). 4. in the box beneath what name do you want for the output file? , enter the file name or click the browse button to search for it. 1 for the design to compile successfully, always enable the dynamic reconfiguration controller for all the altgx instances in the design. figure 3?2. megawizard plug-in manager?altgx_reconfig (page 2) chapter 3: stratix iv altgx_reconfig megafunction user guide 3?3 dynamic reconfiguration ? november 2009 altera corporation stratix iv device handbook volume 3 figure 3?3 shows page 3 of the altgx_reconfig megawizard plug-in manager. from the drop-down menu, select the number of channels controlled by the dynamic reconfiguration controller. figure 3?3. megawizard plug-in manager?altgx_reconfig (reconfiguration settings) 3?4 chapter 3: stratix iv altgx_reconfig megafunction user guide dynamic reconfiguration stratix iv device handbook volume 3 ? november 2009 altera corporation table 3?1 describes the available options on page 3 of the megawizard plug-in manager for your altgx_reconfig custom megafunction variation. select the match project/default option if you want to change the device currently selected device family options. make your selections on page 3, then click next . tab le 3 ?1 . megawizard plug-in manager options (page 3) (part 1 of 2) altgx_reconfig setting description reference what is the number of channels controlled by the reconfig controller? determine the highest logical channel address among all the altgx instances connected to the altgx_reconfig instance. round it up to the next multiple of four and set that number in this option. depending on this setting, the altgx_reconfig megawizard plug-in manager generates the appropriate signal width for the interface signal ( reconfig_fromgxb ) between the altgx_reconfig and the altgx instances. it also gives the necessary bus width for all the selected physical media attachment (pma) signals. depending on the number of channels set, the resource estimate changes because this is a soft implementation that uses fabric logic resources. the resource estimate is shown in the bottom left of page 3 of the megawizard plug-in manager. ?total number of channels controlled by the altgx_reconfig instance? section of the stratix iv dynamic reconfiguration chapter. chapter 3: stratix iv altgx_reconfig megafunction user guide 3?5 dynamic reconfiguration ? november 2009 altera corporation stratix iv device handbook volume 3 what are the features to be reconfigured by the reconfig controller? this feature is always enabled by default: offset cancellation for receiver channels ?after the device powers up, the dynamic reconfiguration controller performs offset cancellation on the receiver portion of all the transceiver channels controlled by it. ?offset cancellation? section of the stratix iv dynamic reconfiguration chapter. these features are available for selection: analog controls ?allows dynamic reconfiguration of pma controls such as equalization, pre-emphasis, dc gain, and voltage offset differential (vod). data rate division in tx ?allows dynamic reconfiguration of the transmitter local divider settings to 1, 2, or 4. the transmitter channel data rate is reconfigured based on the local divider settings. channel and tx pll select/reconfig ?the following features are available under this option: ? cmu pll reconfiguration ?allows you to dynamically reconfigure the clock multiplier unit (cmu) phase-locked loop (pll) to a different data rate. ? channel and cmu pll reconfiguration ?allows the dynamic reconfiguration of the transceiver channel from one functional mode to another and also the cmu pll reconfiguration. ? channel reconfiguration with tx pll select ? allows you to select additional transmitter plls for the transceiver channel and reconfigure the functional mode of the channel. ? central control unit reconfiguration ?allows you to reconfigure bonded mode configurations from one to another. adaptive equalization control ?allows you to reconfigure the adaptive equalization hardware (aeq) in the receiver portion of the transceivers. there are three modes available: ? enable continuous mode for a single channel ?the equalization settings for the specified channel are continuously optimized by the aeq hardware. ? enable one time mode for a single channel ?a single stable equalization value is set up and locked for the specified channel by the aeq hardware. ? powerdown for a single channel ?the aeq hardware of the specified channel is put into standby mode by the aeq control logic (soft-ip) in the dynamic reconfiguration controller. ?pma controls reconfiguration mode details? section of the stratix iv dynamic reconfiguration chapter. ?data rate division in transmitter mode details? section of the stratix iv dynamic reconfiguration chapter. ?cmu pll reconfiguration mode details?? section of the stratix iv dynamic reconfiguration chapter. ?channel and cmu pll reconfiguration mode details? section of the stratix iv dynamic reconfiguration chapter. ?channel reconfiguration with tx pll select mode details? section of the stratix iv dynamic reconfiguration chapter. ?adaptive equalization (aeq)? section in the stratix iv dynamic reconfiguration chapter. what are the features to be reconfigured by the reconfig controller? eyeq control ?allows you to reconfigure the eyeq hardware in the receiver portion of the transceivers. ?eyeq? section in the stratix iv dynamic reconfiguration chapter. tab le 3 ?1 . megawizard plug-in manager options (page 3) (part 2 of 2) altgx_reconfig setting description reference 3?6 chapter 3: stratix iv altgx_reconfig megafunction user guide dynamic reconfiguration stratix iv device handbook volume 3 ? november 2009 altera corporation figure 3?4 shows page 4 of the altgx_reconfig megawizard plug-in manager. figure 3?4. megawizard plug-in manager?altgx_reconfig (analog controls) chapter 3: stratix iv altgx_reconfig megafunction user guide 3?7 dynamic reconfiguration ? november 2009 altera corporation stratix iv device handbook volume 3 table 3?2 describes the available options on page 4 of the megawizard plug-in manager for your altgx_reconfig custom megafunction variation. make your selections on page 4, then click next . tab le 3 ?2 . megawizard plug-in manager options (page 4) (part 1 of 2) altgx_reconfig setting description reference use ? logical_channel_ address ? port for analog controls reconfiguration this option is applicable only for analog controls reconfiguration and is available for selection when the number of channels controlled by the altgx_reconfig instance is more than one. the dynamic reconfiguration controller reconfigures only the channel whose logical channel address is specified at the logical_channel_address port. the width of this port is selected by the altgx_reconfig megawizard plug-in manager depending on the number of channels controlled by the dynamic reconfiguration controller. the maximum width of the logical_channel_address port is 9 bits. ?dynamic reconfiguration controller port list? and ?method 1?using the logical_channel_address port? sections of the stratix iv dynamic reconfiguration chapter. use the same control signal for all channels this option is available for selection when the number of channels controlled by the altgx_reconfig instance is more than one. when you enable this option, the dynamic reconfiguration controller writes the same control signals to all the channels connected to it. you cannot select this option if you enable the use 'logical_channel_address' port for analog controls reconfiguration option. method 2 and method 3 of the ?pma controls reconfiguration mode details? section of the stratix iv dynamic reconfiguration chapter. 3?8 chapter 3: stratix iv altgx_reconfig megafunction user guide dynamic reconfiguration stratix iv device handbook volume 3 ? november 2009 altera corporation write control the pma control ports available to write various analog settings to the transceiver channels controlled by the dynamic reconfiguration controller are as follows: tx_vodctrl ?v od ; 3 bits per channel tx_preemp_0t ?pre-emphasis control pre-tap; 5 bits per channel tx_preemp_1t ?pre-emphasis control 1st post-tap; 5 bits per channel tx_preemp_2t ?pre-emphasis control 2nd post-tap; 5 bits per channel rx_eqdcgain ?equalizer dc gain; 3 bits per channel rx_eqctrl ?equalizer control; 4 bits per channel these are optional signals. the signal widths are based on the setting you entered for the what is the number of channels controlled by the reconfig controller? option and whether you enabled the use 'logical_channel_address' port for analog controls reconfiguration option. the port width is also determined by the use the same control signal for all channels option. at least one of these pma control ports must be enabled to configure and use the dynamic reconfiguration controller. ?dynamically reconfiguring pma controls? section of the stratix iv dynamic reconfiguration chapter. read control the pma control ports available to read the existing values from the transceiver channels controlled by the dynamic reconfiguration controller are as follows: tx_vodctrl_out ?v od ; 3 bits per channel tx_preemp_0t_out ?pre-emphasis control pre-tap; 5 bits per channel tx_preemp1t_out ?pre-emphasis control 1st post-tap; 5 bits per channel tx_preemp_2t_out ?pre-emphasis control 2nd post-tap; 5 bits per channel rx_eqdcgain_out ?equalizer dc gain; 3 bits per channel rx_eqctrl_out ?equalizer control; 4 bits per channel these are optional signals. the signal widths are based on the setting you entered for the what is the number of channels controlled by the reconfig controller? option and whether you enabled the use 'logical_channel_address' port for analog controls reconfiguration option. the pma controls are available for selection only if you select the corresponding write control. read and write transactions cannot be performed simultaneously. tab le 3 ?2 . megawizard plug-in manager options (page 4) (part 2 of 2) altgx_reconfig setting description reference chapter 3: stratix iv altgx_reconfig megafunction user guide 3?9 dynamic reconfiguration ? november 2009 altera corporation stratix iv device handbook volume 3 figure 3?5 shows page 5 of the altgx_reconfig megawizard plug-in manager. table 3?4 describes the available options on page 5 of the megawizard plug-in manager for your altgx_reconfig custom megafunction variation. figure 3?5. megawizard plug-in manager?altgx_reconfig (channel and tx/pll reconfiguration) tab le 3 ?3 . megawizard plug-in manager options (page 5) (part 1 of 2) altgx_reconfig setting description reference enable continuous write of all the words needed for reconfiguration. for a continuous write operation, select the enable continuous write of all the words needed for reconfiguration option to pulse the write_all signal once to write an entire memory initialization file ( .mif ). ?dynamic reconfiguration controller port list? section in the stratix iv dynamic reconfiguration chapter . what is the read latency of the mif contents? this option is available only if you have selected the enable continuous write of all the words needed for reconfiguration option. enter the desired latency in terms of the reconfig_clk cycles it takes for each .mif word to be present at the reconfig_data port. for more information, refer to figure 3?6 . ?dynamic reconfiguration controller port list? section in the stratix iv dynamic reconfiguration chapter . 3?10 chapter 3: stratix iv altgx_reconfig megafunction user guide dynamic reconfiguration stratix iv device handbook volume 3 ? november 2009 altera corporation use ?reconfig_address_out? this option is enabled by default when you select the channel and tx pll select/reconfig option. the value on reconfig_address_out[5:0] indicates the address associated with the words in the .mif , which contains the dynamic reconfiguration instructions. the dynamic reconfiguration controller automatically increments the address at the end of each .mif write transaction. ?dynamic reconfiguration controller port list? section in the stratix iv dynamic reconfiguration chapter . use ?reconfig_address_en? when high, this optional output status signal indicates that the address used in the .mif write transaction cycle has changed. this signal is asserted when the .mif write transaction is completed (when the busy signal is de-asserted). ?dynamic reconfiguration controller port list? section in the stratix iv dynamic reconfiguration chapter . use ?reset_reconfig_address? when asserted, this optional control signal resets reconfig_address_out (the current reconfiguration address) to 0 . ?dynamic reconfiguration controller port list? section in the stratix iv dynamic reconfiguration chapter . use ?logical_tx_pll_sel? this is an optional control signal. the logical_tx_pll_sel[1:0] signal refers to the logical reference index of the cmu pll. the functionality of the signal depends on the feature activated, as shown below: cmu pll reconfiguration ?the corresponding cmu pll is reconfigured based on the value at logical_tx_pll_sel[1:0] . channel and cmu pll reconfiguration ?the corresponding cmu pll is reconfigured based on the value at this signal. the transceiver channel listens to the cmu pll selected by logical_tx_pll_sel[1:0] . channel reconfiguration with tx pll select ? the transceiver channel listens to the tx pll selected by logical_tx_pll_sel[1:0] . ?the logical_tx_pll_sel and logical_tx_pll_sel_en ports? section in the stratix iv dynamic reconfiguration chapter . use ?logical_tx_pll_sel_en? this is an optional control signal. when you enable this signal, the value set on the logical_tx_pll_sel[1:0] signal is valid only if the logical_tx_pll_sel_en is set to 1 . ?the logical_tx_pll_sel and logical_tx_pll_sel_en ports? section in the stratix iv dynamic reconfiguration chapter . tab le 3 ?3 . megawizard plug-in manager options (page 5) (part 2 of 2) altgx_reconfig setting description reference chapter 3: stratix iv altgx_reconfig megafunction user guide 3?11 dynamic reconfiguration ? november 2009 altera corporation stratix iv device handbook volume 3 figure 3?6 shows that the read latency of the .mif contents is 2, as it takes two reconfig_clk cycles for the .mif data to become available on the reconfig_data port after providing address on the reconfig_address_out port. figure 3?7 shows page 6 of the altgx_reconfig megawizard plug-in manager. figure 3?6. read latency reconfig_clock reconfig_address_out reconfig_data address 0 latency = 2 address 1 address 2 invalid data data 1 data 0 figure 3?7. megawizard plug-in manager?altgx_reconfig (error checks/data rate switch) 3?12 chapter 3: stratix iv altgx_reconfig megafunction user guide dynamic reconfiguration stratix iv device handbook volume 3 ? november 2009 altera corporation table 3?4 describes the available options on page 6 of the megawizard plug-in manager for your altgx_reconfig custom megafunction variation. make your selections on page 6, then click next . tab le 3 ?4 . megawizard plug-in manager options (page 6) altgx_reconfig setting description reference enable illegal mode checking when you select this option, the altgx_reconfig megawizard plug-in manager provides the error output port. the dynamic reconfiguration controller detects the error conditions within two reconfig_clk cycles , de-asserts the busy signal, and asserts the error signal for two reconfig_clk cycles . ?error indication in the altgx_reconfig megawizard plug-in manager? section of the stratix iv dynamic reconfiguration chapter. enable self recovery when you select this option, the controller automatically recovers if the operation did not complete within the expected time. the error signal is driven high whenever the controller performs a self recovery. ?error indication in the altgx_reconfig megawizard plug-in manager? section of the stratix iv dynamic reconfiguration chapter. use rate_switch_out port to read out the current data rate division the rate_switch_out[1:0] signal is available when you select data rate division in tx mode. you can read the existing local divider settings of a transmitter channel at this port. the decoding for this signal is listed below: 2?b00?division of 1 2?b01?division of 2 2?b10?division of 4 2?b11?not supported ?data rate division in tx' mode section in the stratix iv dynamic reconfiguration chapter. use the rx_tx_duplex_sel port to enable rx only, tx only or duplex configuration you can read or write the receiver and transmitter settings, only the receiver settings, or only the transmitter settings, based on the value you set at the rx_tx_duplex_sel[1:0] port; 2?b00?duplex mode 2?b01?rx only mode 2?b10?tx only mode 2?b11?unsupported value (do not use this value) if you disable the rx_tx_duplex_sel[1:0] port, the dynamic reconfiguration controller reads or writes both the receiver and transmitter settings. ?dynamically reconfiguring pma controls? section of the stratix iv dynamic reconfiguration chapter. chapter 3: stratix iv altgx_reconfig megafunction user guide 3?13 dynamic reconfiguration ? november 2009 altera corporation stratix iv device handbook volume 3 figure 3?8 shows page 7 (the simulation libraries page) of the megawizard plug-in manager, which is used for dynamic reconfiguration selection. make your selections, then click next . table 3?5 describes the available option on page 7 of the megawizard plug-in manager for your altgx_reconfig custom megafunction variation. make your selections on page 7, then click next . figure 3?8. megawizard plug-in manager?altgx_reconfig (simulation libraries) tab le 3 ?5 . megawizard plug-in manager options (page 7) altgx_reconfig setting description reference generate a netlist for synthesis area and timing estimation selecting this option generates a netlist file that third-party synthesis tools can use to estimate the timing and resource usage. ? 3?14 chapter 3: stratix iv altgx_reconfig megafunction user guide document revision history stratix iv device handbook volume 3 ? november 2009 altera corporation figure 3?9 shows page 8 (the last page) of the megawizard plug-in manager for the dynamic reconfiguration protocol set up. you can select optional files on this page. after you make your selections, click finish to generate the files. document revision history table 3?6 shows the revision history for this chapter. figure 3?9. megawizard plug-in manager?altgx_reconfig (summary) tab le 3 ?6 . document revision history date and document version changes made summary of changes november 2009, v3.0 updated tab le 3 ?1 . updated tab le 3 ?3 . added figure 3?6 . made minor text edits. ? june 2009, v2.1 updated table 3?3. added introductory sentences to improve search ability. minor text edits. ? march 2009, v2.0 updated screen shots. ? november 2008, v1.0 added chapter to the stratix iv device handbook ? 101 innovation drive san jose, ca 95134 www.altera.com siv5v4-4.6 volume 4 stratix iv device handbook stratix iv device handbook volume 4 stratix iv device handbook volume 4 november 2010 altera corporation ? 2010 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megacore, nios, quartus and stratix are reg. u.s. pat. & tm. off. and/or trademarks of altera corporation in the u.s. and other countries. all other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance with altera?s standard warranty, but reserves the right to make changes to any products and services at any time without notice . altera assumes no responsibility or liability arising out of the ap plication or use of any information, p rodu ct, or service described herein excep t as expressly ag reed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and bef ore plac ing orders for prod ucts or services. november 2010 altera corporation stratix iv device handbook volume 4 contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v section i. stratix iv device datasheet and addendum chapter 1. dc and switching characteristics for stratix iv devices electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?6 internal weak pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?10 i/o standard specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?11 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?14 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?14 transceiver performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?14 transceiver datapath pcs latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?43 core performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?43 clock tree specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?43 pll specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?44 dsp block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?45 trimatrix memory block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?46 configuration and jtag specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?49 temperature sensing diode specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?49 chip-wide reset (dev_clrn) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?50 periphery performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?50 high-speed i/o specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?50 oct calibration block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?57 duty cycle distortion (dcd) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?58 i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?58 programmable ioe delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?58 programmable output buffer delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?59 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?59 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?63 chapter 2. addendum to the stratix iv device handbook adaptive equalization (aeq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 decision feedback equalization (dfe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2 power-on reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 power-on reset specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 additional information how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 iv contents stratix iv device handbook volume 4 november 2010 altera corporation november 2010 altera corporation stratix iv device handbook volume 4 chapter revision dates the chapters in this document, stratix iv device handbook volume 4, were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1. dc and switching characteristics for stratix iv devices revised: november 2010 part number: siv54001-4.5 chapter 2. addendum to the stratix iv device handbook revised: september 2010 part number: siv54002-1.4 vi chapter revision dates stratix iv device handbook volume 4 november 2010 altera corporation november 2010 altera corporation stratix iv device handbook volume 4 section i. stratix iv device datasheet and addendum this section includes the following chapters: chapter 1, dc and switching characteristics for stratix iv devices chapter 2, addendum to the stratix iv device handbook revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook. i?2 section i: stratix iv device datasheet and addendum stratix iv device handbook volume 4 november 2010 altera corporation stratix iv device handbook volume 4 november 2010 siv54001-4.5 subscribe ? 2010 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megacore, nios, quartus and stratix are reg. u.s. pat. & tm. off. and/or trademarks of altera corporation in the u.s. and other countries. all other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance with altera?s standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability aris ing out of the app lication or u se of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advi sed to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 1. dc and switching characteristics for stratix iv devices electrical characteristics this chapter covers the electrical and switching characteristics for stratix ? iv devices. electrical characteristics include operating conditions and power consumption. switching characteristics include transceiver specifications, core, and periphery performance. this chapter also describes i/o timing, including programmable i/o element (ioe) delay and programmable output buffer delay. f for information regarding the densities and packages of devices in the stratix iv family, refer to table 1-1 and table 1-2 of the stratix iv device family overview chapter. operating conditions when you use stratix iv devices, they are rated according to a set of defined parameters. to maintain the highest possible performance and reliability of the stratix iv devices, you must consider the operating requirements described in this chapter. stratix iv devices are offered in both commercial and industrial grades. commercial devices are offered in ?2 (fastest), ?2, ?3, and ?4 speed grades. industrial devices are offered in ?1, ?2, ?3, and ?4 speed grades. absolute maximum ratings absolute maximum ratings define the maximum operating conditions for stratix iv devices. the values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. the functional operation of the device is not implied for these conditions. c conditions other than those listed in table 1?1 , table 1?2 , and table 1?3 may cause permanent damage to the device. additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. table 1?1. absolute maximum ratings for stratix iv devices (part 1 of 2) symbol description minimum maximum unit v cc core voltage and periphery circuitry power supply -0.5 1.35 v v cccb power supply to the configuration ram bits -0.5 1.8 v v ccpgm configuration pins power supply -0.5 3.75 v v ccaux auxiliary supply for the programmable power technology -0.5 3.75 v v ccbat battery back-up power supply for design security volatile key register -0.5 3.75 v v ccpd i/o pre-driver power supply -0.5 3.75 v v ccio i/o power supply -0.5 3.9 v november 2010 siv54001-4.5 1?2 chapter 1: dc and switching characteristics for stratix iv devices electrical characteristics stratix iv device handbook volume 4 november 2010 altera corporation v cc_clkin differential clock input power supply -0.5 3.75 v v ccd_pll pll digital power supply -0.5 1.35 v v cca_pll pll analog power supply -0.5 3.75 v v i dc input voltage -0.5 4.0 v i out dc output current per pin -25 40 ma t j operating junction temperature -55 125 c t stg storage temperature (no bias) -65 150 c table 1?1. absolute maximum ratings for stratix iv devices (part 2 of 2) symbol description minimum maximum unit table 1?2. transceiver power supply absolute maximum ratings for stratix iv gx devices symbol description minimum maximum unit v cca_l transceiver high voltage power (left side) -0.5 3.75 v v cca_r transceiver high voltage power (right side) -0.5 3.75 v v cchip_l transceiver hip digital power (left side) -0.5 1.35 v v cchip_r transceiver hip digital power (right side) -0.5 1.35 v v ccr_l receiver power (left side) -0.5 1.35 v v ccr_r receiver power (right side) -0.5 1.35 v v cct_l transmitter power (left side) -0.5 1.35 v v cct_r transmitter power (right side) -0.5 1.35 v v ccl_gxbln (1) transceiver clock power (left side) -0.5 1.35 v v ccl_gxbrn (1) transceiver clock power (right side) -0.5 1.35 v v cch_gxbln (1) transmitter output buffer power (left side) -0.5 1.8 v v cch_gxbrn (1) transmitter output buffer power (right side) -0.5 1.8 v note to tab l e 1 ?2 : (1) n = 0, 1, 2, or 3. table 1?3. transceiver power supply absolute maximum ratings for stratix iv gt devices (note 1) (part 1 of 2) symbol description minimum maximum unit v cca_l transceiver high voltage power (left side) -0.5 3.75 v v cca_r transceiver high voltage power (right side) -0.5 3.75 v v cchip_l transceiver hip digital power (left side) -0.5 1.35 v v cchip_r transceiver hip digital power (right side) -0.5 1.35 v v ccr_l receiver power (left side) -0.5 1.35 v v ccr_r receiver power (right side) -0.5 1.35 v v cct_l transmitter power (left side) -0.5 1.35 v v cct_r transmitter power (right side) -0.5 1.35 v v ccl_gxbln (2) transceiver clock power (left side) -0.5 1.35 v v ccl_gxbrn (2) transceiver clock power (right side) -0.5 1.35 v v cch_gxbln (2) transmitter output buffer power (left side) -0.5 1.8 v chapter 1: dc and switching characteristics for stratix iv devices 1?3 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 maximum allowed overshoot and undershoot voltage during transitions, input signals may overshoot to the voltage shown in table 1?4 and undershoot to -2.0 v for input currents less than 100 ma and periods shorter than 20 ns. table 1?4 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. the maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. a dc signal is equivalent to 100% duty cycle. for example, a signal that overshoots to 4.3 v can only be at 4.3 v for ~5% over the lifetime of the device; for a device lifetime of 10 years, this amounts to half of a year. v cch_gxbrn (2) transmitter output buffer power (right side) -0.5 1.8 v notes to ta bl e 1? 3 : (1) for the absolute maximum ratings for stratix iv gt engineering sample (es1) devices, contact your local altera sales represe ntative. (2) n = 0, 1, 2, or 3. table 1?3. transceiver power supply absolute maximum ratings for stratix iv gt devices (note 1) (part 2 of 2) symbol description minimum maximum unit table 1?4. maximum allowed overshoot during transitions symbol description condition (v) overshoot duration as % of high time unit vi (ac) ac input voltage 4.0 100.000 % 4.05 79.330 % 4.1 46.270 % 4.15 27.030 % 4.2 15.800 % 4.25 9.240 % 4.3 5.410 % 4.35 3.160 % 4.4 1.850 % 4.45 1.080 % 4.5 0.630 % 4.55 0.370 % 4.6 0.220 % chapter 1: dc and switching characteristics for stratix iv devices 1?4 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 recommended operating conditions this section lists the functional operation limits for ac and dc parameters for stratix iv devices. table 1?5 lists the steady-state voltage and current values expected from stratix iv devices. power supply ramps must all be strictly monotonic, without plateaus. table 1?5. recommended operating conditions for stratix iv devices (part 1 of 2) symbol description condition minimum typical maximum unit v cc (stratix iv gx and stratix iv e) core voltage and periphery circuitry power supply ? 0.87 0.90 0.93 v v cc (stratix iv gt) core voltage and periphery circuitry power supply ? 0.92 0.95 0.98 v v cccb power supply to the configuration ram bits ? 1.45 1.50 1.55 v v ccaux auxiliary supply for the programmable power technology ? 2.375 2.5 2.625 v v ccpd (2) i/o pre-driver (3.0 v) power supply ? 2.85 3.0 3.15 v i/o pre-driver (2.5 v) power supply ? 2.375 2.5 2.625 v v ccio i/o buffers (3.0 v) power supply ? 2.85 3.0 3.15 v i/o buffers (2.5 v) power supply ? 2.375 2.5 2.625 v i/o buffers (1.8 v) power supply ? 1.71 1.8 1.89 v i/o buffers (1.5 v) power supply ? 1.425 1.5 1.575 v i/o buffers (1.2 v) power supply ? 1.14 1.2 1.26 v v ccpgm configuration pins (3.0 v) power supply ? 2.85 3.0 3.15 v configuration pins (2.5 v) power supply ? 2.375 2.5 2.625 v configuration pins (1.8 v) power supply ? 1.71 1.8 1.89 v v cca_pll pll analog voltage regulator power supply ? 2.375 2.5 2.625 v v ccd_pll (stratix iv gx and stratix iv e) pll digital voltage regulator power supply ? 0.87 0.90 0.93 v v ccd_pll (stratix iv gt) pll digital voltage regulator power supply ? 0.92 0.95 0.98 v v cc_clkin differential clock input power supply ? 2.375 2.5 2.625 v v ccbat (1) battery back-up power supply (for design security volatile key register) ?1.2?3.3v v i dc input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v t j (stratix iv gx and stratix iv e) operating junction temperature commercial 0 ? 85 c industrial ?40 ? 100 c t j (stratix iv gt) operating junction temperature industrial 0 ? 100 c chapter 1: dc and switching characteristics for stratix iv devices 1?5 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 table 1?6 lists the transceiver power supply recommended operating conditions for stratix iv gx devices. table 1?7 lists the recommended operating conditions for the stratix iv gt transceiver power supply. t ramp power supply ramp time normal por (porsel=0) 0.05 ? 100 ms fast por (porsel=1) 0.05 ? 4 ms notes to ta bl e 1? 5 : (1) altera recommends a 3.0-v nominal battery voltage when connecting v ccbat to a battery for volatile key backup. if you do not use the volatile security key, you may connect the v ccbat to either gnd or a 3.0-v power supply. (2) v ccpd must be 2.5 v when v ccio is 2.5, 1.8, 1.5, or 1.2 v. v ccpd must be 3.0 v when v ccio is 3.0 v. table 1?5. recommended operating conditions for stratix iv devices (part 2 of 2) symbol description condition minimum typical maximum unit table 1?6. transceiver power supply operating conditions for stratix iv gx devices (note 4) symbol description minimum typical maximum unit v cca_l transceiver high voltage power (left side) 2.85/2.375 3.0/2.5 (2) 3.15/2.625 v v cca_r transceiver high voltage power (right side) v cchip_l transceiver hip digital power (left side) 0.87 0.9 0.93 v v cchip_r transceiver hip digital power (right side) 0.87 0.9 0.93 v v ccr_l receiver power (left side) 1.05 1.1 1.15 v v ccr_r receiver power (right side) 1.05 1.1 1.15 v v cct_l transmitter power (left side) 1.05 1.1 1.15 v v cct_r transmitter power (right side) 1.05 1.1 1.15 v v ccl_gxbln (1) transceiver clock power (left side) 1.05 1.1 1.15 v v ccl_gxbrn (1) transceiver clock power (right side) 1.05 1.1 1.15 v v cch_gxbln (1) transmitter output buffer power (left side) 1.33/1.425 1.4/1.5 (3) 1.47/1.575 v v cch_gxbrn (1) transmitter output buffer power (right side) notes to ta bl e 1? 6 : (1) n = 0, 1, 2, or 3. (2) v cca_l/r must be connected to a 3.0-v supply if the clock multiplier unit (cmu) phase-locked loop (pll), receiver clock data recovery ( cdr), or both, are configured at a base data rate > 4.25 g bps. for data rates up to 4.25 gbps, you can connect v cca_l/r to either 3.0 v or 2.5 v. (3) v cch_gxbl/r must be connected to a 1.4-v supply if the transmitter channel data rate is > 6.25 gbps. for data rates up to 6.25 gbps, you can connect v cch_gxbl/r to either 1.4 v or 1.5 v. (4) transceiver power supplies do not have power-on-reset (por) circuitry. after initial power-up, violating the transceiver pow er supply operating conditions could lead to unpredictable link behavior. table 1?7. transceiver power supply operating conditions for stratix iv gt devices (note 1) , (3) symbol description minimum typical maximum unit v cca_l transceiver high voltage power (left side) 3.17 3.3 3.43 v v cca_r transceiver high voltage power (right side) 3.17 3.3 3.43 v v cchip_l transceiver hip digital power (left side) 0.92 0.95 0.98 v v cchip_r transceiver hip digital power (right side) 0.92 0.95 0.98 v chapter 1: dc and switching characteristics for stratix iv devices 1?6 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 dc characteristics this section lists the supply current, i/o pin leakage current, input pin capacitance, on-chip termination tolerance, and hot socketing specifications. supply current standby current is the current drawn from the respective power rails used for power budgeting. use the excel-based early power estimator (epe) to get supply current estimates for your design because these currents vary greatly with the resources you use. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook . i/o pin leakage current table 1?8 lists the stratix iv i/o pin leakage current specifications. v ccr_l receiver power (left side) 1.15 1.2 1.25 v v ccr_r receiver power (right side) 1.15 1.2 1.25 v v cct_l transmitter power (left side) 1.15 1.2 1.25 v v cct_r transmitter power (right side) 1.15 1.2 1.25 v v ccl_gxbln (2) transceiver clock power (left side) 1.15 1.2 1.25 v v ccl_gxbrn (2) transceiver clock power (right side) 1.15 1.2 1.25 v v cch_gxbln (2) transmitter output buffer power (left side) 1.33 1.4 1.47 v v cch_gxbrn (2) transmitter output buffer power (right side) 1.33 1.4 1.47 v notes to ta bl e 1? 7 : (1) for the recommended operating conditions for stratix iv gt engineering sample (es1) devices, contact your local altera sales representative. (2) n = 0, 1, 2, or 3. (3) transceiver power supplies do not have power-on-reset (por) circuitry. after initial power-up, violating the transceiver pow er supply operating conditions could lead to unpredictable link behavior. table 1?7. transceiver power supply operating conditions for stratix iv gt devices (note 1) , (3) symbol description minimum typical maximum unit table 1?8. i/o pin leakage current for stratix iv devices symbol description conditions min typ max unit i i input pin v i = 0v to v cciomax -20 ? 20 a i oz tri-stated i/o pin v o = 0v to v cciomax -20 ? 20 a chapter 1: dc and switching characteristics for stratix iv devices 1?7 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 bus hold specifications table 1?9 lists the stratix iv device family bus hold specifications. on-chip termination (oct) specifications if you enable oct calibration, calibration is automatically performed at power-up for i/os connected to the calibration block. table 1?10 lists the stratix iv oct termination calibration accuracy specifications. table 1?9. bus hold parameters parameter symbol conditions v ccio unit 1.2 v1.5 v1.8 v2.5 v3.0 v min max min max min max min max min max low sustaining current i susl v in > v il (maximum) 22.5 ? 25.0 ? 30.0 ? 50.0 ? 70.0 ? a high sustaining current i sush v in < v ih (minimum) -22.5?-25.0?-30.0?-50.0?-70.0? a low overdrive current i odl 0v < v in < v ccio ?120?160?200?300?500a high overdrive current i odh 0v < v in < v ccio ? -120 ? -160 ? -200 ? -300 ? -500 a bus-hold trip point v tr ip ? 0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 v table 1?10. on-chip termination calibration accuracy specifications for stratix iv devices (part 1 of 2) (note 1) symbol description conditions calibration accuracy unit c2 c3,i3 c4,i4 25- ? r s (2) 3.0, 2.5, 1.8, 1.5, 1.2 internal series termination with calibration (25- ? setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 8 8 8 % 50- ? r s 3.0, 2.5, 1.8, 1.5, 1.2 internal series termination with calibration (50- ? setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 8 8 8 % 50- ? r t 2.5, 1.8, 1.5, 1.2 internal parallel termination with calibration (50- ? setting) v ccio = 2.5, 1.8, 1.5, 1.2 v 10 10 10 % 20- ? , 40- ? , and 60- ? r s (3) 3.0, 2.5, 1.8, 1.5, 1.2 expanded range for internal series termination with calibration (20- ? , 40- ??? and 60- ? r s setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 10 10 10 % chapter 1: dc and switching characteristics for stratix iv devices 1?8 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 the calibration accuracy for calibrated series and parallel octs are applicable at the moment of calibration. when process, voltage, and temperature (pvt) conditions change after calibration, the tolerance may change. table 1?11 lists the stratix iv oct without calibration resistance tolerance to pvt changes. 25- ? r s_left_shift 3.0, 2.5, 1.8, 1.5, 1.2 internal left shift series termination with calibration (25- ? r s_left_shift setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 10 10 10 % notes to ta bl e 1? 10 : (1) oct calibration accuracy is valid at the time of calibration only. (2) 25- ? r s is not supported for 1.5 v and 1.2 v in row i/o. (3) 20- ? r s is not supported for 1.5 v and 1.2 v in row i/o. table 1?10. on-chip termination calibration accuracy specifications for stratix iv devices (part 2 of 2) (note 1) symbol description conditions calibration accuracy unit c2 c3,i3 c4,i4 table 1?11. on-chip termination without calibration resistance tolerance specifications for stratix iv devices symbol description conditions resistance tolerance unit c2 c3,i3 c4,i4 25- ? r s 3.0 and 2.5 internal series termination without calibration (25- ? setting) v ccio = 3.0 and 2.5 v 30 40 40 % 25- ? r s 1.8 and 1.5 internal series termination without calibration (25- ? setting) v ccio = 1.8 and 1.5 v 30 40 40 % 25- ? r s 1.2 internal series termination without calibration (25- ? setting) v ccio = 1.2 v 35 50 50 % 50- ? r s 3.0 and 2.5 internal series termination without calibration (50- ? setting) v ccio = 3.0 and 2.5 v 30 40 40 % 50- ? r s 1.8 and 1.5 internal series termination without calibration (50- ? setting) v ccio = 1.8 and 1.5 v 30 40 40 % 50- ? r s 1.2 internal series termination without calibration (50- ? setting) v ccio = 1.2 v 35 50 50 % 100- ? r d 2.5 internal differential termination (100- ? setting) v ccio = 2.5 v 25 25 25 % chapter 1: dc and switching characteristics for stratix iv devices 1?9 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 oct calibration is automatically performed at power-up for oct-enabled i/os. table 1?12 lists oct variation with temperature and voltage after power-up calibration. use table 1?12 to determine the oct variation after power-up calibration and equation 1?1 to determine the oct variation without re-calibration. table 1?12 lists the on-chip termination variation after the power-up calibration. pin capacitance table 1?13 lists the stratix iv device family pin capacitance. equation 1?1. oct variation without re-calibration (note 1) , (2) , (3) , (4) , (5) , (6) notes to equation 1?1 : (1) the r oc t value calculated from equation 1?1 shows the range of oct resistance with the variation of temperature and v ccio . (2) r scal is the oct resistance value at power-up. (3) ? t is the variation of temperature with respect to the temperature at power-up. (4) ? v is the variation of voltage with respect to the v ccio at power-up. (5) dr/dt is the percentage change of r scal with temperature. (6) dr/dv is the percentage change of r scal with voltage. table 1?12. on-chip termination variation after power-up calibration (note 1) symbol description v ccio (v) typical unit dr/dv oct variation with voltage without re-calibration 3.0 0.0297 %/mv 2.5 0.0344 1.8 0.0499 1.5 0.0744 1.2 0.1241 dr/dt oct variation with temperature without re-calibration 3.0 0.189 %/c 2.5 0.208 1.8 0.266 1.5 0.273 1.2 0.317 note to tab l e 1 ?1 2 : (1) valid for v ccio range of 5% and temperature range of 0 to 85c. r oct r scal 1 dr dt ------- ? t ? ?? dr dv ------- ? v ? ?? ? + ?? ?? = table 1?13. pin capacitance for stratix iv devices (part 1 of 2) symbol description typical unit c iotb input capacitance on the top and bottom i/o pins 4 pf c iolr input capacitance on the left and right i/o pins 4 pf c clktb input capacitance on the top and bottom non-dedicated clock input pins 4 pf c clklr input capacitance on the left and right non-dedicated clock input pins 4 pf chapter 1: dc and switching characteristics for stratix iv devices 1?10 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 hot socketing table 1?14 lists the hot socketing specifications for stratix iv devices. internal weak pull-up resistor table 1?15 lists the weak pull-up resistor values for stratix iv devices. c outfb input capacitance on the dual-purpose clock output and feedback pins 5 pf c clk1 , c clk3 , c clk8 , and c clk10 input capacitance for dedicated clock input pins 2 pf table 1?13. pin capacitance for stratix iv devices (part 2 of 2) symbol description typical unit table 1?14. hot socketing specifications for stratix iv devices symbol description maximum i iopin (dc) dc current per i/o pin 300 ? a i iopin (ac) ac current per i/o pin 8 ma (1) i xc vr- tx ( dc) (2) dc current per transceiver tx pin 100 ma i xc vr- rx ( dc) (2) dc current per transceiver rx pin 50 ma notes to ta bl e 1? 14 : (1) the i/o ramp rate is 10 ns or more. for ramp rates faster than 10 ns, |i iopin | = c dv/dt, in which c is the i/o pin capacitance and dv/dt is the slew rate. (2) these specifications are preliminary. table 1?15. internal weak pull-up resistor for stratix iv devices (note 1) , (3) symbol description conditions min typ max unit r pu value of the i/o pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled. v ccio = 3.0 v 5% (2) ?25?k ? v ccio = 2.5 v 5% (2) ?25?k ? v ccio = 1.8 v 5% (2) ?25?k ? v ccio = 1.5 v 5% (2) ?25?k ? v ccio = 1.2 v 5% (2) ?25?k ? notes to ta bl e 1? 15 : (1) all i/o pins have an option to enable weak pull-up excep t configuration, test, and jtag pins. (2) pin pull-up resistance values may be lower if an external source drives the pin higher than v ccio . (3) the internal weak pull-down feature is only available for the jtag tck pin. the typical value for this internal weak pull-down resistor is approximately 25 k ?? chapter 1: dc and switching characteristics for stratix iv devices 1?11 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 i/o standard specifications table 1?16 through table 1?21 list the input voltage (v ih and v il ), output voltage (v oh and v ol ), and current drive characteristics (i oh and i ol ) for various i/o standards supported by stratix iv devices. these tables also show the stratix iv device family i/o standard specifications. v ol and v oh values are valid at the corresponding i oh and i ol , respectively. for an explanation of terms used in table 1?16 through table 1?21 , refer to ?glossary? on page 1?59 . table 1?16. single-ended i/o standards i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min lvttl 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.4 2.4 2 -2 lvcmos 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.2 v ccio - 0.2 0.1 -0.1 2.5 v 2.375 2.5 2.625 -0.3 0.7 1.7 3.6 0.4 2 1 -1 1.8 v 1.71 1.8 1.89 -0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.45 v ccio - 0.45 2-2 1.5 v 1.425 1.5 1.575 -0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.25 * v ccio 0.75 * v ccio 2-2 1.2 v 1.14 1.2 1.26 -0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.25 * v ccio 0.75 * v ccio 2-2 3.0-v pci 2.85 3 3.15 ? 0.3 * v ccio 0.5 * v ccio 3.6 0.1 * v ccio 0.9 * v ccio 1.5 -0.5 3.0-v pci-x 2.85 3 3.15 ? 0.35 * v ccio 0.5 * v ccio ? 0.1 * v ccio 0.9 * v ccio 1.5 -0.5 table 1?17. single-ended sstl and hstl i/o reference voltage specifications i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio v ref - 0.04 v ref v ref + 0.04 sstl-18 class i, ii 1.71 1.8 1.89 0.833 0.9 0.969 v ref - 0.04 v ref v ref + 0.04 sstl-15 class i, ii 1.425 1.5 1.575 0.47 * v ccio 0.5 * v ccio 0.53 * v ccio 0.47 * v ccio v ref 0.53 * v ccio hstl-18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 ? v ccio /2 ? hstl-15 class i, ii 1.425 1.5 1.575 0.68 0.75 0.9 ? v ccio /2 ? hstl-12 class i, ii 1.14 1.2 1.26 0.47 * v ccio 0.5 * v ccio 0.53 * v ccio ?v ccio /2 ? chapter 1: dc and switching characteristics for stratix iv devices 1?12 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 table 1?18. single-ended sstl and hstl i/o standards signal specifications i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min sstl-2 class i -0.3 v ref - 0.15 v ref + 0.15 v ccio + 0.3 v ref - 0.31 v ref + 0.31 v tt - 0.57 v tt + 0.57 8.1 -8.1 sstl-2 class ii -0.3 v ref - 0.15 v ref + 0.15 v ccio + 0.3 v ref - 0.31 v ref + 0.31 v tt - 0.76 v tt + 0.76 16.2 -16.2 sstl-18 class i -0.3 v ref - 0.125 v ref + 0.125 v ccio + 0.3 v ref - 0.25 v ref + 0.25 v tt - 0.475 v tt + 0.475 6.7 -6.7 sstl-18 class ii -0.3 v ref - 0.125 v ref + 0.125 v ccio + 0.3 v ref - 0.25 v ref + 0.25 0.28 v ccio - 0.28 13.4 -13.4 sstl-15 class i ? v ref - 0.1 v ref + 0.1 ? v ref - 0.175 v ref + 0.175 0.2 * v ccio 0.8 * v ccio 8-8 sstl-15 class ii ? v ref - 0.1 v ref + 0.1 ? v ref - 0.175 v ref + 0.175 0.2 * v ccio 0.8 * v ccio 16 -16 hstl-18 class i ? v ref - 0.1 v ref + 0.1 ?v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 8-8 hstl-18 class ii ? v ref - 0.1 v ref + 0.1 ?v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 16 -16 hstl-15 class i ? v ref - 0.1 v ref + 0.1 ?v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 8-8 hstl-15 class ii ? v ref - 0.1 v ref + 0.1 ?v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 16 -16 hstl-12 class i -0.15 v ref - 0.08 v ref + 0.08 v ccio + 0.15 v ref - 0.15 v ref + 0.15 0.25* v ccio 0.75* v ccio 8-8 hstl-12 class ii -0.15 v ref - 0.08 v ref + 0.08 v ccio + 0.15 v ref - 0.15 v ref + 0.15 0.25* v ccio 0.75* v ccio 16 -16 table 1?19. differential sstl i/o standards i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) v ox(ac) (v) min typ max min max min typ max min max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.3 v ccio + 0.6 v ccio /2 - 0.2 ? v ccio /2 + 0.2 0.62 v ccio + 0.6 v ccio /2 - 0.15 ? v ccio /2 + 0.15 sstl-18 class i, ii 1.71 1.8 1.89 0.25 v ccio + 0.6 v ccio /2 - 0.175 ? v ccio /2 + 0.175 0.5 v ccio + 0.6 v ccio /2 - 0.125 ? v ccio /2 + 0.125 sstl-15 class i, ii 1.425 1.5 1.575 0.2 ? ? v ccio /2 ? 0.35 ? ? v ccio /2 ? chapter 1: dc and switching characteristics for stratix iv devices 1?13 electrical characteristics november 2010 altera corporation stratix iv device handbook volume 4 table 1?20. differential hstl i/o standards i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max min max hstl-18 class i 1.71 1.8 1.89 0.2 ? 0.78 ? 1.12 0.78 ? 1.12 0.4 ? hstl-15 class i, ii 1.425 1.5 1.575 0.2 ? 0.68 ? 0.9 0.68 ? 0.9 0.4 ? hstl-12 class i, ii 1.14 1.2 1.26 0.16 v ccio + 0.3 ? 0.5* v ccio ? 0.4* v ccio 0.5* v ccio 0.6* v ccio 0.3 v ccio + 0.48 table 1?21. differential i/o standard specifications (note 1) , (2) i/o standard v ccio (v) v id (mv) v ic m(dc ) (v) v od (v) (3) v ocm (v) (3) min typ max min condition max min condition max min typ ma x min typ max pcml transmitter, receiver, and input reference clock pins of high-speed transceivers use pcml i/o standard. for transmitter, receiver, and reference clock i/o pin specifications, refer to table 1?22 on page 1?14 and table 1?23 on page 1?23 . 2.5 v lvds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v ?0.05 d max ? 700 mbps 1.8 0.247 ? 0.6 1.125 1.25 1.375 ?1.05 d max > 700 mbps 1.55 0.247 ? 0.6 1.125 1.25 1.375 2.5 v lvds (vio) 2.375 2.5 2.625 100 v cm = 1.25 v ?0.05 d max ? 700 mbps 1.8 0.247 ? 0.6 1 1.25 1.5 ?1.05 d max > 700 mbps 1.55 0.247 ? 0.6 1 1.25 1.5 rsds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.3 ? 1.4 0.1 0.2 0.6 0.5 1.2 1.4 rsds (vio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.3 ? 1.4 0.1 0.2 0.6 0.5 1.2 1.5 mini- lvds (hio) 2.375 2.5 2.625 200 ? 600 0.4 ? 1.325 0.25 ? 0.6 1 1.2 1.4 mini- lvds (vio) 2.375 2.5 2.625 200 ? 600 0.4 ? 1.325 0.25 ? 0.6 1 1.2 1.5 lvpecl 2.375 2.5 2.625 300 ? ? 0.6 d max ? 700 mbps 1.8 (4) ?????? 2.375 2.5 2.625 300 ? ? 1 d max > 700 mbps 1.6 (4) ?????? notes to ta bl e 1? 21 : (1) vertical i/o (vio) is top and bottom i/os; horizontal i/o (hio) is left and right i/os. (2) 1.4-v/1.5-v pcml transceiver i/o standard specifications are described in ?transceiver performance specifications? on page 1?14 . (3) rl range: 90 ? rl ? 110 ? . (4) for d max > 700 mbps, the minimum input voltage is 0.85 v; the maximum input voltage is 1.75 v. for f max ? 700 mbps, the minimum input voltage is 0.45 v; the maximum input voltage is 1.95 v. chapter 1: dc and switching characteristics for stratix iv devices 1?14 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 power consumption altera offers two ways to estimate power consumption for a design: the excel-based early power estimator and the quartus ? ii powerplay power analyzer feature. 1 you typically use the interactive excel-based early power estimator before designing the fpga to get a magnitude estimate of the device power. the quartus ii powerplay power analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. the powerplay power analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. f for more information about power estimation tools, refer to the powerplay early power estimator user guide for stratix iii and stratix iv fpgas and the powerplay power analysis chapter in the quartus ii handbook . switching characteristics this section provides performance characteristics of stratix iv core and periphery blocks for commercial grade devices. these characteristics can be designated as preliminary or final. preliminary characteristics are created using simulation results, process data, and other known parameters. the title of these tables show the designation as ?preliminary?. final numbers are based on actual silicon characterization and testing. the numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. there are no designations on finalized tables. transceiver performance specifications this section describes transceiver performance specifications. table 1?22 lists the stratix iv gx transceiver specifications. table 1?22. transceiver specifications for stratix iv gx devices (part 1 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/industrial and ?2 commercial speed grade (1) ?4 commercial/industrial speed grade unit min typ max min typ max min typ max reference clock supported i/o standards 1.2 v pcml, 1.5 v pcml, 2.5 v pcml, differential lvpecl, lvds, hcsl input frequency from refclk input pins ? 50? 69750? 69750?637.5mhz chapter 1: dc and switching characteristics for stratix iv devices 1?15 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 phase frequency detector (cmu pll and receiver cdr) ? 50? 42550? 32550?325mhz absolute v max for a refclk pin ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v operational v max for a refclk pin ? ? ? 1.5 ? ? 1.5 ? ? 1.5 v absolute v min for a refclk pin ? -0.4? ?-0.4? ?-0.4? ? v rise/fall time (19) ? ? ? 0.2 ? ? 0.2 ? ? 0.2 ui duty cycle ? 45 ? 55 45 ? 55 45 ? 55 % peak-to-peak differential input voltage ? 200 ? 1600 200 ? 1600 200 ? 1600 mv spread-spectrum modulating clock frequency pcie 30? 3330 ? 3330?33khz spread-spectrum downspread pcie ? 0 to -0.5% ?? 0 to -0.5% ?? 0 to -0.5% ?? on-chip termination resistors ? ? 100 ? ? 100 ? ? 100 ? ? v icm (ac coupled) ? 1100 10% 1100 10% 1100 10% mv v icm (dc coupled) hcsl i/o standard for pcie reference clock 250 ? 550 250 ? 550 250 ? 550 mv transmitter refclk phase noise 10 hz ? ? -50 ? ? -50 ? ? -50 dbc/hz 100 hz ? ? -80 ? ? -80 ? ? -80 dbc/hz 1 khz ? ? -110 ? ? -110 ? ? -110 dbc/hz 10 khz ? ? -120 ? ? -120 ? ? -120 dbc/hz 100 khz ? ? -120 ? ? -120 ? ? -120 dbc/hz ? 1 mhz ? ? -130 ? ? -130 ? ? -130 dbc/hz r ref ?? 2000 1% ?? 2000 1% ?? 2000 1% ? ? transceiver clocks calibration block clock frequency ? 10? 12510? 12510?125mhz fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? ? 125 ? mhz table 1?22. transceiver specifications for stratix iv gx devices (part 2 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/industrial and ?2 commercial speed grade (1) ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?16 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 reconfig_clk clock frequency dynamic reconfiguration clock frequency 2.5/ 37.5 (2) ?50 2.5/ 37.5 (2) ?50 2.5/ 37.5 (2) ?50 ? delta time between reconfig_clks (17) ???2??2??2ms transceiver block minimum power-down ( gxb_powerdown ) pulse width ?1??1??1??s receiver supported i/o standards 1.4 v pcml, 1.5 v pcml, 2.5 v pcml, lvpecl, lvds data rate (single width, non-pma direct) ? 600 ? 3750 600 ? 3750 600 ? 3750 mbps data rate (double width, non-pma direct) ? 1000 ? 8500 1000 ? 6500 1000 ? 6375 (20) mbps data rate (single width, pma direct) ? 600 ? 3250 600 ? 3250 600 ? 3250 mbps data rate (double width, pma direct) ? 1000 ? 6500 1000 ? 6500 1000 ? 6375 mbps absolute v max for a receiver pin (3) ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v operational v max for a receiver pin ? ? ? 1.5 ? ? 1.5 ? ? 1.5 v absolute v min for a receiver pin ? -0.4? ?-0.4? ?-0.4? ? v maximum peak-to-peak differential input voltage v id (diff p-p) before device configuration ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v maximum peak-to-peak differential input voltage v id (diff p-p) after device configuration v icm = 0.82 v setting ? ? 2.7 ? ? 2.7 ? ? 2.7 v v icm =1.1 v setting (4) ? ? 1.6 ? ? 1.6 ? ? 1.6 v table 1?22. transceiver specifications for stratix iv gx devices (part 3 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/industrial and ?2 commercial speed grade (1) ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?17 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 minimum differential eye opening at receiver serial input pins (18) data rate = 600 mbps to 5gbps equalization = 0 dc gain = 0 db 100 ? ? 100 ? ? 165 ? ? mv data rate >5gbps equalization = 0 dc gain = 0 db 165 ? ? 165 ? ? 165 ? ? mv v icm v icm = 0.82 v setting 820 10% 820 10% 820 10% mv v icm = 1.1 v setting (4) 1100 10% 1100 10% 1100 10% mv receiver dc coupling support ? for more information about receiver dc coupling support, refer to the ?dc-coupled links? section in the stratix iv transceiver architecture chapter. differential on-chip termination resistors 85 ?? setting 85 20% 85 20% 85 20% ? 100 ?? setting 100 20% 100 20% 100 20% ? 120 ?? setting 120 20% 120 20% 120 20% ? 150- ? setting 150 20% 150 20% 150 20% ? differential and common mode return loss pcie (gen 1 and gen 2), xaui, higig+, cei sr/lr, serial rapidio sr/lr, cpri lv/hv, obsai, sata compliant ? programmable ppm detector (5) ? 62.5, 100, 125, 200, 250, 300, 500, 1000 ppm run length ? ? ? 200 ? ? 200 ? ? 200 ui programmable equalization (16) ? ?? 16?? 16??16 db t ltr (6) ? ?? 75?? 75??75 s t ltr_ltd_manual (7) ? 15? ? 15? ? 15? ? s t ltd_manual (8) ? ? ? 4000 ? ? 4000 ? ? 4000 ns t ltd_auto (9) ? ? ? 4000 ? ? 4000 ? ? 4000 ns table 1?22. transceiver specifications for stratix iv gx devices (part 4 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/industrial and ?2 commercial speed grade (1) ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?18 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 receiver cdr 3 db bandwidth in lock-to-data (ltd) mode pcie gen1 20 - 35 mhz pcie gen2 40 - 65 mhz (oif) cei phy at 6.375 gbps 20 - 35 mhz xaui 10 - 18 mhz serial rapidio 1.25 gbps 10 - 18 mhz serial rapidio 2.5 gbps 10 - 18 mhz serial rapidio 3.125 gbps 6 - 10 mhz gige 6 - 10 mhz sonet oc12 3 - 6 mhz sonet oc48 14 - 19 mhz receiver buffer and cdr offset cancellation time (per channel) ? ? ? 17000 ? ? 17000 ? ? 17000 recon fig_ clk cycles programmable dc gain dc gain setting = 0 ?0 ??0 ??0 ? db dc gain setting = 1 ?3 ??3 ??3 ? db dc gain setting = 2 ?6 ??6 ??6 ? db dc gain setting = 3 ?9 ??9 ??9 ? db dc gain setting = 4 ?12 ? ?12 ? ?12 ? db eyeq data rate ? 600 ? 3250 600 ? 3250 600 ? 3250 mbps aeq data rate min v id (diff p-p) outer envelope = 600 mv 8b/10b encoded data 2500 ? 6500 2500 ? 6500 ? ? ? mbps decision feedback equalizer (dfe) data rate min v id (diff p-p) outer envelope = 500 mv 3125 ? 6500 3125 ? 6500 ? ? ? mbps table 1?22. transceiver specifications for stratix iv gx devices (part 5 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/industrial and ?2 commercial speed grade (1) ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?19 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 transmitter supported i/o standards 1.4 v pcml, 1.5 v pcml data rate (single width, non-pma direct) ? 600 ? 3750 600 ? 3750 600 ? 3750 mbps data rate (double width, non-pma direct) ? 1000 ? 8500 1000 ? 6500 1000 ? 6375 (20) mbps data rate (single width, pma direct) ? 600 ? 3250 600 ? 3250 600 ? 3250 mbps data rate (double width, pma direct) (10) ? 1000 ? 6500 1000 ? 6500 1000 ? 6375 mbps v ocm 0.65 v setting ? 650 ? ? 650 ? ? 650 ? mv differential on-chip termination resistors 85 ?? setting 85 15% 85 15% 85 15% ? 100 ?? setting 100 15% 100 15% 100 15% ? 120 ?? setting 120 15% 120 15% 120 15% ? 150- ? setting 150 15% 150 15% 150 15% ? differential and common mode return loss pcie gen1 and gen2 (tx v od =4), xaui (tx v od =6), higig+ (tx v od =6), cei sr/lr (tx v od =8), serial rapidio sr (v od =6), serial rapidio lr (v od =8), cpri lv (v od =6), cpri hv (v od =2), obsai (v od =6), sata (v od =4), compliant ? rise time (11) ? 50? 20050? 20050?200 ps fall time (11) ? 50? 20050? 20050?200 ps intra-differential pair skew ? ?? 15?? 15??15 ps intra-transceiver block transmitter channel-to-channel skew 4 pma and pcs bonded mode example: xaui, pcie 4, basic 4 ? ? 120 ? ? 120 ? ? 120 ps table 1?22. transceiver specifications for stratix iv gx devices (part 6 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/industrial and ?2 commercial speed grade (1) ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?20 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 inter-transceiver block transmitter channel-to-channel skew 8 pma and pcs bonded mode example: pcie 8, basic 8 ? ? 500 ? ? 500 ? ? 500 ps inter-transceiver block skew in basic (pma direct) n mode (12) n < 18 channels located across three transceiver blocks with the source cmu pll located in the center transceiver block ? ? 400 ? ? 400 ? ? 400 ps n ? 18 channels located across four transceiver blocks with the source cmu pll located in one of the two center transceiver blocks ? ? 650 ? ? 650 ? ? 650 ps cmu0 pll and cmu1 pll supported data range ? 600 ? 8500 600 ? 6500 600 ? 6375 mbps pll_powerdown minimum pulse width ( tpll_powerdown ) ?1 ? s cmu pll lock time from pll_powerdown de-assertion ? ? ? 100 ? ? 100 ? ? 100 ? s table 1?22. transceiver specifications for stratix iv gx devices (part 7 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/industrial and ?2 commercial speed grade (1) ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?21 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 -3 db bandwidth pcie gen1 2.5 - 3.5 mhz pcie gen2 6 - 8 mhz (oif) cei phy at 4.976 gbps 7 - 11 mhz (oif) cei phy at 6.375 gbps 5 - 10 mhz xaui 2 - 4 mhz serial rapidio 1.25 gbps 3 - 5.5 mhz serial rapidio 2.5 gbps 3 - 5.5 mhz serial rapidio 3.125 gbps 2 - 4 mhz gige 2.5 - 4.5 mhz sonet oc12 1.5 - 2.5 mhz sonet oc48 3.5 - 6 mhz atx pll (6g) supported data range (14) /l = 1 4800-5400 and 6000-6500 4800-5400 and 6000-6500 ?m b p s /l = 2 2400-2700 and 3000-3250 2400-2700 and 3000-3250 ?m b p s /l = 4 1200-1350 and 1500-1625 1200-1350 and 1500-1625 ?m b p s -3 db bandwidth pcie gen 2 1.5 1.5 ? mhz (oif) cei phy at 6.375 gbps 3 - 4.5 3 - 4.5 ? mhz transceiver-fpga fabric interface interface speed (non-pma direct) ? 25? 32525? 32525?250mhz interface speed (pma direct) ? 50? 32550? 32550?325mhz table 1?22. transceiver specifications for stratix iv gx devices (part 8 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/industrial and ?2 commercial speed grade (1) ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?22 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 digital reset pulse width ? minimum is two parallel clock cycles ? notes to ta bl e 1? 22 : (1) the ? 2 speed grade is the fastest speed grade offered in the following stratix iv gx devices: ep4sgx70df29, ep4sgx110df29, ep4sgx11 0ff35, ep4sgx230df29, ep4sgx110ff35, ep4sgx180df29, ep4sgx230ff35, ep4sgx290ff35, ep4sgx180ff35, ep4sgx290fh29, ep4sgx360ff35, and epsgx360fh29. (2) the minimum reconfig_clk frequency is 2.5 mhz if the transceiver channel is configured in transmitter only mode. the minimum reconfig_clk frequency is 37.5 mhz if the transceiver channel is configured in receiver only or receiver and transmitter mode. for more information, refer to the stratix iv dynamic reconfiguration chapter in volume 2 of the stratix iv device handbook . (3) the device cannot tolerate prolonged operation at this absolute maximum. (4) you must use the 1.1-v rx v icm setting if the input serial data standard is lvds. (5) the rate matcher supports only up to 300 parts per million (ppm). (6) time taken to rx_pll_locked goes high from rx_analogreset de-assertion. refer to figure 1?2 on page 1?31 . (7) time for which the cdr must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. refer to figure 1?2 on page 1?31 . (8) time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. refer to figure 1?2 on page 1?31 . (9) time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. refer to figure 1?3 on page 1?31 . (10) a gpll may be required to meet the pma-fpga fabric interface timing above certain data rates. for more information, refer t o the "left/right pll requirements in basic (pma direct) mode" section in the stratix iv gx transceiver clocking chapter. (11) the quartus ii software automatically selects the appropriate slew rate depending on the configured data rate or functional mode. (12) for applications that require low transmit lane-to-lane skew, use basic (pma direct) xn to achieve pma-only bonding across all channels in the link. you can bond all channels on one side of the device by configuring them in basic (pma direct) xn mode. for more information about clocking requirements in this mode, refer to the ?basic (pma direct) mode clocking? section in the stratix iv gx transceiver clocking chapter. (13) pending characterization. (14) the quartus ii software automatically selects the appropriate /l divider depending on the configured data. (15) the maximum transceiver-fpga fabric interface speed of 265.625 mhz is allowed only in basic low-latency pcs mode with a 32-b it interface width. for more information, refer to the ?basic double-width mode configurations? section in the stratix iv transceiver architecture chapter. (16) figure 1?1 shows the ac gain curves for each of the 16 available equalization settings. (17) if your design uses more than one dynamic reconfiguration controller ( altgx_reconfig ) instances to control the transceiver ( altgx ) channels physically located on the same side of the device and if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed. (18) the differential eye opening specification at the receiver input pins assumes that receiver equalization is disabled. if yo u enable receiver equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. use h-spice simulation to der ive the minimum eye opening requirement with receiver equalization enabled. (19) the rise and fall time transition is specified from 20% to 80%. (20) stratix iv gx devices in -4 speed grade support basic mode and deterministic latency mode transceiver configurations up to 6375 mbps. these configurations are shown in the figures 1-90, 1-92, 1-94, 1-96, and 1-101 in the stratix iv transceiver architecture chapter. table 1?22. transceiver specifications for stratix iv gx devices (part 9 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/industrial and ?2 commercial speed grade (1) ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?23 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 figure 1?1 shows the top-to-bottom ac gain curve for equalization settings 0 to 15. table 1?23 lists the stratix iv gt transceiver specifications. figure 1?1. ac gain curves for equalization settings 0 to 15 (bottom to top) table 1?23. transceiver specifications for stratix iv gt devices (part 1 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max reference clock supported i/o standards 1.2 v pcml, 1.5 v pcml, 2.5 v pcml, differential lvpecl, lvds input frequency from refclk input pins ? 50 ? 706.25 50 ? 706.25 50 ? 706.25 mhz phase frequency detector (cmu pll and receiver cdr) ? 50 ? 425 50 ? 425 50 ? 425 mhz absolute v max for a refclk pin ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v operational v max for a refclk pin ? ? ? 1.5 ? ? 1.5 ? ? 1.5 v absolute v min for a refclk pin ? -0.3 ? ? -0.3 ? ? -0.3 ? ? v rise/fall time ? ? ? 0.2 ? ? 0.2 ? ? 0.2 ui chapter 1: dc and switching characteristics for stratix iv devices 1?24 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 duty cycle ? 45 ? 55 45 ? 55 45 ? 55 % peak-to-peak differential input voltage after device configuration ? 200 ? 1600 200 ? 1600 200 ? 1600 mv max peak-to-peak differential input voltage before device configuration ? ? ? 900 ? ? 900 ? ? 900 mv on-chip termination resistors ? ? 100 ? ? 100 ? ? 100 ? ? v icm ? 1200 10% 1200 10% 1200 10% mv transmitter refclk phase noise 10 hz ? ? -50 ? ? -50 ? ? -50 dbc/h z 100 hz ? ? -80 ? ? -80 ? ? -80 dbc/h z 1 khz ? ? -110 ? ? -110 ? ? -110 dbc/h z 10 khz ? ? -120 ? ? -120 ? ? -120 dbc/h z 100 khz ? ? -120 ? ? -120 ? ? -120 dbc/h z ? 1 mhz ? ? -130 ? ? -130 ? ? -130 dbc/h z r ref ??? 2000 1% ? 2000 1% ?? 2000 1% ? ? transceiver clocks calibration block clock frequency ? 10 ? 125 10 ? 125 10 ? 125 mhz reconfig_clk clock frequency dynamic reconfigurat ion clock frequency 2.5/ 37.5 (1) ?? 2.5/ 37.5 (1) ?50 2.5/ 37.5 (1) ?50mhz fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? ? 125 ? mhz delta time between reconfig_clks (14) ???2??2??2ms transceiver block minimum ( gxb_powerdown ) power-down pulse width ??1??1??1?s table 1?23. transceiver specifications for stratix iv gt devices (part 2 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?25 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 receiver supported i/o standards 1.4 v pcml, 1.5 v pcml, 2.5 v pcml, lvpecl, lvds data rate (single width, non-pma direct) ? 600 ? 3750 600 ? 3750 600 ? 3750 mbps data rate (double width, non-pma direct) ? 1000 ? 11300 1000 - 10312. 5 1000 ? 8500 mbps data rate (single width, pma direct) ? 600 - 3250 600 - 3250 600 ? 3250 mbps data rate (double width, pma direct) ? 1000 - 6500 1000 - 6500 1000 ? 6500 mbps absolute v max for a receiver pin (2) ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v operational v max for a receiver pin ? ? ? 1.5 ? ? 1.5 ? ? 1.5 v absolute v min for a receiver pin ? ? -0.4 ? -0.4 ? ? -0.4 ? ? v maximum peak-to- peak differential input voltage v id (diff p-p) before device configuration ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v maximum peak-to- peak differential input voltage v id (diff p-p) after device configuration v icm = 0.82 v setting ? ? 2.7 ? ? 2.7 ? ? 2.7 v v icm = 1.2 v setting (3) ? ? 1.2 ? ? 1.2 ? ? 1.2 v minimum differential eye opening at receiver serial input pins equalization = 0 (4) dc gain =0db 85 ? ? 85 ? ? 85 ? ? mv v icm v icm = 0.82 v setting 820 10% 820 10% 820 10% mv v icm = 1.2 v setting (3) 1200 10% 1200 10% 1200 10% mv table 1?23. transceiver specifications for stratix iv gt devices (part 3 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?26 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 differential on-chip termination resistors 85 ?? setting 85 20% 85 20% 85 20% ? 100 ?? setting 100 20% 100 20% 100 20% ? 120 ?? setting 120 20% 120 20% 120 20% ? 150- ? setting 150 20% 150 20% 150 20% ? differential and common mode return loss pcie (gen 1 and gen 2), xaui, higig+, cei sr/lr, serial rapidio sr/lr, cpri lv/hv, obsai, sata compliant ? programmable ppm detector (5) ?? 62.5, 100, 125, 200, 250, 300, 500, 1000 ppm run length ? ? ? 200 ? ? 200 ? ? 200 ui programmable equalization ???16??16??16db t ltr (6) ? ??75??75??75s t ltr_ltd_manual (7) ? 15 ? ? 15? ? 15? ? s t ltd_manual (8) ? ? ? 4000 ? ? 4000 ? ? 4000 ns t ltd_auto (9) ? ? ? 4000 ? ? 4000 ? ? 4000 ns receiver buffer and cdr offset cancellation time (per channel) ? ? ? 17000 ? ? 17000 ? ? 17000 reconf ig_clk cycles programmable dc gain dc gain setting = 0 ?0 ??0 ??0 ?db dc gain setting = 1 ?3 ??3 ??3 ?db dc gain setting = 2 ?6 ??6 ??6 ?db dc gain setting = 3 ?9 ??9 ??9 ?db dc gain setting = 4 ? 12 ? ?12 ? ?12 ? db eyeq max data rate ? ? ? 4.0 ? ? 4.0 ? ? 4.0 gbps table 1?23. transceiver specifications for stratix iv gt devices (part 4 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?27 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 aeq data rate min v id (diff p-p) outer envelope = 600 mv 8b/10b encoded data 2500 ? 6500 2500 ? 6500 ? ? ? mbps decision feedback equalizer (dfe) data rate min v id (diff p-p) outer envelope = 600 mv 3125 ? 6500 3125 ? 6500 ? ? ? mbps transmitter supported i/o standards 1.4 v pcml data rate (single width, non-pma direct) ? 600 ? 3750 600 ? 3750 600 ? 3750 mbps data rate (double width, non-pma direct) ? 1000 ? 11300 1000 ? 10312. 5 1000 ? 8500 mbps data rate (single width, pma direct) ? 600 ? 3250 600 ? 3250 600 ? 3250 mbps data rate (double width, pma direct) (10) ? 1000 ? 6500 1000 ? 6500 1000 ? 6500 mbps v ocm 0.65 v setting ? 650 ? ? 650 ? ? 650 ? mv differential on-chip termination resistors 85 ?? setting 85 15% 85 15% 85 15% ? 100 ?? setting 100 15% 100 15% 100 15% ? 120 ?? setting 120 15% 120 15% 120 15% ? 150- ? setting 150 15% 150 15% 150 15% ? table 1?23. transceiver specifications for stratix iv gt devices (part 5 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?28 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 differential and common mode return loss pcie gen1 and gen2 (tx v od =4), xaui (tx v od =6), higig+ (tx v od =6), cei sr/lr (tx v od =8), serial rapidio sr (v od =6), serial rapidio lr (v od =8), cpri lv (v od =6), cpri hv (v od =2), obsai (v od =6), sata (v od =4), compliant ? rise time (11) ? 50 ? 200 50 ? 200 50 ? 200 ps fall time (11) ? 50 ? 200 50 ? 200 50 ? 200 ps intra-differential pair skew ? ??15??15??15ps intra-transceiver block transmitter channel-to-channel skew 4 pma and pcs bonded mode example: xaui, pcie, 4, basic 4 ? ? 120 ? ? 120 ? ? 120 ps inter-transceiver block transmitter channel-to-channel skew 8 pma and pcs bonded mode example: pcie 8, basic 8 ? ? 500 ? ? 500 ? ? 500 ps table 1?23. transceiver specifications for stratix iv gt devices (part 6 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?29 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 inter-transceiver block skew in basic (pma direct) n mode (11) n < 18 channels located across three transceiver blocks with the source cmu pll located in the center transceiver block ? ? 400 ? ? 400 ? ? 400 ps n ? 18 channels located across four transceiver blocks with the source cmu pll located in one of the two center transceiver blocks ? ? 650 ? ? 650 ? ? 650 ps cmu pll0 and cmu pll1 supported data range ? 600 ? 11300 600 ? 10312. 5 600 ? 8500 mbps cmu pll lock time from pll_powerdown de-assertion ? ? ? 100 ? ? 100 ? ? 100 ? s atx pll (6g) supported data range /l = 1 4800-5400 and 6000-6500 4800-5400 and 6000-6500 ?mbps /l = 2 2400-2700 and 3000-3250 2400-2700 and 3000-3250 ?mbps /l = 4 1200-1350 and 1500-1625 1200-1350 and 1500-1625 ?mbps atx pll (10g) supported data range ? 9900 ? 11300 9900 ? 10312. 5 ?m b p s transceiver-fpga fabric interface interface speed (non-pma direct) ? 25 ? 325 25 ? 325 25 ? 265.62 5 mhz table 1?23. transceiver specifications for stratix iv gt devices (part 7 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?30 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 interface speed (pma direct) ? 50 ? 325 50 ? 325 50 ? 325 mhz digital reset pulse width ? minimum is two parallel clock cycles ? notes to ta bl e 1? 23 : (1) the minimum reconfig_clk frequency is 2.5 mhz if the transceiver channel is configured in transmitter only mode. the minimum reconfig_clk frequency is 37.5 mhz if the transceiver channel is configured in receiver only or receiver and transmitter mode. for more information, refer to the stratix iv dynamic reconfiguration chapter. (2) the device cannot tolerate prolonged operation at this absolute maximum. (3) you must use the 1.2-v rxv icm setting if the input serial data standard is lvds. (4) the differential eye opening specification at the receiver input pins assumes that receiver equalization is disabled. if you enable receiver equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. use h-spice simulation to derive the minimum eye opening requirement with receiver equalization enabled. (5) the rate matcher supports only up to 300 ppm. (6) time taken to rx_pll_locked goes high from rx_analogreset de-assertion. refer to figure 1?2 on page 1?31 . (7) time for which the cdr must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. refer to figure 1?2 on page 1?31 . (8) time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. refer to figure 1?2 on page 1?31 . (9) time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. refer to figure 1?3 on page 1?31 . (10) a gpll may be required to meet the pma-fpga fabric interface timing above certain data rates. for more information, refer to the "left/right pll requirements in basic (pma direct) mode" section in the stratix iv gx transceiver clocking chapter. (11) the quartus ii software automatically selects the appropriate slew rate depending on the configured data rate or functional mode. (12) for applications that require low transmit lane-to-lane skew, use basic (pma direct) xn to achieve pma-only bonding across all channels in the link. you can bond all channels on one side of the device by configuring them in basic (pma direct) xn mode. for more information about clocking requirements in this mode, refer to the ?basic (pma direct) mode clocking? section in the stratix iv gx transceiver clocking chapter. (13) pending characterization. (14) if your design uses more than one dynamic reconfiguration controller ( altgx_reconfig ) instances to control the transceiver ( altgx ) channels physically located on the same side of the device and if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed. table 1?23. transceiver specifications for stratix iv gt devices (part 8 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?31 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 figure 1?2 shows the lock time parameters in manual mode. 1 ltd = lock-to-data; ltr = lock-to-reference figure 1?3 shows the lock time parameters in automatic mode. figure 1?2. lock time parameters for manual mode ltr ltd invalid data valid data r x_locktodata ltd_manual cdr status r x_dataout r x_pl l_locked r x_analogreset ltr ltr_ltd_manual t t t figure 1?3. lock time parameters for automatic mode ltr ltd invalid data valid data r x_freqlocked ltd_auto r x_dataout cdr status t chapter 1: dc and switching characteristics for stratix iv devices 1?32 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 table 1?24 through table 1?27 lists the typical differential v od termination settings for stratix iv gx and gt devices. table 1?28 lists typical transmitter pre-emphasis levels in db for the first post tap under the following conditions (low-frequency data pattern [five 1s and five 0s] at 6.25 gbps). the levels listed in table 1?28 are a representation of possible pre-emphasis levels under the specified conditions only and that the pre-emphasis levels may change with data pattern and data rate. f to predict the pre-emphasis level for your specific data rate and pattern, run simulations using the stratix iv hssi hspice models. table 1?24. typical v od setting, tx term = 85 ? symbol v od setting (mv) 01234567 v od differential peak-to-peak typical (mv) 170 20% 340 20% 510 20% 595 20% 680 20% 765 20% 850 20% 1020 20% table 1?25. typical v od setting, tx term = 100 ? symbol v od setting (mv) 01234567 v od differential peak-to-peak typical (mv) 200 20% 400 20% 600 20% 700 20% 800 20% 900 20% 1000 20% 1200 20% table 1?26. typical v od setting, tx term = 120 ? symbol v od setting (mv) 0123456 v od differential peak-to-peak typical (mv) 240 20% 480 20% 720 20% 840 20% 960 20% 1080 20% 1200 20% table 1?27. typical v od setting, tx term = 150 ? symbol v od setting (mv) 012345 v od differential peak-to-peak typical (mv) 300 20% 600 20% 900 20% 1050 20% 1200 20% 1350 20% table 1?28. transmitter pre-emphasis levels for stratix iv devices (part 1 of 2) pre- emphasis 1st post-tap setting v od setting 01234567 000000000 1n / a0 . 7000000 chapter 1: dc and switching characteristics for stratix iv devices 1?33 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 2n / a10 . 300000 3n / a1 . 50 . 600000 4n / a20 . 70 . 30000 5 n/a 2.7 1.2 0.5 0.3 0 0 0 6 n/a 3.1 1.3 0.8 0.5 0.2 0 0 7 n/a 3.7 1.8 1.1 0.7 0.4 0.2 0 8 n/a 4.2 2.1 1.3 0.9 0.6 0.3 0 9 n/a 4.9 2.4 1.6 1.2 0.8 0.5 0.2 10 n/a 5.4 2.8 1.9 1.4 1 0.7 0.3 11 n/a 6 3.2 2.2 1.7 1.2 0.9 0.4 12 n/a 6.8 3.5 2.6 1.9 1.4 1.1 0.6 13 n/a 7.5 3.8 2.8 2.1 1.6 1.2 0.6 14 n/a 8.1 4.2 3.1 2.3 1.7 1.3 0.7 15 n/a 8.8 4.5 3.4 2.6 1.9 1.5 0.8 16 n/a n/a 4.9 3.7 2.9 2.2 1.7 0.9 17 n/a n/a 5.3 4 3.1 2.4 1.8 1.1 18 n/a n/a 5.7 4.4 3.4 2.6 2 1.2 19 n/a n/a 6.1 4.7 3.6 2.8 2.2 1.4 20 n/a n/a 6.6 5.1 4 3.1 2.4 1.5 21 n/a n/a 7 5.4 4.3 3.3 2.7 1.7 22 n/a n/a 8 6.1 4.8 3.8 3 2 23 n/a n/a 9 6.8 5.4 4.3 3.4 2.3 24 n/a n/a 10 7.6 6 4.8 3.9 2.6 25 n/a n/a 11.4 8.4 6.8 5.4 4.4 3 26 n/a n/a 12.6 9.4 7.4 5.9 4.9 3.3 27 n/a n/a n/a 10.3 8.1 6.4 5.3 3.6 28 n/a n/a n/a 11.3 8.8 7.1 5.8 4 29 n/a n/a n/a 12.5 9.6 7.7 6.3 4.3 30 n/an/an/an/a11.4 9 7.4n/a 31 n/an/an/an/a12.910 8.2n/a table 1?28. transmitter pre-emphasis levels for stratix iv devices (part 2 of 2) pre- emphasis 1st post-tap setting v od setting 01234567 chapter 1: dc and switching characteristics for stratix iv devices 1?34 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 table 1?29 lists the stratix iv gx transceiver jitter specifications for all supported protocols. for protocols supported by stratix iv gt industrial speed grade devices, refer to the stratix iv gx ?2 commercial speed grade column in table 1?29 . table 1?29. transceiver block jitter specifications for stratix iv gx devices (note 1) , (2) (part 1 of 8) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max sonet/sdh transmit jitter generation (3) peak-to-peak jitter at 622.08 mbps pattern = prbs15 ? ? 0.1 ? ? 0.1 ? ? 0.1 ui rms jitter at 622.08 mbps pattern = prbs15 ? ? 0.01 ? ? 0.01 ? ? 0.01 ui peak-to-peak jitter at 2488.32 mbps pattern = prbs15 ? ? 0.1 ? ? 0.1 ? ? 0.1 ui rms jitter at 2488.32 mbps pattern = prbs15 ? ? 0.01 ? ? 0.01 ? ? 0.01 ui sonet/sdh receiver jitter tolerance (3) jitter tolerance at 622.08 mbps jitter frequency = 0.03 khz pattern = prbs15 > 15 > 15 > 15 ui jitter frequency = 25 khz pattern = prbs15 > 1.5 > 1.5 > 1.5 ui jitter frequency = 250 khz pattern = prbs15 > 0.15 > 0.15 > 0.15 ui jitter tolerance at 2488.32 mbps jitter frequency = 0.06 khz pattern = prbs15 > 15 > 15 > 15 ui jitter frequency = 100 khz pattern = prbs15 > 1.5 > 1.5 > 1.5 ui jitter frequency = 1 mhz pattern = prbs15 > 0.15 > 0.15 > 0.15 ui jitter frequency = 10 mhz pattern = prbs15 > 0.15 > 0.15 > 0.15 ui fibre channel transmit jitter generation (4) , (12) total jitter fc-1 pattern = crpat ? ? 0.23 ? ? 0.23 ? ? 0.23 ui deterministic jitter fc-1 pattern = crpat ? ? 0.11 ? ? 0.11 ? ? 0.11 ui total jitter fc-2 pattern = crpat ? ? 0.33 ? ? 0.33 ? ? 0.33 ui deterministic jitter fc-2 pattern = crpat ? ? 0.2 ? ? 0.2 ? ? 0.2 ui total jitter fc-4 pattern = crpat ? ? 0.52 ? ? 0.52 ? ? 0.52 ui deterministic jitter fc-4 pattern = crpat ? ? 0.33 ? ? 0.33 ? ? 0.33 ui fibre channel receiver jitter tolerance (4) , (13) deterministic jitter fc-1 pattern = cjtpat > 0.37 > 0.37 > 0.37 ui random jitter fc-1 pattern = cjtpat > 0.31 > 0.31 > 0.31 ui chapter 1: dc and switching characteristics for stratix iv devices 1?35 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 sinusoidal jitter fc-1 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui deterministic jitter fc-2 pattern = cjtpat > 0.33 > 0.33 > 0.33 ui random jitter fc-2 pattern = cjtpat > 0.29 > 0.29 > 0.29 ui sinusoidal jitter fc-2 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui deterministic jitter fc-4 pattern = cjtpat > 0.33 > 0.33 > 0.33 ui random jitter fc-4 pattern = cjtpat > 0.29 > 0.29 > 0.29 ui sinusoidal jitter fc-4 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui xaui transmit jitter generation (5) total jitter at 3.125 gbps pattern = cjpat ? ? 0.3 ? ? 0.3 ? ? 0.3 ui deterministic jitter at 3.125 gbps pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui xaui receiver jitter tolerance (5) total jitter ? > 0.65 > 0.65 > 0.65 ui deterministic jitter ? > 0.37 > 0.37 > 0.37 ui peak-to-peak jitter jitter frequency = 22.1 khz > 8.5 > 8.5 > 8.5 ui peak-to-peak jitter jitter frequency = 1.875 mhz > 0.1 > 0.1 > 0.1 ui peak-to-peak jitter jitter frequency = 20 mhz > 0.1 > 0.1 > 0.1 ui pcie transmit jitter generation (6) total jitter at 2.5 gbps (gen1)?1, 4, and 8 compliance pattern ? ? 0.25 ? ? 0.25 ? ? 0.25 ui total jitter at 5 gbps (gen2)?1, 4, and 8 (14) compliance pattern ? ? 0.25 ? ? 0.25 ? ? ? ui pcie receiver jitter tolerance (6) total jitter at 2.5 gbps (gen1) compliance pattern > 0.6 > 0.6 > 0.6 ui total jitter at 5 gbps (gen2) compliance pattern compliant compliant ? ui pcie (gen 1) electrical idle detect threshold v rx-idle-detdiffp-p (15) compliance pattern 65 ? 175 65 ? 175 65 ? 175 ui serial rapidio transmit jitter generation (7) deterministic jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui table 1?29. transceiver block jitter specifications for stratix iv gx devices (note 1) , (2) (part 2 of 8) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?36 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 total jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui serial rapidio receiver jitter tolerance (7) deterministic jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.55 > 0.55 > 0.55 ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1 khz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 1.875 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 > 0.1 > 0.1 ui jitter frequency = 20 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 > 0.1 > 0.1 ui gige transmit jitter generation (8) deterministic jitter (peak-to-peak) pattern = crpat ? ? 0.14 ? ? 0.14 ? ? 0.14 ui total jitter (peak-to-peak) pattern = crpat ? ? 0.279 ? ? 0.279 ? ? 0.279 ui gige receiver jitter tolerance (8) deterministic jitter tolerance (peak-to-peak) pattern = cjpat > 0.4 > 0.4 > 0.4 ui combined deterministic and random jitter tolerance (peak-to-peak) pattern = cjpat > 0.66 > 0.66 > 0.66 ui higig transmit jitter generation (9) deterministic jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ??0.17 ? ? ? ?? ? ui total jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ??0.35 ? ? ? ?? ? ui table 1?29. transceiver block jitter specifications for stratix iv gx devices (note 1) , (2) (part 3 of 8) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?37 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 higig receiver jitter tolerance (9) deterministic jitter tolerance (peak-to-peak) data rate = 3.75 gbps pattern = cjpat > 0.37 ? ? ? ? ? ? ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 3.75 gbps pattern = cjpat > 0.65 ? ? ? ? ? ? ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1 khz data rate = 3.75 gbps pattern = cjpat > 8.5 ? ? ? ? ? ? ui jitter frequency = 1.875mhz data rate = 3.75 gbps pattern = cjpat > 0.1 ? ? ? ? ? ? ui jitter frequency = 20 mhz data rate = 3.75 gbps pattern = cjpat > 0.1 ? ? ? ? ? ? ui (oif) cei transmitter jitter generation (10) total jitter (peak-to-peak) data rate = 6.375 gbps pattern = prbs15 ber = 10 -12 ?? 0.3 ? ? 0.3 ?? n/a ui (oif) cei receiver jitter tolerance (10) deterministic jitter tolerance (peak-to-peak) data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.675 > 0.675 ? ? ? ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 6.375 gbps pattern=prbs31 ber = 10 -12 > 0.988 > 0.988 ? ? ? ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 38.2 khz data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 5 > 5 ? ? ? ui jitter frequency = 3.82 mhz data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.05 > 0.05 ? ? ? ui jitter frequency = 20 mhz data rate= 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.05 > 0.05 ? ? ? ui table 1?29. transceiver block jitter specifications for stratix iv gx devices (note 1) , (2) (part 4 of 8) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?38 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 sdi transmitter jitter generation (11) alignment jitter (peak-to-peak) data rate = 1.485 gbps (hd) pattern = color bar low-frequency roll-off = 100 khz 0.2 ? ? 0.2 ? ? 0.2 ? ? ui data rate = 2.97 gbps (3g) pattern = color bar low-frequency roll-off = 100 khz 0.3 ? ? 0.3 ? ? 0.3 ? ? ui sdi receiver jitter tolerance (11) sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 15 khz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 2> 2> 2ui jitter frequency = 100 khz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 0.3 > 0.3 > 0.3 ui jitter frequency = 148.5 mhz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 0.3 > 0.3 > 0.3 ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 20 khz data rate = 1.485 gbps (hd) pattern = 75% color bar > 1> 1> 1ui jitter frequency = 100 khz data rate = 1.485 gbps (hd) pattern = 75% color bar > 0.2 > 0.2 > 0.2 ui jitter frequency = 148.5 mhz data rate = 1.485 gbps (hd) pattern = 75% color bar > 0.2 > 0.2 > 0.2 ui sas transmit jitter generation (16) total jitter at 1.5 gbps (g1) pattern = cjpat ? ? 0.55 ? ? 0.55 ? ? 0.55 ui deterministic jitter at 1.5 gbps (g1) pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui total jitter at 3.0 gbps (g2) pattern = cjpat ? ? 0.55 ? ? 0.55 ? ? 0.55 ui deterministic jitter at 3.0 gbps (g2) pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui total jitter at 6.0 gbps (g3) pattern = cjpat ? ? 0.25 ? ? 0.25 ? ? 0.25 ui table 1?29. transceiver block jitter specifications for stratix iv gx devices (note 1) , (2) (part 5 of 8) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?39 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 random jitter at 6.0 gbps (g3) pattern = cjpat ? ? 0.15 ? ? 0.15 ? ? 0.15 ui sas receiver jitter tolerance (16) total jitter tolerance at 1.5 gbps (g1) pattern = cjpat > 0.65 > 0.65 > 0.65 ui deterministic jitter tolerance at 1.5 gbps (g1) pattern = cjpat > 0.35 > 0.35 > 0.35 ui sinusoidal jitter tolerance at 1.5 gbps (g1) jitter frequency = 900 khz to 5mhz pattern = cjtpat ber = 1e-12 > 0.1 > 0.1 > 0.1 ui cpri transmit jitter generation (17) total jitter e.6.hv, e.12.hv pattern = cjpat ? ? 0.279 ? ? 0.279 ? ? 0.279 ui e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui deterministic jitter e.6.hv, e.12.hv pattern = cjpat ? ? 0.14 ? ? 0.14 ? ? 0.14 ui e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui cpri receiver jitter tolerance (17) total jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.66 > 0.66 > 0.66 ui deterministic jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.4 > 0.4 > 0.4 ui total jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.65 > 0.65 > 0.65 ui deterministic jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.55 > 0.55 > 0.55 ui table 1?29. transceiver block jitter specifications for stratix iv gx devices (note 1) , (2) (part 6 of 8) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max 1?40 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook volume 4 november 2010 altera corporation obsai transmit jitter generation (18) total jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6mhz pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui deterministic jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6mhz pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui obsai receiver jitter tolerance (18) deterministic jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.55 > 0.55 > 0.55 ui sinusoidal jitter tolerance at 768 mbps jitter frequency = 5.4 khz pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 460 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 ui sinusoidal jitter tolerance at 1536 mbps jitter frequency = 10.9 khz pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 921.6 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 ui table 1?29. transceiver block jitter specifications for stratix iv gx devices (note 1) , (2) (part 7 of 8) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?41 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 table 1?30 lists the transceiver jitter specifications for protocols supported by stratix iv gt devices. sinusoidal jitter tolerance at 3072 mbps jitter frequency = 21.8 khz pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 1843.2 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 ui notes to ta bl e 1? 29 : (1) dedicated refclk pins were used to drive the input reference clocks. (2) the jitter numbers are valid for the stated conditions only. (3) the jitter numbers for sonet/sdh are compliant to the gr-253-core issue 3 specification. (4) the jitter numbers for fibre channel are compliant to the fc-pi-4 specification revision 6.10. (5) the jitter numbers for xaui are compliant to the ieee802.3ae-2002 specification. (6) the jitter numbers for pci express (pipe) (pcie) are compliant to the pcie base specification 2.0. (7) the jitter numbers for serial rapidio are compliant to the rapidio specification 1.3. (8) the jitter numbers for gige are compliant to the ieee802.3-2002 specification. (9) the jitter numbers for higig are compliant to the ieee802.3ae-2002 specification. (10) the jitter numbers for (oif) cei are compliant to the oif-cei-02.0 specification. (11) the hd-sdi and 3g-sdi jitter numbers are compliant to the smpte292m and smpte424m specifications. (12) the fibre channel transmitter jitter generation numbers are compliant to the specification at ? t interoperability point. (13) the fibre channel receiver jitter tolerance numbers are compliant to the specification at ? r interoperability point. (14) you must use the atx pll adjacent to the transceiver channels to meet the transmitter jitter generation compliance in pcie gen2 8 modes. (15) stratix iv pcie receivers are compliant to this specification provided the v tx -c m-dc-activeidle-delta of the upstream transmitter is less than 50mv. (16) the jitter numbers for serial attached scsi (sas) are compliant to the sas-2.1 specification. (17) the jitter numbers for cpri are compliant to the cpri specification v3.0. (18) the jitter numbers for obsai are compliant to the obsai rp3 specification v4.1. table 1?29. transceiver block jitter specifications for stratix iv gx devices (note 1) , (2) (part 8 of 8) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max table 1?30. transceiver jitter specifications for protocols by stratix iv gt devices (part 1 of 2) symbol/ description conditions -1 industrial speed grad -2 industrial speed grade -3 industrial speed grade unit min typ max min typ max min typ max xlaui/caui transmit jitter generation (1) total jitter pattern = prbs- 31 v od = 800 mv refclk = 644.53 mhz 4 (xlaui)/ 10 (caui) channels in basic 1 mode ? ? 0.32 ? ? 0.32 ? ? 0.32 ui deterministic jitter ? ? 0.17 ? ? 0.17 ? ? 0.17 ui 1?42 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook volume 4 november 2010 altera corporation table 1?31 lists the sfi-s transmitter jitter specifications for stratix iv gt devices. xlaui/caui receiver jitter tolerance (1) sinusoidal jitter tolerance jitter frequency = 40 khz pattern = prbs- 31 equalization = disabled ber = 1e-12 > 5 > 5 ? ui jitter frequency ? 4mhz pattern = prbs- 31 equalization = disabled ber = 1e-12 > 0.05 > 0.05 ? ui xfi transmitter jitter generation (2) total jitter at 10.3125 gbps pattern = prbs-31 vod = 800 mv refclk = 644.53 mhz 10 channels in basic 1 mode ??0.3??0.3???ui note to tab l e 1 ?3 0 : (1) the jitter numbers for xlaui/caui are compliant to the ieee p802.3ba specification. (2) stratix iv gt transceivers are compliant to the xfi datacom transmitter jitter specifications in table 9 of xfp revision 4.1 . table 1?30. transceiver jitter specifications for protocols by stratix iv gt devices (part 2 of 2) symbol/ description conditions -1 industrial speed grad -2 industrial speed grade -3 industrial speed grade unit min typ max min typ max min typ max table 1?31. sfi-s transmitter jitter specifications for stratix iv gt devices (note 1) , (2) symbol/description conditions -1 industrial speed grade -2 industrial speed grade -3 industrial speed grade mean mean mean total transmitter jitter at 11.3 gbps pattern = prbs-31 vod = 800 mv refclk = 706.25 mhz 12 channels in basic 1 mode 0.23 ui (3) ?? note to tab l e 1 ?3 1 : (1) dedicated refclk pins were used to drive the input reference clocks. (2) the jitter numbers are valid for stated conditions only. (3) two hundred channels were characterized to derive the mean transmitter jitter specification of 0.23 ui. the maximum jitter across the 200 units characterized was 0.32 ui. chapter 1: dc and switching characteristics for stratix iv devices 1?43 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 transceiver datapath pcs latency f for more information about: basic mode pcs latency, refer to figure 1-90 through figure 1-97 in the stratix iv transceiver architecture chapter. pcie mode pcs latency, refer to figure 1-102 in the stratix iv transceiver architecture chapter. xaui mode pcs latency, refer to figure 1-119 in the stratix iv transceiver architecture chapter. gige mode pcs latency, refer to figure 1-128 in the stratix iv transceiver architecture chapter. sonet/sdh mode pcs latency, refer to figure 1-136 in the stratix iv transceiver architecture chapter. sdi mode pcs latency, refer to figure 1-141 in the stratix iv transceiver architecture chapter. (oif) cei phy mode pcs latency, refer to figure 1-143 in the stratix iv transceiver architecture chapter. core performance specifications this section describes the clock tree, phase-locked loop (pll), digital signal processing (dsp), trimatrix, configuration, and jtag specifications. clock tree specifications table 1?32 lists the clock tree specifications for stratix iv devices. 1 for the stratix iv gt ?1 and ?2 speed grade specifications, refer to the ?2/?2 speed grade column. for the stratix iv gt ?3 speed grade specification, refer to the ?3 speed grade column. table 1?32. clock tree performance for stratix iv devices?preliminary performance unit symbol ?2/?2 speed grade ?3 speed grade ?4 speed grade gclk and rclk 800 700 500 mhz pclk 550 500 450 mhz 1?44 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook volume 4 november 2010 altera corporation pll specifications table 1?33 lists the stratix iv pll specifications when operating in both the commercial junction temperature range (0 to 85c) and the industrial junction temperature range (-40 to 100c). table 1?33. pll specifications for stratix iv devices (part 1 of 2)?preliminary symbol parameter min typ max unit f in input clock frequency (?2/?2x speed grade) 5 ? 800 (1) mhz input clock frequency (?3 speed grade) 5 ? 717 (1) mhz input clock frequency (?4 speed grade) 5 ? 717 (1) mhz f inpfd input frequency to the pfd 5 ? 325 mhz f vco pll vco operating range (?2 speed grade) 600 ? 1600 mhz pll vco operating range (?3 speed grade) 600 ? 1300 mhz pll vco operating range (?4 speed grade) 600 ? 1300 mhz t einduty input clock or external feedback clock input duty cycle 40 ? 60 % f out output frequency for internal global or regional clock (?2/?2x speed grade) ? ? 800 (2) mhz output frequency for internal global or regional clock (?3 speed grade) ? ? 717 (2) mhz output frequency for internal global or regional clock (?4 speed grade) ? ? 717 (2) mhz f out_ext output frequency for external clock output (?2 speed grade) ? ? 800 (2) mhz output frequency for external clock output (?3 speed grade) ? ? 717 (2) mhz output frequency for external clock output (?4 speed grade) ? ? 717 (2) mhz t outduty duty cycle for external clock output (when set to 50%) 45 50 55 % t fcomp external feedback clock compensation time ? ? 10 ns t configpll time required to reconfigure scan chain ? 3.5 ? scanclk cycles t configphase time required to reconfigure phase shift ? 1 ? scanclk cycles f scanclk scanclk frequency ? ? 100 mhz t lock time required to lock from end-of-device configuration or de-assertion of areset ?? 1 ms t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) ?? 1 ms f clbw pll closed-loop low bandwidth ? 0.3 ? mhz pll closed-loop medium bandwidth ? 1.5 ? mhz pll closed-loop high bandwidth (7) ?4 ? mhz t pll_pserr accuracy of pll phase shift ? ? 50 ps t ar eset minimum pulse width on the areset signal 10 ? ? ns t inccj (3) , (4) input clock cycle to cycle jitter (f ref 100 mhz) ? ? 0.15 ui (p-p) input clock cycle to cycle jitter (f ref < 100 mhz) ? ? 750 ps (p-p) t outpj_dc (5) period jitter for dedicated clock output (f out 100 mhz) ? ? 175 ps (p-p) period jitter for dedicated clock output (f out < 100 mhz) ? ? 17.5 mui (p-p) chapter 1: dc and switching characteristics for stratix iv devices 1?45 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 dsp block specifications table 1?34 lists the stratix iv dsp block performance specifications. t outccj_dc (5) cycle to cycle jitter for dedicated clock output (f out 100 mhz) ? ? 175 ps (p-p) cycle to cycle jitter for dedicated clock output (f out <100mhz) ? ? 17.5 mui (p-p) t outpj_io (5) , (8) period jitter for clock output on regular i/o (f out 100 mhz) ? ? 600 ps (p-p) period jitter for clock output on regular i/o (f out <100mhz) ? ? 60 mui (p-p) t outccj_io (5) , (8) cycle to cycle jitter for clock output on regular i/o (f out 100 mhz) ? ? 600 ps (p-p) cycle to cycle jitter for clock output on regular i/o (f out <100mhz) ? ? 60 mui (p-p) t casc_outpj_dc (5) , (6) period jitter for dedicated clock output in cascaded plls (f out 100mhz) ? ? 250 ps (p-p) period jitter for dedicated clock output in cascaded plls (f out < 100mhz) ? ? 25 mui (p-p) f drift frequency drift after pfdena is disabled for duration of 100 us ?? 10 % notes to ta bl e 1? 33 : (1) this specification is limited in the quartus ii software by the i/o maximum frequency. the maximum i/o frequency is differen t for each i/o standard. (2) this specification is limited by the lower of the two: i/o f max or f out of the pll. (3) a high input jitter directly affects the pll output jitter. to have low pll output clock jitter, you must provide a clean cl ock source that is less than 120 ps. (4) f ref is fin/n when n = 1. (5) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999999974404% confidence level). the output jitter specification applies to the intrinsic jitter of the pll, when an input jitter of 30 ps is applied. the external memory interface clock output jitter specifications use a different measurement method and are available in table 1?49 on page 1?58 . (6) the cascaded pll specificat ion is only applicable with the following condition: a. upstream pll: 0.59mhz d upstream pll bw < 1 mhz b. downstream pll: downstream pll bw > 2 mhz (7) high bandwidth pll settings are not supported in external feedback mode. (8) external memory interface clock output jitter specifications use a different measurement method, which is available in table 1?47 on page 1?57 . table 1?33. pll specifications for stratix iv devices (part 2 of 2)?preliminary symbol parameter min typ max unit table 1?34. block performance specifications for stratix iv dsp devices (note 1) ?preliminary mode resources used performance unit number of multipliers ?2/?2 speed grade ?3 speed grade ?4 speed grade 99-bit multiplier 1 520 460 400 mhz 1212-bit multiplier 1 540 500 440 mhz 1818-bit multiplier 1 600 550 480 mhz 1?46 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook volume 4 november 2010 altera corporation trimatrix memory block specifications table 1?35 lists the stratix iv trimatrix memory block specifications. 3636-bit multiplier 1 480 440 380 mhz 1818-bit multiply accumulator 4 490 440 380 mhz 1818-bit multiply adder 4 510 470 410 mhz 1818-bit multiply adder-signed full precision 2 490 450 390 mhz 1818-bit multiply adder with loopback (2) 2 390 350 310 mhz 36-bit shift (32-bit data) 1 490 440 380 mhz double mode 1 480 440 380 mhz notes to ta bl e 1? 34 : (1) maximum is for fully pipelined block with round and saturation disabled. (2) maximum for loopback input registers disabled, round and saturation disabled, and pipeline and output registers enabled. table 1?34. block performance specifications for stratix iv dsp devices (note 1) ?preliminary mode resources used performance unit number of multipliers ?2/?2 speed grade ?3 speed grade ?4 speed grade table 1?35. trimatrix memory block performance specifications for stratix iv devices?preliminary (note 1) (part 1 of 3) memory mode resources used performance aluts trimatrix memory ?2 /?2 commercial/ industrial speed grade ?3 commercial/ industrial speed grade ?4 commercial/ industrial speed grade ?3 industrial speed grade (2) ?4 industrial speed grade (2) unit mlab (3) single port 6410 0 1 600 500 450 500 450 mhz simple dual-port 3220 0 1 600 500 450 500 450 mhz simple dual-port 6410 0 1 600 500 450 500 450 mhz rom 6410 0 1 600 500 450 500 450 mhz rom 3220 0 1 600 500 450 500 450 mhz chapter 1: dc and switching characteristics for stratix iv devices 1?47 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 m9k block (3) single-port 25636 0 1 600 540 475 540 475 mhz simple dual-port 25636 0 1 550 490 420 490 420 mhz simple dual-port 25636, with the read-during-write option set to old data 0 1 375 340 300 340 300 mhz true dual port 51218 0 1 490 430 370 430 370 mhz true dual-port 51218, with the read-during-write option set to old data 0 1 375 335 290 335 290 mhz rom 1 port 0 1 600 540 475 540 475 mhz rom 2 port 0 1 600 540 475 540 475 mhz min pulse width (clock high time) ? ? 750 800 850 800 850 ps min pulse width (clock low time) ? ? 500 625 690 625 690 ps table 1?35. trimatrix memory block performance specifications for stratix iv devices?preliminary (note 1) (part 2 of 3) memory mode resources used performance aluts trimatrix memory ?2 /?2 commercial/ industrial speed grade ?3 commercial/ industrial speed grade ?4 commercial/ industrial speed grade ?3 industrial speed grade (2) ?4 industrial speed grade (2) unit 1?48 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook volume 4 november 2010 altera corporation 1 for the stratix iv gt ?1 and ?2 speed grade specifications, refer to the ?2/?2 speed grade column. for the stratix iv gt ?3 speed grade specification, refer to the ?3 speed grade column. m144k block (3) single-port 2k72 0 1 475 440 380 400 350 mhz simple dual-port 2k72 0 1 465 435 385 375 325 mhz simple dual-port 2k72, with the read-during-write option set to old data 0 1 260 240 205 225 200 mhz simple dual-port 2k64 (with ecc) 0 1 335 300 255 295 250 mhz true dual-port 4k36 0 1 400 375 330 350 310 mhz true dual-port 4k36, with the read-during-write option set to old data 0 1 245 230 205 225 200 mhz rom 1 port 0 1 540 500 435 450 420 mhz rom 2 port 0 1 500 465 400 425 400 mhz min pulse width (clock high time) ? ? 700 755 860 860 950 ps min pulse width (clock low time) ? ? 500 625 690 690 690 ps notes to ta bl e 1? 35 : (1) to achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip pll set to 50% output duty cycle. use the quartus ii software to report timing for this and other memory block clocking schemes. (2) this is only applicable to the stratix iv e and gx devices. (3) when you use the error detection crc feature, there is no degradation in f ma x . table 1?35. trimatrix memory block performance specifications for stratix iv devices?preliminary (note 1) (part 3 of 3) memory mode resources used performance aluts trimatrix memory ?2 /?2 commercial/ industrial speed grade ?3 commercial/ industrial speed grade ?4 commercial/ industrial speed grade ?3 industrial speed grade (2) ?4 industrial speed grade (2) unit chapter 1: dc and switching characteristics for stratix iv devices 1?49 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 configuration and jtag specifications table 1?36 lists the stratix iv configuration mode specifications. table 1?37 lists the jtag timing parameters and values for stratix iv devices. temperature sensing diode specifications table 1?38 lists the specifications for the stratix iv temperature sensing diode. table 1?36. configuration mode specifications for stratix iv devices?preliminary programming mode dclk f max unit min typ max passive serial ? ? 125 mhz fast passive parallel ? ? 125 mhz fast active serial 17 26 40 mhz remote update only in fast as mode 4.3 5.3 10 mhz table 1?37. jtag timing parameters and values for stratix iv devices?preliminary symbol description min max unit t jcp tck clock period 30 ? ns t jch tck clock high time 14 ? ns t jcl tck clock low time 14 ? ns t jpsu (tdi) tdi jtag port setup time 1 ? ns t jpsu (tms) tms jtag port setup time 3 ? ns t jph jtag port hold time 5 ? ns t jpco jtag port clock to output ? 11 (1) ns t jpzx jtag port high impedance to valid output ? 14 (1) ns t jpxz jtag port valid output to high impedance ? 14 (1) ns note to tab l e 1 ?3 7 : (1) a 1 ns adder is required for each v ccio voltage step down from 3.0 v. for example, t jpco = 12 ns if v ccio of the tdo i/o bank = 2.5 v, or 13 ns if it equals 1.8 v. table 1?38. external temperature sensing diode specifications?preliminary description min typ max unit i bias , diode source current 8 ? 500 ? a v bias, voltage across diode 0.3 ? 0.9 v series resistance ? ? < 5 ? diode ideality factor ? ? 1.030 ? 1?50 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook volume 4 november 2010 altera corporation chip-wide reset (dev_clrn) specifications table 1?39 lists the specifications for the stratix iv chip-wide reset ( dev_clrn ). periphery performance this section describes periphery performance, including high-speed i/o and external memory interface. i/o performance supports several system interfaces, such as the lvds high-speed i/o interface, external memory interface, and the pci/pci-x bus interface. general-purpose i/o standards such as 3.3-, 2.5-, 1.8-, and 1.5-lvttl/lvcmos are capable of typical 167 mhz and 1.2 lvcmos at 100 mhz interfacing frequency with 10 pf load. 1 actual achievable frequency depends on design- and system-specific factors. you must perform hspice/ibis simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. high-speed i/o specification table 1?40 lists the high-speed i/o timing for stratix iv devices. table 1?39. chip-wide reset (dev_clrn) specifications description min typ max unit dev_clrn 500 ? ? ? s table 1?40. high-speed i/o specifications (note 1), (2), (10) (part 1 of 3)?preliminary symbol conditions ?2/?2 speed grade ?3 speed grade ?4 speed grade unit min typ max min typ max min typ max f hsclk_in (input clock frequency) true differential i/o standards clock boost factor w = 1 to 40 (3) 5 ? 800 5 ? 717 5 ? 717 mhz f hsclk_in (input clock frequency) single ended i/o standards (9) clock boost factor w = 1 to 40 (3) 5 ? 800 5 ? 717 5 ? 717 mhz f hsclk_in (input clock frequency) single ended i/o standards (10) clock boost factor w = 1 to 40 (3) 5 ? 520 5 ? 420 5 ? 420 mhz f hsclk_out (output clock frequency) ?5? 800 (7) 5? 717 (7) 5? 717 (7) mhz chapter 1: dc and switching characteristics for stratix iv devices 1?51 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 transmitter true differential i/o standards - f hsdr (data rate) serdes factor j = 3 to 10 (8) (4) ?1600 (4) ?1250 (4) ?1250mbps serdes factor j = 2, uses ddr registers (4) ? (4) (4) ? (4) (4) ? (4) mbps serdes factor j = 1, uses an sdr register (4) ? (4) (4) ? (4) (4) ? (4) mbps emulated differential i/o standards with three external output resistor networks - f hsdr (data rate) (5) serdes factor j = 4 to 10 (4) ?1250 (4) ?1152 (4) ?800mbps emulated differential i/o standards with one external output resistor - f hsdr (data rate) (4) ?311 (4) ?200 (4) ?200mbps t x jitter - true differential i/o standards total jitter for data rate, 600 mbps to 1.6 gbps ? ? 160 ? ? 160 ? ? 160 ps total jitter for data rate, < 600 mbps ?? 0.1 ?? 0.1 ?? 0.1 ui t x jitter - emulated differential i/o standards with three external output resistor network total jitter for data rate, 600 mbps to 1.25 gbps ? ? 300 ? ? 300 ? ? 325 ps total jitter for data rate < 600 mbps ?? 0.2 ?? 0.2 ??0.25 ui t x jitter - emulated differential i/o standards with one external output resistor network ? ??0.125??0.15??0.15 ui t duty tx output clock duty cycle for both true and emulated differential i/o standards 45 50 55 45 50 55 45 50 55 % t rise & t fall true differential i/o standards ? ? 160 ? ? 200 ? ? 200 ps emulated differential i/o standards with three external output resistor networks ? ? 250 ? ? 250 ? ? 300 ps emulated differential i/o standards with one external output resistor ? ? 460 ? ? 500 ? ? 500 ps table 1?40. high-speed i/o specifications (note 1), (2), (10) (part 2 of 3)?preliminary symbol conditions ?2/?2 speed grade ?3 speed grade ?4 speed grade unit min typ max min typ max min typ max 1?52 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook volume 4 november 2010 altera corporation 1 for the stratix iv gt ?1 and ?2 speed grade specifications, refer to the ?2/?2 speed grade column. for the stratix iv gt ?3 speed grade specification, refer to the ?3 speed grade column. tccs true differential i/o standards ? ? 100 ? ? 100 ? ? 100 ps emulated differential i/o standards ? ? 250 ? ? 250 ? ? 250 ps receiver true differential i/o standards - f hsdrdpa (data rate) serdes factor j = 3 to 10 150 ? 1600 150 ? 1250 150 ? 1250 mbps f hsdr (data rate) serdes factor j = 3 to 10 (4) ? (6) (4) ? (6) (4) ? (6) mbps serdes factor j = 2, uses ddr registers (4) ? (4) (4) ? (4) (4) ? (4) mbps serdes factor j = 1, uses an sdr register (4) ? (4) (4) ? (4) (4) ? (4) mbps dpa mode dpa run length ? ? ? 10000 ? ? 10000 ? ? 10000 ui soft cdr mode soft-cdr ppm tolerance ? ? ? 300 ? ? 300 ? ? 300 ppm non dpa mode sampling window ? ? ? 300 ? ? 300 ? ? 300 ps notes to ta bl e 1? 40 : (1) when j = 3 to 10, use the serdes block. (2) when j = 1 or 2, bypass the serdes block. (3) clock boost factor (w) is the ratio between input data rate to the input clock rate. (4) the minimum specification depends on the clock source (for example, the pll and clock pin) and the clock routing resource (g lobal, regional, or local) that you use. the i/o differential buffer and input register do not have a minimum toggle rate. (5) you must calculate the leftover timing margin in the receiver by performing link timing closure analysis. you must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin. (6) you can estimate the achievable maximum data rate for non-dpa m ode by performing link timing cl osure analysis. you must cons ider the board skew margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported. (7) this is achieved by using the lvds and dpa clock network. (8) if the receiver with dpa enabled and transmitter are using shared plls, the minimum data rate is 150 mbps. (9) this only applies to dpa and soft-cdr modes. (10) this only applies to lvds source synchronous mode. table 1?40. high-speed i/o specifications (note 1), (2), (10) (part 3 of 3)?preliminary symbol conditions ?2/?2 speed grade ?3 speed grade ?4 speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?53 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 table 1?41 lists the dpa lock time specifications for stratix iv es devices. figure 1?4 shows the dpa lock time specifications with dpa pll calibration enabled. table 1?41. dpa lock time specifications?stratix iv es devices only (note 1) , (2) , (3) standard training pattern number of data tran si tio ns i n one repetition of training pattern number of repetitions per 256 data transitions (4) condition maximum spi-4 00000000001111111111 2 128 without dpa pll calibration 256 data transitions with dpa pll calibration 3x256 data transitions + 2x96 slow clock cycles (5) parallel rapid i/o 00001111 2 128 without dpa pll calibration 256 data transitions with dpa pll calibration 3x256 data transitions + 2x96 slow clock cycles (5) 10010000 4 64 without dpa pll calibration 256 data transitions with dpa pll calibration 3x256 data transitions + 2x96 slow clock cycles (5) miscellaneous 10101010 8 32 without dpa pll calibration 256 data transitions with dpa pll calibration 3x256 data transitions + 2x96 slow clock cycles (5) 01010101 8 32 without dpa pll calibration 256 data transitions with dpa pll calibration 3x256 data transitions + 2x96 slow clock cycles (5) notes to ta bl e 1? 41 : (1) the dpa lock time is for one channel. (2) one data transition is defined as a 0-to-1 or 1-to-0 transition. (3) the dpa lock time applies to both commercial and industrial grade. (4) this is the number of repetition for the stated training pattern to achieve 256 data transitions. (5) slow clock = data rate (mbps)/deserialization factor. figure 1?4. dpa lock time specification with dpa pll calibration enabled rx_dpa_locked rx_reset dpa lock time 256 data transitions 96 slow clock cycles 256 data transitions 256 data transitions 96 slow clock cycles 1?54 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook volume 4 november 2010 altera corporation table 1?42 lists the dpa lock time specifications for stratix iv gx and gt devices. figure 1?5 shows the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate equal to or higher than 1.25 gbps. table 1?43 lists this information in table form. table 1?42. dpa lock time specifications?stratix iv gx and gt devices only (note 1) , (2) , (3) standard training pattern number of data transitions in one repetition of the training pattern number of repetitions per 256 data transitions (4) maximum spi-4 00000000001111111111 2 128 640 data transitions parallel rapid i/o 00001111 2 128 640 data transitions 10010000 4 64 640 data transitions miscellaneous 10101010 8 32 640 data transitions 01010101 8 32 640 data transitions notes to ta bl e 1? 42 : (1) the dpa lock time is for one channel. (2) one data transition is defined as a 0-to-1 or 1-to-0 transition. (3) the dpa lock time stated in the table applies to both commercial and industrial grade. (4) this is the number of repetitions for the stated training pattern to achieve the 256 data transitions. figure 1?5. lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate equal to or higher than 1.25 gbps l v ds soft-cdr/dpa sin u soidal jitter tolerance specification f1 f2 f3 f4 jitter fre quency (hz) jitter amphlitude (ui) 0.1 0.35 8.5 25 chapter 1: dc and switching characteristics for stratix iv devices 1?55 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 table 1?43 lists the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate equal to or higher than 1.25 gbps. figure 1?6 shows the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate less than 1.25 gbps. dll and dqs logic block specifications table 1?44 lists the dll frequency range specifications for stratix iv devices. table 1?43. lvds soft-cdr/dpa sinusoidal jitter mask values for a data rate equal to or higher than 1.25 gbps jitter frequency (hz) sinusoidal jitter (ui) f1 10,000 25.000 f2 17,565 25.000 f3 1,493,000 0.350 f4 50,000,000 0.350 figure 1?6. lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate less than 1.25 gbps 0.1 ui p-p baud/1667 20 mhz fre quency sin usoidal jitter amplitude 20db/dec table 1?44. dll frequency range specifications for stratix iv devices?preliminary (part 1 of 2) frequency mode frequency range (mhz) available phase shift dqs delay buffer mode (1) number of delay chains ?2/?2 speed grade ?3 speed grade ?4 speed grade 0 90-140 90-130 90-120 22.5, 45, 67.5, 90 low 16 1 120-180 120-170 120-160 30, 60, 90, 120 low 12 2 150-220 150-210 150-200 36, 72, 108, 144 low 10 3 180-280 180-260 180-240 45, 90,135, 180 low 8 4 240-350 240-320 240-290 30, 60, 90, 120 high 12 5 290-430 290-380 290-360 36, 72, 108, 144 high 10 6 360-540 360-450 360-450 45, 90, 135, 180 high 8 1?56 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook volume 4 november 2010 altera corporation 1 for the stratix iv gt ?1 and ?2 speed grade specifications, refer to the ?2/?2 speed grade column. for the stratix iv gt ?3 speed grade specification, refer to the ?3 speed grade column. table 1?45 lists the dqs phase offset delay per stage for stratix iv devices. 1 for the stratix iv gt ?1 and ?2 speed grade specifications, refer to the ?2/?2 speed grade column. for the stratix iv gt ?3 speed grade specification, refer to the ?3 speed grade column. table 1?46 lists the dqs phase shift error for stratix iv devices. 7 470-700 470-630 470-590 60, 120, 180, 240 high 6 note to tab l e 1 ?4 4 : (1) low indicates a 6-bit dqs delay setting; high indicates a 5-bit dqs delay setting. table 1?44. dll frequency range specifications for stratix iv devices?preliminary (part 2 of 2) frequency mode frequency range (mhz) available phase shift dqs delay buffer mode (1) number of delay chains ?2/?2 speed grade ?3 speed grade ?4 speed grade table 1?45. dqs phase offset delay per setting for stratix iv devices (note 1) , (2) , (3) speed grade min max unit ?2/?2 7 13 ps ?3 7 15 ps ?4 7 16 ps notes to ta bl e 1? 45 : (1) the valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes 4 to 6. (2) the typical value equals the average of the minimum and maximum values. (3) the delay settings are linear, with a cumulative delay variation of 40 ps for all speed grades. for example, when using a ?2 speed grade and applying a 10 phase offset settings to a 90 phase shift at 400 mhz, the expected average cumulative delay is [625 ps + (10 10.5 ps) 20 ps ] = 730 ps 20 ps. table 1?46. dqs phase shift error specification for dll-delayed clock (t dqs_pserr ) for stratix iv devices (note 1) number of dqs delay buffer ?2/?2x speed grade ?3 speed grade ?4 speed grade unit 1262830ps 2525660ps 3788490ps 4 104 112 120 ps note to tab l e 1 ?4 6 : (1) this error specification is the absolute maximum and minimum error. for example, skew on three dqs delay buffers in a ?2/?2x speed grade is 78 ps or 39 ps. chapter 1: dc and switching characteristics for stratix iv devices 1?57 switching characteristics november 2010 altera corporation stratix iv device handbook volume 4 1 for the stratix iv gt ?1 and ?2 speed grade specifications, refer to the ?2/?2 speed grade column. for the stratix iv gt ?3 speed grade specification, refer to the ?3 speed grade column. table 1?47 lists the memory output clock jitter specifications for stratix iv devices. 1 for the stratix iv gt ?1 and ?2 speed grade specifications, refer to the ?2/?2 speed grade column. for the stratix iv gt ?3 speed grade specification, refer to the ?3 speed grade column. oct calibration block specifications table 1?48 lists the oct calibration block specifications for stratix iv devices. table 1?47. memory output clock jitter specification for stratix iv devices (note 1) , (2) , (3) parameter clock network symbol ?2/?2x speed grade ?3 speed grade ?4 speed grade unit min max min max min max clock period jitter regional t ji t(per) -50 50 -55 55 -55 55 ps cycle-to-cycle period jitter regional t jit(cc) -100 100 -110 110 -110 110 ps duty cycle jitter regional t jit(duty) -50 50 -82.5 82.5 -82.5 82.5 ps clock period jitter global t ji t(per) -75 75 -82.5 82.5 -82.5 82.5 ps cycle-to-cycle period jitter global t jit(cc) -150 150 -165 165 -165 165 ps duty cycle jitter global t jit(duty) -75 75 -90 90 -90 90 ps notes to ta bl e 1? 47 : (1) the memory output clock jitter measurements are for 200 consecutive clock cycles, as sp ecified in the jedec ddr2/ ddr3 sdram standard. (2) the clock jitter specification applies to memory output clock pins generated using differential signal-splitter and ddio cir cuits clocked by a pll output routed on a regional or global clock network as specified. altera recommends using regional clock networks whenever poss ible. (3) the memory output clock jitter stated in table 1?47 is applicable when an input jitter of 30 ps is applied. table 1?48. oct calibration block specifications for stratix iv devices symbol description min typ max unit octusrclk clock required by oct calibration blocks ? ? 20 mhz t octcal number of octusrclk clock cycles required for oct r s /r t calibration ?1000?cycles t octshift number of octusrclk clock cycles required for oct code to shift out ?28?cycles t rs_rt time required between the dyn_term_ctrl and oe signal transitions in a bidirectional i/o buffer to dynamically switch between oct r s and r t ?2.5? ns 1?58 chapter 1: dc and switching characteristics for stratix iv devices i/o timing stratix iv device handbook volume 4 november 2010 altera corporation duty cycle distortion (dcd) specifications table 1?49 lists the worst-case dcd for stratix iv devices. i/o timing altera offers two ways to determine i/o timing?the excel-based i/o timing and the quartus ii timing analyzer. excel-based i/o timing provides pin timing performance for each device density and speed grade. the data is typically used prior to designing the fpga to get an estimate of the timing budget as part of the link timing analysis. the quartus ii timing analyzer provides a more accurate and precise i/o timing data based on the specifics of the design after you complete place-and-route. f the excel-based i/o timing spreadsheet is downloadable from the stratix iv devices literature webpage. programmable ioe delay table 1?50 lists the stratix iv ioe programmable delay settings. table 1?49. worst-case dcd on stratix iv i/o pins symbol ?2/?2 speed grade ?3 speed grade ?4 speed grade unit min max min max min max output duty cycle 45 55 45 55 45 55 % table 1?50. ioe programmable delay for stratix iv devices parameter (1) available settings min offset (2) fast model slow model industrial commercial (3) c2 (3) c3 c4 i3 i4 unit d1 15 0 0.462 0.505 0.732 0.795 0.857 0.801 0.864 ps d2 7 0 0.234 0.232 0.337 0.372 0.407 0.371 0.405 ps d3 7 0 1.700 1.769 2.695 2.927 3.157 2.948 3.178 ps d4 15 0 0.508 0.554 0.813 0.882 0.952 0.889 0.959 ps d5 15 0 0.472 0.500 0.747 0.799 0.875 0.817 0.882 ps d6 6 0 0.186 0.195 0.294 0.319 0.345 0.321 0.347 ps notes to ta bl e 1? 50 : (1) you can set this value in the quartus ii software by selecting d1 , d2 , d3 , d4 , d5 , and d6 in the assignment name column. (2) minimum offset does not include the intrinsic delay. (3) for the ep4sgx530 device density, the ioe programmable delays have an additional 5% maximum offset. chapter 1: dc and switching characteristics for stratix iv devices 1?59 glossary november 2010 altera corporation stratix iv device handbook volume 4 programmable output buffer delay table 1?51 lists the delay chain settings that control the rising and falling edge delays of the output buffer. the default delay is 0 ps. glossary table 1?52 lists the glossary for this chapter. table 1?51. programmable output buffer delay (note 1) symbol parameter typical unit d outbuf rising and/or falling edge delay 0 (default) ps 50 ps 100 ps 150 ps note to tab l e 1 ?5 1 : (1) you can set the programmable output buffer delay in the quartus ii software by setting the output buffer delay control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the output buffer delay assignment. table 1?52. glossary table (part 1 of 5) letter subject definitions a ?? b ?? c ?? 1?60 chapter 1: dc and switching characteristics for stratix iv devices glossary stratix iv device handbook volume 4 november 2010 altera corporation d differential i/o standards receiver input waveforms transmitter output waveforms e ?? f f hsclk left/right pll input clock frequency. f hsdr high-speed i/o block: maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa high-speed i/o block: maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. g ?? h ?? i ?? table 1?52. glossary table (part 2 of 5) letter subject definitions single-ended waveform differential waveform positive channel (p) = v ih negative channel (n) = v il ground v id v id v id p ? n = 0 v v cm single-ended waveform differential waveform positive channel (p) = v oh negative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm chapter 1: dc and switching characteristics for stratix iv devices 1?61 glossary november 2010 altera corporation stratix iv device handbook volume 4 j j high-speed i/o block: deserialization factor (width of parallel data bus). jtag timing specifications jtag timing specifications: k ?? l ?? m ?? n ?? o ?? p pll specifications diagram of pll specifications (1) note: (1) core clock can only be fed by dedicated clock input pins or pll outputs. q ?? rr l receiver differential input discrete resistor (external to stratix iv device). table 1?52. glossary table (part 3 of 5) letter subject definitions tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms core clock external feedback reconfigurable in user mode key clk n m pfd switchover vco cp lf clkout pins gclk rclk f inpfd f in f vco f out f out_ext counters c0..c9 1?62 chapter 1: dc and switching characteristics for stratix iv devices glossary stratix iv device handbook volume 4 november 2010 altera corporation s sw (sampling window) timing diagram?the period of time during which the data must be valid in order to capture it correctly. the setup and hold times determine the ideal strobe position within the sampling window, as shown: single-ended voltage referenced i/o standard the jedec standard for sstl and hstl i/o defines both the ac and dc input signal values. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. after the receiver input has crossed the ac value, the receiver changes to the new logic state. the new logic state is then maintained as long as the input stays beyond the ac threshold. this approach is intended to provide predictable receiver timing in the presence of input waveform ringing, as shown: single-ended voltage referenced i/o standard t t c high-speed receiver/transmitter input and output clock period. tccs (channel- to-channel-skew) the timing difference between the fastest and slowest output edges, including t co variation and clock skew, across channels driven by the same pll. the clock is included in the tccs measurement (refer to the timing diagram figure under sw in this table). t duty high-speed i/o block: duty cycle on high-speed transmitter output clock. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ) t fall signal high-to-low transition time (80-20%) t inccj cycle-to-cycle jitter tolerance on the pll clock input t outpj_io period jitter on the general purpose i/o driven by a pll t outpj_dc period jitter on the dedicated clock output driven by a pll t rise signal low-to-high transition time (20-80%) u ?? table 1?52. glossary table (part 4 of 5) letter subject definitions bit time 0.5 x tccs rskm sampling window (sw) rskm 0.5 x tccs v ih ( ac ) v ih(dc) v ref v il(dc) v il(ac ) v oh v ol v ccio v ss chapter 1: dc and switching characteristics for stratix iv devices 1?63 document revision history november 2010 altera corporation stratix iv device handbook volume 4 document revision history table 1?53 lists the revision history for this chapter. v v cm(dc) dc common mode input voltage. v ic m input common mode voltage?the common mode of the differential signal at the receiver. v id input differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. v dif(ac) ac differential input voltage?minimum ac input differential voltage required for switching. v dif(dc) dc differential input voltage? minimum dc input differential voltage required for switching. v ih voltage input high?the minimum positive voltage applied to the input which is accepted by the device as a logic high. v ih (ac ) high-level ac input voltage v ih (dc) high-level dc input voltage v il voltage input low?the maximum positive voltage applied to the input which is accepted by the device as a logic low. v il(a c) low-level ac input voltage v il(d c) low-level dc input voltage v ocm output common mode voltage?the common mode of the differential signal at the transmitter. v od output differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. v swing differential input voltage v x input differential cross point voltage v ox output differential cross point voltage w w high-speed i/o block: clock boost factor x ?? y ?? z ?? table 1?52. glossary table (part 5 of 5) letter subject definitions table 1?53. document revision history (part 1 of 2) date version changes november 2010 4.5 updated ta bl e 1? 29 . updated chapter title. minor text edits. september 2010 4.4 applied new template. updated ta bl e 1? 1 and table 1?5 . july 2010 4.3 updated table 1?7, table 1?22, table 1?23, table 1?33, table 1?35, table 1?36, and table 1?40. added table 1?39. changed ?pci express? to ?pcie? throughout. minor text edits 1?64 chapter 1: dc and switching characteristics for stratix iv devices document revision history stratix iv device handbook volume 4 november 2010 altera corporation march 2010 4.2 updated table 1?22, table 1?23, table 1?30, table 1?46, and table 1?49. added table 1?31. minor text edits. february 2010 4.1 updated table 1?11, table 1?22, table 1?23, table 1?24, table 1?25, table 1?26, table 1?27, table 1?29, table 1?32, table 1?33, table 1?34, table 1?35, table 1?39, table 1?40, table 1?43, table 1?46, and table 1?49. added stratix iv gt speed grade note to table 1?32, table 1?35, table 1?39, table 1?43, table 1?44, table 1?45, and table 1?46. added table 1?28 and table 1?30. minor text edits. november 2009 4.0 added table 1?9, table 1?15, table 1?38, and table 1?39. added figure 1?5 and figure 1?6. added the ?transceiver datapath pcs latency? section. updated the ?electrical characteristics?, ?operating conditions?, and ?i/o timing? sections. all tables updated except table 1?16, table 1?24, table 1?25, table 1?26, table 1?27, table 1?33, table 1?34, and table 1?45. updated figure 1?2 and figure 1?3. updated equation 1?1. deleted table 1-28, table 1-29, table 1-30, table 1-42, table 1-43, and table 1-44. minor text edits. june 2009 3.1 added ?preliminary specifications? to the footer of each page. updated table 1?1, table 1?2, table 1?7, table 1?10, table 1?11, table 1?12, table 1?21, table 1?22, table 1?23, table 1?25, table 1?37, table 1?38, table 1?39, table 1?40, and table 1?44. minor text edits. march 2009 3.0 replaced t able 1?31 and table 1?37. updated table 1?1, table 1?2, table 1?5, table 1?19, table 1?41, table 1?44, table 1?45, table 1?49, and table 1?51. added table 1?21, table 1?46, and table 1?47 added figure 1?3. removed ?timing model?, ?preliminary and final timing?, ?i/o timing measurement methodology?, ?i/o default capacitive loading?, and ?referenced documents? sections. december 2008 2.1 minor changes. november 2008 2.0 minor text edits. updated table 1?19, table 1?32, table 1?34 - table 1?39. minor text edits. august 2008 1.1 updated table 1?1, table 1?2, table 1?4, table 1?5, and table 1?26. removed figures from ?transceiver performance specifications? on page 1?10 that are repeated in the glossary. minor text edits and an additional note to table 1?26. may 2008 1.0 initial release. table 1?53. document revision history (part 2 of 2) date version changes chapter 1: dc and switching characteristics for stratix iv devices 1?65 document revision history november 2010 altera corporation stratix iv device handbook volume 4 stratix iv device handbook volume 4 september 2010 siv54002-1.4 subscribe ? 2010 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megacore, nios, quartus and stratix are reg. u.s. pat. & tm. off. and/or trademarks of altera corporation in the u.s. and other countries. all other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance with altera?s standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability aris ing out of the app lication or u se of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advi sed to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 2. addendum to the stratix iv device handbook this chapter describes changes to the published version of the stratix iv device handbook. it describes changes to the ?adaptive equalization (aeq)? section of the stratix iv dynamic reconfiguration chapter and the ?power-on reset circuitry? and ?power-on reset specifications? sections of the power-on reset in stratix iv devices chapter. table 2?1 lists the changes and chapters described in this addendum. 1 any information not contained in this addendum is considered the same as the information contained in the published version of the stratix iv device handbook . adaptive equalization (aeq) table 2?2 lists the changes to the ?adaptive equalization (aeq)? section, page 5-74, of the stratix iv dynamic reconfiguration chapter. table 2?1. changes to the stratix iv handbook change chapter adaptive equalization (aeq) stratix iv dynamic reconfiguration decision feedback equalization (dfe) ? power-on reset circuitry hot socketing and power-on reset in stratix iv devices power-on reset specifications hot socketing and power-on reset in stratix iv devices table 2?2. changes to the adaptive equalization (aeq) section old version correction subsection: ?continuous mode for single channel? this feature is not supported. subsection: ?powerdown for a single channel? this feature is not supported. figure 5-40: ?timing diagram for powering down the aeq for a single channel (mode 3)? powering down the aeq circuitry and reading out the translated manual equalization setting are not supported. september 2010 siv54002-1.4 2?2 chapter 2: addendum to the stratix iv device handbook decision feedback equalization (dfe) stratix iv device handbook volume 4 september 2010 altera corporation stratix iv gx and gt devices only support one-time adaptation mode for the aeq feature. figure 2?1 shows the aeq timing diagram in this mode. after assertion of write_all signals, the dynamic reconfiguration controller performs the following steps sequentially: 1. powers down the receiver buffer and performs offset calibration for the target channel. 2. powers up the receiver buffer and runs the convergence algorithm to set the appropriate equalization settings. 3. puts the aeq circuitry in stand-by mode maintaining the converged equalization setting. in standby mode, no further adaptation occurs. if you observe bit errors over time with the converged equalization settings, you can re-initiate one-time adaptation by following the timing diagram shown in figure 2?1 . each time you re-initiate one-time adaptation, the receiver buffer is powered down for offset calibration, thereby interrupting the link during this time. decision feedback equalization (dfe) the dfe feature is available in stratix iv gx and gt devices. use this feature to improve the high frequency signal-to-noise ratio by compensating for inter-symbol interference (isi). the dfe feature boosts the high frequency components of a signal without noise amplification. f for more information about the dfe feature, refer to an 612: decision feedback equalization in stratix iv devices which will be available october 2010. figure 2?1. aeq timing diagram in one-time adaptation mode w rite_all reconfig_mode_sel[3:0] logical_channel_address[] b usy 4 (logical channel 4) 4?b1001 indicates aeq con v ergence and entry into stand-by mode offset calibration and aeq con v ergence chapter 2: addendum to the stratix iv device handbook 2?3 power-on reset circuitry september 2010 altera corporation stratix iv device handbook volume 4 power-on reset circuitry table 2?3 lists the change to the ?power-on reset circuitry? section, page 9-4 of the hot socketing and power-on reset in stratix iv devices chapter. the change is noted in bold. f all other information not contained in this addendum remains the same as in the ?power-on reset circuitry? section of the hot socketing and power-on reset in stratix iv devices chapter. power-on reset specifications table 2?4 lists the change to the ?power-on reset specifications? section, page 9-5 of the hot socketing and power-on reset in stratix iv devices chapter. the change is noted in bold. f all other information not contained in this addendum remains the same as in the ?power-on reset specifications? section of the hot socketing and power-on reset in stratix iv devices chapter. document revision history table 2?5 lists the revision history for this chapter. table 2?3. change to the power-on reset circuitry section old version corrected version ?altera recommends powering up v cc before v ccaux .? ?altera requires powering up v cc before v ccaux .? table 2?4. change to the power-on reset specifications section old version corrected version ?altera recommends powering up v cc before v ccaux .? ?altera requires powering up v cc before v ccaux .? table 2?5. document revision history (part 1 of 2) date version changes september 2010 1.4 added corrections for the adaptive equalization (aeq) section of the stratix iv dynamic reconfiguration chapter. added new information for the decision feedback equalization (dfe) feature. april 2010 1.3 added corrections for the ?power-on reset circuitry? and ?power-on reset specifications? sections to of the hot socketing and power-on reset in stratix iv devices chapter. 2?4 chapter 2: addendum to the stratix iv device handbook document revision history stratix iv device handbook volume 4 september 2010 altera corporation march 2010 1.2 moved the ?power-on reset circuitry?, ?power-on reset specifications?, ?correct power-up sequence for production devices?, and ?correct power-up sequence for production devices? sections to the hot socketing and power-on reset in stratix iv devices chapter. moved the ?power-on reset circuit? and ?jtag tms and tdi pin pull-up resistor value specification? sections to the configuration, design security, remote system upgrades with stratix iv devices chapter. moved the ?summary of oct assignments? section to the i/o features in stratix iv devices chapter. february 2010 1.1 added the ?power-on reset circuitry?, ?power-on reset specifications?, ?correction to por signal pulse width delay times?, ?correct power-up sequence for production devices?, ?power-on reset circuit?, ?summary of oct assignments?, and ?jtag tms and tdi pin pull-up resistor value specification? sections. minor text edits. november 2009 1.0 stratix iv gx enhanced transceiver data rate specifications in ? 4 commercial speed grade. initial release. table 2?5. document revision history (part 2 of 2) date version changes november 2010 altera corporation stratix iv device handbook volume 4 additional information this chapter provides additional information about the document and altera. about this handbook this handbook provides comprehensive information about the altera ? stratix ? iv family of devices. how to contact altera to locate the most up-to-date information about altera products, refer to the following table. typographic conventions the following table shows the typographic conventions this document uses. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature non-technical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note to table: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicate command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicate document titles. for example, stratix iv design guidelines . italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, 2?2 additional information typographic conventions stratix iv device handbook volume 4 november 2010 altera corporation courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . the suffix n denotes an active-low signal. for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). r an angled arrow instructs you to press the enter key. 1., 2., 3., and a., b., c., and so on numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. a question mark directs you to a software help system with related information. f the feet direct you to another document or website with related information. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. the envelope links to the email subscription management center page of the altera website, where you can sign up to receive update notifications for altera documents. visual cue meaning |
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